* clk-spacemit:
clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
reset: spacemit: add support for SpacemiT CCU resets
clk: spacemit: mark K1 pll1_d8 as critical
clk: spacemit: define three reset-only CCUs
clk: spacemit: set up reset auxiliary devices
soc: spacemit: create a header for clock/reset registers
dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
* clk-allwinner:
clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()
clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll
clk: sunxi-ng: v3s: Fix de clock definition
clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset
dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
* clk-amlogic:
clk: amlogic: s4: remove unused data
clk: amlogic: drop clk_regmap tables
clk: amlogic: get regmap with clk_regmap_init
clk: amlogic: remove unnecessary headers
clk: amlogic: axg-audio: use the auxiliary reset driver
Stephen Boyd [Tue, 29 Jul 2025 22:18:13 +0000 (15:18 -0700)]
Merge branches 'clk-bindings', 'clk-cleanup', 'clk-pwm', 'clk-hw-device', 'clk-xilinx' and 'clk-adi' into clk-next
- Support atomic PWMs in the PWM clk driver
- clk_hw_get_dev() and clk_hw_get_of_node() helpers
* clk-bindings: (30 commits)
dt-bindings: clock: convert lpc1850-cgu.txt to yaml format
dt-bindings: clock: Convert qca,ath79-pll to DT schema
dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema
dt-bindings: clock: Convert moxa,moxart-clock to DT schema
dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema
dt-bindings: clock: Convert maxim,max9485 to DT schema
dt-bindings: clock: Convert qcom,krait-cc to DT schema
dt-bindings: clock: qcom: Remove double colon from description
dt-bindings: clock: convert lpc1850-ccu.txt to yaml format
dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema
dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema
dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema
dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema
dt-bindings: clock: Convert marvell,berlin2-clk to DT schema
dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema
dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema
dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema
dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema
dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema
dt-bindings: clock: Convert lsi,axm5516-clks to DT schema
...
* clk-cleanup: (29 commits)
clk: clocking-wizard: Fix the round rate handling for versal
clk: Fix typos
clk: tegra: periph: Make tegra_clk_periph_ops static
clk: tegra: periph: Fix error handling and resolve unsigned compare warning
clk: imx: scu: convert from round_rate() to determine_rate()
clk: imx: pllv4: convert from round_rate() to determine_rate()
clk: imx: pllv3: convert from round_rate() to determine_rate()
clk: imx: pllv2: convert from round_rate() to determine_rate()
clk: imx: pll14xx: convert from round_rate() to determine_rate()
clk: imx: pfd: convert from round_rate() to determine_rate()
clk: imx: frac-pll: convert from round_rate() to determine_rate()
clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
clk: imx: fixup-div: convert from round_rate() to determine_rate()
clk: imx: cpu: convert from round_rate() to determine_rate()
clk: imx: busy: convert from round_rate() to determine_rate()
clk: imx: composite-93: remove round_rate() in favor of determine_rate()
clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
clk: bcm: bcm2835: convert from round_rate() to determine_rate()
MAINTAINERS: Include clk.py under COMMON CLK FRAMEWORK entry
clk: ti: Simplify ti_find_clock_provider()
...
* clk-pwm:
clk: pwm: Make use of non-sleeping PWMs
clk: pwm: Don't reconfigure running PWM at probe time
clk: pwm: Convert to use pwm_apply_might_sleep()
clk: pwm: Let .get_duty_cycle() return the real duty cycle
* clk-hw-device:
clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests
clk: tests: Make clk_register_clk_parent_data_device_driver() common
clk: add a clk_hw helpers to get the clock device or device_node
* clk-xilinx:
clk: xilinx: vcu: Update vcu init/reset sequence
clk: xilinx: vcu: unregister pll_post only if registered correctly
* clk-adi:
clk: clk-axi-clkgen: fix coding style issues
clk: clk-axi-clkgen move to min/max()
clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime
include: adi-axi-common: add new helper macros
include: linux: move adi-axi-common.h out of fpga
clk: clk-axi-clkgen: make sure to include mod_devicetable.h
clk: clk-axi-clkgen: fix fpfd_max frequency for zynq
clk: clocking-wizard: Fix the round rate handling for versal
Fix the `clk_round_rate` implementation for Versal platforms by calling
the Versal-specific divider calculation helper. The existing code used
the generic divider routine, which results in incorrect round rate.
clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
Return 0 instead of -EINVAL if function ccu_pll_recalc_rate() fails to
get correct rate entry. Follow .recalc_rate callback documentation
as mentioned in include/linux/clk-provider.h for error return value.
Signed-off-by: Akhilesh Patil <akhilesh@ee.iitb.ac.in> Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC") Reviewed-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Alex Elder <elder@riscstar.com> Link: https://lore.kernel.org/r/aIBzVClNQOBrjIFG@bhairav-test.ee.iitb.ac.in Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: tegra: periph: Make tegra_clk_periph_ops static
Reduce symbol visibility by converting tegra_clk_periph_ops to static.
Removed the extern declaration from clk.h as the symbol is now locally
scoped to clk-periph.c.
Brian Masney [Thu, 10 Jul 2025 21:10:45 +0000 (17:10 -0400)]
clk: imx: scu: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
This driver also implements both the determine_rate() and round_rate()
clk ops, and the round_rate() clk ops is deprecated. When both are
defined, clk_core_determine_round_nolock() from the clk core will only
use the determine_rate() clk ops, so let's remove the round_rate() clk
ops since it's unused.
Brian Masney [Thu, 10 Jul 2025 21:10:44 +0000 (17:10 -0400)]
clk: imx: pllv4: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Thu, 10 Jul 2025 21:10:43 +0000 (17:10 -0400)]
clk: imx: pllv3: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Thu, 10 Jul 2025 21:10:42 +0000 (17:10 -0400)]
clk: imx: pllv2: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Thu, 10 Jul 2025 21:10:41 +0000 (17:10 -0400)]
clk: imx: pll14xx: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Thu, 10 Jul 2025 21:10:40 +0000 (17:10 -0400)]
clk: imx: pfd: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Thu, 10 Jul 2025 21:10:39 +0000 (17:10 -0400)]
clk: imx: frac-pll: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Thu, 10 Jul 2025 21:10:38 +0000 (17:10 -0400)]
clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Thu, 10 Jul 2025 21:10:37 +0000 (17:10 -0400)]
clk: imx: fixup-div: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
The change to call fixup_div->ops->determine_rate() instead of
fixup_div->ops->round_rate() was done by hand.
Brian Masney [Thu, 10 Jul 2025 21:10:36 +0000 (17:10 -0400)]
clk: imx: cpu: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Thu, 10 Jul 2025 21:10:35 +0000 (17:10 -0400)]
clk: imx: busy: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
The change to call busy->div_ops->determine_rate() instead of
busy->div_ops->round_rate() was done by hand.
Brian Masney [Thu, 10 Jul 2025 21:10:34 +0000 (17:10 -0400)]
clk: imx: composite-93: remove round_rate() in favor of determine_rate()
This driver implements both the determine_rate() and round_rate() clk
ops, and the round_rate() clk ops is deprecated. When both are defined,
clk_core_determine_round_nolock() from the clk core will only use the
determine_rate() clk ops, so let's remove the round_rate() clk ops since
it's unused.
Brian Masney [Thu, 10 Jul 2025 21:10:33 +0000 (17:10 -0400)]
clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
This driver implements both the determine_rate() and round_rate() clk
ops, and the round_rate() clk ops is deprecated. When both are defined,
clk_core_determine_round_nolock() from the clk core will only use the
determine_rate() clk ops, so let's remove the round_rate() clk ops since
it's unused.
Brian Masney [Thu, 3 Jul 2025 23:22:25 +0000 (19:22 -0400)]
clk: bcm: bcm2835: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Frank Li [Fri, 6 Jun 2025 16:24:09 +0000 (12:24 -0400)]
dt-bindings: clock: convert lpc1850-cgu.txt to yaml format
Convert lpc1850-cgu.txt to yaml format.
Additional changes:
- remove extra clock source nodes in example.
- remove clock consumer in example.
- remove clock-output-names and clock-clock-indices from required list to
match existed dts.
Florian Fainelli [Wed, 25 Jun 2025 23:10:38 +0000 (16:10 -0700)]
MAINTAINERS: Include clk.py under COMMON CLK FRAMEWORK entry
Include the GDB scripts file under scripts/gdb/linux/clk.py under the
COMMON CLK subsystem since it parses internal data structures that
depend upon that subsystem.
Stephen Boyd [Mon, 21 Jul 2025 17:32:46 +0000 (10:32 -0700)]
Merge tag 'clk-meson-v6.17-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet:
- Use the auxiliary reset controller implementation in the
Amlogic axg-audio, instead of implementing the reset
controller in drivers/clk
- Drop unnecessary clock controller headers for Amlogic drivers
- Drop clock controller big regmap tables in the Amlogic drivers
* tag 'clk-meson-v6.17-1' of https://github.com/BayLibre/clk-meson:
clk: amlogic: s4: remove unused data
clk: amlogic: drop clk_regmap tables
clk: amlogic: get regmap with clk_regmap_init
clk: amlogic: remove unnecessary headers
clk: amlogic: axg-audio: use the auxiliary reset driver
clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests
clk: tests: Make clk_register_clk_parent_data_device_driver() common
clk: add a clk_hw helpers to get the clock device or device_node
Stephen Boyd [Mon, 21 Jul 2025 17:26:31 +0000 (10:26 -0700)]
Merge tag 'sunxi-clk-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Chen-Yu Tsai:
- Add Allwinner A523's missing PPU0 reset (both DT binding and
driver) The binding change is shared with the soc tree.
- Fix Allwinner V3s DE clock mux field width
- Stop passing rate change requests to parent for Allwinner V3s
DE clock
- Force and lock Allwinner V3s DE and TCON clocks to the same
parent, the video PLL
* tag 'sunxi-clk-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()
clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()
clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll
clk: sunxi-ng: v3s: Fix de clock definition
clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset
dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
Brian Masney [Thu, 3 Jul 2025 23:22:34 +0000 (19:22 -0400)]
clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
I manually fixed up one minor formatting issue that occurred after
applying the semantic patch:
Brian Masney [Thu, 3 Jul 2025 23:22:33 +0000 (19:22 -0400)]
clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Thu, 3 Jul 2025 23:22:32 +0000 (19:22 -0400)]
clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Brian Masney [Thu, 3 Jul 2025 23:22:31 +0000 (19:22 -0400)]
clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll
It appears (based on experimentation) that both the de and tcon clocks
need to have the same parent for the two units to work together.
Assign them both to the video pll by manually clearing the parent
selection bits (effectively setting index 0) and marking the clocks
with the CLK_SET_RATE_NO_REPARENT flag, which ensures that they will
never use a different parent.
The video pll is also a possible parent for the camera subsystem,
but it can use the dedicated isp pll if needed so there should be
no negative side-effect due to this change.
Note that ccu_mux_helper_set_parent cannot be used at this stage as
it requires the clock driver to be initialized and this configuration
is best done before the clock driver is available to consumers.
The de clock is marked with CLK_SET_RATE_PARENT, which is really not
necessary (as confirmed from experimentation) and significantly
restricts flexibility for other clocks using the same parent.
In addition the source selection (parent) field is marked as using
2 bits, when it the documentation reports that it uses 3.
Stephen Boyd [Sun, 13 Jul 2025 16:53:50 +0000 (09:53 -0700)]
Merge tag 'spacemit-clk-for-6.17-1' of https://github.com/spacemit-com/linux into clk-spacemit
Pull SpacemiT clk driver updates from Yixun Lan:
- Mark SpacemiT pll1_d8 clk as critical
- Add reset support for SpacemiT K1 SoC
* tag 'spacemit-clk-for-6.17-1' of https://github.com/spacemit-com/linux:
reset: spacemit: add support for SpacemiT CCU resets
clk: spacemit: mark K1 pll1_d8 as critical
clk: spacemit: define three reset-only CCUs
clk: spacemit: set up reset auxiliary devices
soc: spacemit: create a header for clock/reset registers
dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
Stephen Boyd [Sun, 13 Jul 2025 16:19:45 +0000 (09:19 -0700)]
Merge tag 'renesas-clk-for-v6.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add Expanded Serial Peripheral Interface (xSPI) clocks and resets on
Renesas RZ/V2H(P) and RZ/V2N
- Add SPI (RSPI) clocks and resets on Renesas RZ/V2H(P)
- Add SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H
- Add Ethernet clocks and resets on Renesas RZ/G3E
- Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H
(R9A09G087) SoCs
- Add Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N
- Add timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on
Renesas RZ/V2N
- Rework Module Stop and Power Domain support on the Renesas
RZ/G2L family of SoCs (especially on RZ/G3S)
- Add I3C clocks and resets on Renesas RZ/G3E
* tag 'renesas-clk-for-v6.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (42 commits)
clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well
clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
clk: renesas: r9a09g057: Add XSPI clock/reset
clk: renesas: r9a09g056: Add XSPI clock/reset
clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting
clk: renesas: r9a09g057: Add support for xspi mux and divider
clk: renesas: r9a09g056: Add support for xspi mux and divider
clk: renesas: r9a09g077: Add RIIC module clocks
clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
clk: renesas: r9a09g057: Add entries for the RSPIs
dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
clk: renesas: rzv2h: Add missing include file
clk: renesas: rzv2h: Use devm_kmemdup_array()
clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
clk: renesas: r9a09g077: Add PCLKL core clock
dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
...
clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well
If MSTOP is not added for both clocks in a coupled pair, and the clocks
are not disabled in the reverse order of their enable sequence, the MSTOP
may remain enabled when disabling the clocks.
This happens because rzg2l_mod_clock_endisable() executes for coupled
clocks only when a single clock from the pair is enabled. If one clock has
no MSTOP defined, it can result in the MSTOP configuration being left
active when the clocks are disabled out of order (i.e., not in the reverse
order of enabling).
John Madieu [Wed, 2 Jul 2025 00:57:03 +0000 (02:57 +0200)]
clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
clocks needed by these two GBETH IPs.
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250702005706.1200059-2-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Yixun Lan [Mon, 7 Jul 2025 14:07:15 +0000 (22:07 +0800)]
Merge tag 'spacemit-reset-for-6.17-1' of https://github.com/spacemit-com/linux
RISC-V SpacemiT Reset for 6.17
- Add reset driver support for K1 SoC
* tag 'spacemit-reset-for-6.17-1':
reset: spacemit: add support for SpacemiT CCU resets
clk: spacemit: define three reset-only CCUs
clk: spacemit: set up reset auxiliary devices
soc: spacemit: create a header for clock/reset registers
dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
Alex Elder [Wed, 2 Jul 2025 11:37:07 +0000 (06:37 -0500)]
reset: spacemit: add support for SpacemiT CCU resets
Implement reset support for SpacemiT CCUs. A SpacemiT reset controller
device is an auxiliary device associated with a clock controller (CCU).
This patch defines the reset controllers for the MPMU, APBC, and MPMU
CCUs, which already define clock controllers. It also adds RCPU, RCPU2,
and ACPB2 CCUs, which only define resets.
Signed-off-by: Alex Elder <elder@riscstar.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Yixun Lan <dlan@gentoo.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20250702113709.291748-6-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
Alex Elder [Thu, 12 Jun 2025 22:48:55 +0000 (17:48 -0500)]
clk: spacemit: mark K1 pll1_d8 as critical
The pll1_d8 clock is enabled by the boot loader, and is ultimately a
parent for numerous clocks, including those used by APB and AXI buses.
Guodong Xu discovered that this clock got disabled while responding to
getting -EPROBE_DEFER when requesting a reset controller.
The needed clock (CLK_DMA, along with its parents) had already been
enabled. To respond to the probe deferral return, the CLK_DMA clock
was disabled, and this led to parent clocks also reducing their enable
count. When the enable count for pll1_d8 was decremented it became 0,
which caused it to be disabled. This led to a system hang.
Marking that clock critical resolves this by preventing it from being
disabled.
Define a new macro CCU_FACTOR_GATE_DEFINE() to allow clock flags to
be supplied for a CCU_FACTOR_GATE clock.
Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC") Signed-off-by: Alex Elder <elder@riscstar.com> Tested-by: Guodong Xu <guodong@riscstar.com> Reviewed-by: Haylen Chu <heylenay@4d2.org> Link: https://lore.kernel.org/r/20250612224856.1105924-1-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
Alex Elder [Wed, 2 Jul 2025 11:37:05 +0000 (06:37 -0500)]
clk: spacemit: set up reset auxiliary devices
Add a new reset_name field to the spacemit_ccu_data structure. If it is
non-null, the CCU implements a reset controller, and the name will be
used in the name for the auxiliary device that implements it.
Define a new type to hold an auxiliary device as well as the regmap
pointer that will be needed by CCU reset controllers. Set up code to
initialize and add an auxiliary device for any CCU that implements reset
functionality.
Make it optional for a CCU to implement a clock controller. This
doesn't apply to any of the existing CCUs but will for some new ones
that will be added soon.
Alex Elder [Wed, 2 Jul 2025 11:37:04 +0000 (06:37 -0500)]
soc: spacemit: create a header for clock/reset registers
Move the definitions of register offsets and fields used by the SpacemiT
K1 SoC CCUs into a separate header file, so that they can be shared by
the reset driver that will be found under drivers/reset.
There are additional SpacemiT syscon CCUs whose registers control both
clocks and resets: RCPU, RCPU2, and APBC2. Unlike those defined
previously, these will (initially) support only resets. They do not
incorporate power domain functionality.
Previously the clock properties were required for all compatible nodes.
Make that requirement only apply to the three existing CCUs (APBC, APMU,
and MPMU), so that the new reset-only CCUs can go without specifying them.
Define the index values for resets associated with all SpacemiT K1
syscon nodes, including those with clocks already defined, as well as
the new ones (without clocks).
Lad Prabhakar [Fri, 27 Jun 2025 20:42:35 +0000 (21:42 +0100)]
clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting
Add support for fixed-factor module clocks that can report their enable
status through the module status monitor. Introduce a new clock type,
CLK_TYPE_FF_MOD_STATUS, and define the associated structure,
rzv2h_ff_mod_status_clk, to manage these clocks.
Implement the .is_enabled callback by reading the module status register
using monitor index and bit definitions. Provide a helper macro,
DEF_FIXED_MOD_STATUS, to simplify the definition of such clocks.
Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-clk-for-v6.17
Renesas RZ/V2N and RZ/V2H XSPI Clock DT Binding Definitions
Expanded Serial Peripheral Interface (XSPI) clock DT binding definitions
for the Renesas RZ/V2N (R9A09G056) and RZ/V2H (R9A09G057) SoCs, shared
by driver and DT source files.
Lad Prabhakar [Wed, 25 Jun 2025 14:17:04 +0000 (15:17 +0100)]
clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
Add support for PLL2 to the R9A09G077 (RZ/T2H) clock definitions and
register it as the source for the high-speed SDHI clock (SDHI_CLKHS)
operating at 800MHz.
Also add fixed-factor clock PCLKAM derived from CLK_PLL4D1, and define
module clocks for SDHI0 and SDHI1, both of which use PCLKAM as their
clock source.
Lad Prabhakar [Tue, 24 Jun 2025 15:30:49 +0000 (16:30 +0100)]
clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
The base address can be accessed via the priv pointer already present in
struct pll_clk, making the separate base field redundant. Remove the base
member and its assignment.
Lad Prabhakar [Wed, 25 Jun 2025 14:17:03 +0000 (15:17 +0100)]
dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
a core clock for the SDHI IP and operates at 800MHz.
Add XSPI core clock definitions to the clock bindings for the Renesas
R9A09G056 and R9A09G057 SoCs. These clocks IDs are used to support XSPI
interface.
Jerome Brunet [Mon, 23 Jun 2025 16:37:39 +0000 (18:37 +0200)]
clk: amlogic: s4: remove unused data
Following the removal of the clk_regmap clock table from the s4-peripherals
clock controller driver, it appears some clocks are unused, which means
these are not exported or even registered.
In all likelihood, these clocks have not been tested. Remove the unused
clocks for now. These can added back later when they have been properly
tested.
Jerome Brunet [Mon, 23 Jun 2025 16:37:38 +0000 (18:37 +0200)]
clk: amlogic: drop clk_regmap tables
Remove the clk_regmap tables that are used to keep track which clock
need to be initialised before being registered. The initialisation is now
done by the .init() operation of clk_regmap.
This rework saves a bit memory and makes maintenance a bit easier.
Jerome Brunet [Mon, 23 Jun 2025 16:37:37 +0000 (18:37 +0200)]
clk: amlogic: get regmap with clk_regmap_init
Add clk_regmap_init() and use it with all clock types which derive from
clk_regmap. This helps initialise clk_regmap clocks without requiring
tables to keep track of the clock using this type.
The way it is done couples clk_regmap with the controllers, which is not
ideal. This is a temporary solution to get rid of the tables. The situation
will eventually be improved.
Nuno Sá [Mon, 19 May 2025 15:41:11 +0000 (16:41 +0100)]
clk: clk-axi-clkgen move to min/max()
Instead of using the type versions of min/max(), use the plain ones as
now they are perfectly capable of handling different types like
unsigned and non negative integers that are compiletime constant.
Nuno Sá [Mon, 19 May 2025 15:41:10 +0000 (16:41 +0100)]
clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime
This patch adds support for setting the limits in struct
axi_clkgen_limits in accordance with fpga speed grade, voltage,
technology and family. This new information is extracted from
two new registers implemented in the ip core that are only available
for core versions higher or equal to 4.
Nuno Sá [Mon, 19 May 2025 15:41:08 +0000 (16:41 +0100)]
include: linux: move adi-axi-common.h out of fpga
The adi-axi-common.h header has some common defines used in various ADI
IPs. However they are not specific for any fpga manager so it's
questionable for the header to live under include/linux/fpga. Hence
let's just move one directory up and update all users.
Suggested-by: Xu Yilun <yilun.xu@linux.intel.com> Acked-by: Xu Yilun <yilun.xu@intel.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # for IIO Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20250519-dev-axi-clkgen-limits-v6-3-bc4b3b61d1d4@analog.com Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Uwe Kleine-König <ukleinek@kernel.org> Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Nuno Sá [Mon, 19 May 2025 15:41:06 +0000 (16:41 +0100)]
clk: clk-axi-clkgen: fix fpfd_max frequency for zynq
The fpfd_max frequency should be set to 450 MHz instead of 300 MHz.
Well, it actually depends on the platform speed grade but we are being
conservative for ultrascale so let's be consistent. In a following
change we will set these limits at runtime.
Jerome Brunet [Mon, 23 Jun 2025 14:37:00 +0000 (16:37 +0200)]
clk: amlogic: remove unnecessary headers
Some Amlogic clock controller drivers have a dedicated headers file, some
do not. Over time, these headers have evolved and now only carry register
offset definitions. These offsets are only used by the related controller
and are not meant to be shared.
These headers are not serving any purpose now.
Start enforcing some consistency between the different Amlogic clock
drivers and move the register offset definitions to the related driver.
There is a PPU0 reset control bit in the same register as the PPU1
reset control. This missing reset control is for the PCK-600 unit
in the SoC. Manual tests show that the reset control indeed exists,
and if not configured, the system will hang when the PCK-600 registers
are accessed.
Add a reset entry for it at the end of the existing ones.
Fixes: 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU") Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://patch.msgid.link/20250619171025.3359384-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>
There is a PPU0 reset control bit in the same register as the PPU1
reset control. This missing reset control is for the PCK-600 unit
in the SoC. Manual tests show that the reset control indeed exists,
and if not configured, the system will hang when the PCK-600 registers
are accessed.
Add a reset entry for it at the end of the existing ones.
Fixes: 52dbf84857f0 ("dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs") Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://patch.msgid.link/20250619171025.3359384-2-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Rohit Visavalia [Mon, 10 Feb 2025 11:36:14 +0000 (03:36 -0800)]
clk: xilinx: vcu: Update vcu init/reset sequence
Updated vcu init/reset sequence as per design changes.
If VCU reset GPIO is available then do assert and de-assert it before
enabling/disabling gasket isolation.
This GPIO is added because gasket isolation will be removed during startup
that requires access to SLCR register space. Post startup, the ownership of
the register interface lies with logiCORE IP.
Remove using for_each_of_allnodes_from() which is not safe to use
without holding the DT spinlock. In reality that probably doesn't
matter here. This is the only user in the whole tree, so it can be
made private once removed here. The "from" argument is always NULL, so
it can be dropped as well.
There's a slight change in behavior in matching the "clock-output-names"
value as the prior code would match if the node name matched the
beginning of the value and the comparision was case insensitive. Now
it must be an exact match.
clk: stm32: Do not enable by default during compile testing
Enabling the compile test should not cause automatic enabling of all
drivers. Restrict the default to ARCH also for individual driver, even
though its choice is not visible without selecting parent Kconfig
symbol, because otherwise selecting parent would select the child during
compile testing.
clk: nuvoton: Do not enable by default during compile testing
Enabling the compile test should not cause automatic enabling of all
drivers. Restrict the default to ARCH also for individual driver, even
though its choice is not visible without selecting parent Kconfig
symbol, because otherwise selecting parent would select the child during
compile testing.
clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests
Add kunit test suites clk_hw_get_dev() and clk_hw_get_of_node()
for clocks registered with clk_hw_register() and of_clk_hw_register()
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20250417-clk-hw-get-helpers-v1-2-7743e509612a@baylibre.com Reviewed-by: Brian Masney <bmasney@redhat.com>
[sboyd@kernel.org: Drop genparams, rename tests, drop inits,
combine suites, add test for non-DT platform device] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jerome Brunet [Fri, 20 Jun 2025 06:46:03 +0000 (23:46 -0700)]
clk: tests: Make clk_register_clk_parent_data_device_driver() common
Rename clk_register_clk_parent_data_device_driver() to
kunit_of_platform_driver_dev() and have it return a struct device
pointer while accepting a match table. This will be useful to
find the device associated with an OF node for more tests than
only the clk_parent_data tests.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
[sboyd@kernel.org: Split out from next patch, carry SoB and
authorship, rename API, return device pointer] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
For some PWMs applying a configuration doesn't sleep. For these enabling
and disabling can be done in the clk callbacks .enable() and .disable()
instead of .prepare() and .unprepare().
Do that to possibly reduce the time the PWM is enabled and so save some
energy.
clk: pwm: Don't reconfigure running PWM at probe time
If the PWM is enabled already when .probe() is entered, period and
duty_cycle are updated which essentially corresponds to a clock frequency
change. This is unusual and surprising. So update the settings only when
the clock gets prepared.
pwm_config() is an old function that I'd like to remove. So convert this
driver to use pwm_apply_might_sleep().
There is a minor change in behaviour as the explicitly calculated
duty_cycle used an uprounding division while pwm_set_relative_duty_cycle()
rounds down. I don't expect that difference to matter in practice though.
clk: pwm: Let .get_duty_cycle() return the real duty cycle
pwm_get_state() returns the last requested pwm_state which might differ
from what the lowlevel PWM driver actually implemented. For the purpose
of .get_duty_cycle() the latter is the more interesting info, so use
that to determine the output parameter.
Henry Martin [Tue, 1 Apr 2025 13:13:41 +0000 (21:13 +0800)]
clk: davinci: Add NULL check in davinci_lpsc_clk_register()
devm_kasprintf() returns NULL when memory allocation fails. Currently,
davinci_lpsc_clk_register() does not check for this case, which results
in a NULL pointer dereference.
Add NULL check after devm_kasprintf() to prevent this issue and ensuring
no resources are left allocated.
Fixes: c6ed4d734bc7 ("clk: davinci: New driver for davinci PSC clocks") Signed-off-by: Henry Martin <bsdhenrymartin@gmail.com> Link: https://lore.kernel.org/r/20250401131341.26800-1-bsdhenrymartin@gmail.com Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Sven Peter [Thu, 12 Jun 2025 21:11:27 +0000 (21:11 +0000)]
clk: apple-nco: Drop default ARCH_APPLE in Kconfig
When the first driver for Apple Silicon was upstreamed we accidentally
included `default ARCH_APPLE` in its Kconfig which then spread to almost
every subsequent driver. As soon as ARCH_APPLE is set to y this will
pull in many drivers as built-ins which is not what we want.
Thus, drop `default ARCH_APPLE` from Kconfig.
Onur Özkan [Wed, 18 Jun 2025 09:14:42 +0000 (12:14 +0300)]
rust: make `clk::Hertz` methods const
Marks `Hertz` methods as `const` to make them available
for `const` contexts. This can be useful when defining
static/compile-time frequency parameters in drivers/subsystems.
Lad Prabhakar [Tue, 17 Jun 2025 15:57:57 +0000 (16:57 +0100)]
clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
Add clock driver support for the Renesas RZ/N2H (R9A09G087) SoC by reusing
the existing RZ/T2H (R9A09G077) CPG/MSSR implementation, as both SoCs
share the same clock and reset architecture.
projects / thirdparty / linux.git / log
