Jason Merrill [Thu, 15 Mar 2018 03:49:07 +0000 (23:49 -0400)]
PR c++/84801 - ICE with unexpanded pack in lambda.
We avoid complaining about unexpanded packs when inside a lambda,
since the lambda as a whole could be part of a pack expansion.
But that can only be true if the lambda is in a template context.
* pt.c (check_for_bare_parameter_packs): Don't return early for a
lambda in non-template context.
Jonathan Wakely [Wed, 14 Mar 2018 23:02:01 +0000 (23:02 +0000)]
PR libstdc++/78420 Make std::less etc. yield total order for pointers
In order for std::less<T*> etc. to meet the total order requirements of
[comparisons] p2 we need to cast unrelated pointers to uintptr_t before
comparing them. Those casts aren't allowed in constant expressions, so
only cast when __builtin_constant_p says the result of the comparison is
not a compile-time constant (because the arguments are not constants, or
the result of the comparison is unspecified). When the result is
constant just compare the pointers directly without casting.
This ensures that the function can be called in constant expressions
with suitable arguments, but still yields a total order even for
otherwise unspecified pointer comparisons.
For std::less<void> etc. add new overloads for pointers, which use
std::less<common_type_t<T*,U*>> directly. Also change the generic
overloads to detect when the comparison would call a built-in relational
operator with pointer operands, and dispatch that case to the
corresponding specialization for void pointers.
PR libstdc++/78420
* include/bits/stl_function.h (greater<_Tp*>, less<_Tp*>)
(greater_equal<_Tp*>, less_equal<_Tp>*): Add partial specializations
to ensure total order for pointers.
(greater<void>, less<void>, greater_equal<void>, less_equal<void>):
Add operator() overloads for pointer arguments and make generic
overloads dispatch to new _S_cmp functions when comparisons would
use built-in operators for pointers.
* testsuite/20_util/function_objects/comparisons_pointer.cc: New.
Carl Love [Wed, 14 Mar 2018 23:01:12 +0000 (23:01 +0000)]
re PR target/84422 (ICE on various builtin test functions when compiled with -mcpu=power7)
gcc/ChangeLog:
2018-03-14 Carl Love <cel@us.ibm.com>
PR target/84422
* config/rs6000/rs6000-builtin.def: Change expansion for
VMULESW to BU_P8V_AV_2.
Change expansion for VMULEUW to BU_P8V_AV_2.
* config/rs6000/rs6000.c: Change
ALTIVEC_BUILTIN_VMULESW to P8V_BUILTIN_VMULESW.
Change ALTIVEC_BUILTIN_VMULEUW to P8V_BUILTIN_VMULEUW.
Change ALTIVEC_BUILTIN_VMULOSW to P8V_BUILTIN_VMULOSW.
Change ALTIVEC_BUILTIN_VMULOUW to P8V_BUILTIN_VMULOUW.
* config/rs6000/rs6000-c.c: Change
ALTIVEC_BUILTIN_VMULESW to P8V_BUILTIN_VMULESW.
Change ALTIVEC_BUILTIN_VMULEUW to P8V_BUILTIN_VMULEUW.
Change ALTIVEC_BUILTIN_VMULOSW to P8V_BUILTIN_VMULOSW.
Change ALTIVEC_BUILTIN_VMULOUW to P8V_BUILTIN_VMULOUW.
The underlying problem is the mix of types for storing line numbers:
in parts of libcpp and diagnostic-show-locus.c we use linenum_type;
in other places (including libcpp's expanded_location) we use int.
I looked at using linenum_type throughout, but doing so turned into
a large patch, so this patch fixes the ICE in a less invasive way
by merely using linenum_type more consistently just within
diagnostic-show-locus.c, and fixing line_span::comparator to properly
handle line numbers (and line number differences) >= 2^31, by using
a new helper function for linenum_type differences, computing the
difference using long long, and using the sign of the difference
(as the difference might not fit in the "int" return type imposed
by qsort).
gcc/ChangeLog:
PR c/84852
* diagnostic-show-locus.c (class layout_point): Convert m_line
from int to linenum_type.
(line_span::comparator): Use linenum "compare" function when
comparing line numbers.
(test_line_span): New function.
(layout_range::contains_point): Convert param "row" from int to
linenum_type.
(layout_range::intersects_line_p): Likewise.
(layout::will_show_line_p): Likewise.
(layout::print_source_line): Likewise.
(layout::should_print_annotation_line_p): Likewise.
(layout::print_annotation_line): Likewise.
(layout::print_leading_fixits): Likewise.
(layout::annotation_line_showed_range_p): Likewise.
(struct line_corrections): Likewise for field m_row.
(line_corrections::line_corrections): Likewise for param "row".
(layout::print_trailing_fixits): Likewise.
(layout::get_state_at_point): Likewise.
(layout::get_x_bound_for_row): Likewise.
(layout::print_line): Likewise.
(diagnostic_show_locus): Likewise for locals "last_line" and
"row".
(selftest::diagnostic_show_locus_c_tests): Call test_line_span.
* input.c (selftest::test_linenum_comparisons): New function.
(selftest::input_c_tests): Call it.
* selftest.c (selftest::test_assertions): Test ASSERT_GT,
ASSERT_GT_AT, ASSERT_LT, and ASSERT_LT_AT.
* selftest.h (ASSERT_GT): New macro.
(ASSERT_GT_AT): New macro.
(ASSERT_LT): New macro.
(ASSERT_LT_AT): New macro.
gcc/testsuite/ChangeLog:
PR c/84852
* gcc.dg/fixits-pr84852-1.c: New test.
* gcc.dg/fixits-pr84852-2.c: New test.
libcpp/ChangeLog:
* include/line-map.h (compare): New function on linenum_type.
combine: Don't make log_links for pc_rtx (PR84780 #c10)
distribute_links tries to place a log_link for whatever the destination
of the modified instruction is. It shouldn't do that when that dest
is pc_rtx, which isn't actually a register.
* combine.c (distribute_links): Don't make a link based on pc_rtx.
Martin Liska [Wed, 14 Mar 2018 11:17:01 +0000 (12:17 +0100)]
Fix tree statistics with -fmem-report.
2018-03-14 Martin Liska <mliska@suse.cz>
* tree.c (record_node_allocation_statistics): Use
get_stats_node_kind.
(get_stats_node_kind): New function extracted from
record_node_allocation_statistics.
(free_node): Use get_stats_node_kind.
scan-assembler-times and scan-tree-dump-times dejagnu directives show a
different output in the summary files depending on whether they PASS or
FAIL. This means that dg-cmp-results would not show a regression because
it would not see a connection between the two output.
The difference comes from the FAIL showing the number of actual times
the pattern was match, presumably to help debugging. This patch moves
the info regarding the actual number of times the pattern match in a
separate verbose message. This keeps the message unchanged but let
developers have the required debug message with -v.
2018-03-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/testsuite/
* lib/scanasm.exp (scan-assembler-times): Move FAIL debug info into a
separate verbose message.
* lib/scandump.exp (scan-dump-times): Likewise.
Jakub Jelinek [Wed, 14 Mar 2018 08:50:23 +0000 (09:50 +0100)]
re PR sanitizer/83392 (FAIL: c-c++-common/ubsan/ptr-overflow-sanitization-1.c scan-tree-dump-times)
PR sanitizer/83392
* sanopt.c (maybe_optimize_ubsan_ptr_ifn): Handle also
INTEGER_CST offset, add it together with bitpos / 8 and
sign extend based on POINTER_SIZE.
* c-c++-common/ubsan/ptr-overflow-sanitization-1.c: Adjust expected
check count from 17 to 14.
PR target/78090
* config/i386/constraints.md (Yc): New register constraint.
* config/i386/i386.md (*float<SWI48:mode><MODEF:mode>2_mixed):
Use Yc constraint for alternative 2 of operand 0. Remove
preferred_for_speed attribute.
Vladimir Makarov [Tue, 13 Mar 2018 20:42:49 +0000 (20:42 +0000)]
re PR target/83712 ("Unable to find a register to spill" when compiling for thumb1)
2018-03-13 Vladimir Makarov <vmakarov@redhat.com>
PR target/83712
* lra-assigns.c (find_all_spills_for): Ignore uninteresting
pseudos.
(assign_by_spills): Return a flag of reload assignment failure.
Do not process the reload assignment failures. Do not spill other
reload pseudos if they has the same reg class. Update n if
necessary.
(lra_assign): Add a return arg. Set up from the result of
assign_by_spills call.
(find_reload_regno_insns, lra_split_hard_reg_for): New functions.
* lra-constraints.c (split_reg): Add a new arg. Use it instead of
usage_insns if it is not NULL.
(spill_hard_reg_in_range): New function.
(split_if_necessary, inherit_in_ebb): Pass a new arg to split_reg.
* lra-int.h (spill_hard_reg_in_range, lra_split_hard_reg_for): New
function prototypes.
(lra_assign): Change prototype.
* lra.c (lra): Add code to deal with fails by splitting hard reg
live ranges.
Jakub Jelinek [Tue, 13 Mar 2018 20:32:54 +0000 (21:32 +0100)]
re PR c++/84843 (C++ ICE on builtin redefinition since r258391)
PR c++/84843
* decl.c (duplicate_decls): For redefinition of built-in, use error
and return error_mark_node. For redeclaration, return error_mark_node
rather than olddecl if !flag_permissive.
* g++.dg/ext/pr84843-1.C: New test.
* g++.dg/ext/pr84843-2.C: New test.
Palmer Dabbelt [Tue, 13 Mar 2018 18:35:06 +0000 (18:35 +0000)]
RISC-V: Add and document the "-mno-relax" option
RISC-V relies on aggressive linker relaxation to get good code size. As
a result no text symbol addresses can be known until link time, which
means that alignment must be handled during the link. This alignment
pass is essentially just another linker relaxation, so this has the
unfortunate side effect that linker relaxation is required for
correctness on many RISC-V targets.
The RISC-V assembler has supported an ".option norelax" for a long time
because there are situations in which linker relaxation is a bad idea --
the canonical example is when trying to materialize the initial value of
the global pointer into a register, which would otherwise be relaxed to
a NOP. We've been relying on users who want to disable relaxation for
an entire link to pass "-Wl,--no-relax", but that still relies on the
linker relaxing R_RISCV_ALIGN to handle alignment despite it not being
strictly necessary.
This patch adds a GCC option, "-mno-relax", that disable linker
relaxation by adding ".option norelax" to the top of every generated
assembly file. The assembler is smart enough to handle alignment at
assemble time for files that have never emitted a relaxable relocation,
so this is sufficient to really disable all relaxations in the linker,
which results in significantly faster link times for large objects.
This also has the side effect of allowing toolchains that don't support
linker relaxation (LLVM and the Linux module loader) to function
correctly. Toolchains that don't support linker relaxation should
default to "-mno-relax" and error when presented with any R_RISCV_ALIGN
relocation as those need to be handled for correctness.
gcc/ChangeLog
2018-03-13 Palmer Dabbelt <palmer@sifive.com>
* config/riscv/riscv.opt (mrelax): New option.
* config/riscv/riscv.c (riscv_file_start): Emit ".option
"norelax" when riscv_mrelax is disabled.
* doc/invoke.texi (RISC-V): Document "-mrelax" and "-mno-relax".
Currently, function output_init_element () does not evaluate the left
hand expression in a comma operator that's used for a struct
initializer field if the right hand side is zero-sized. However, the
left hand expression must be evaluated if it's found to have side
effects (for example, a function call).
Patch was successfully bootstrapped and tested on x86_64-linux.
gcc/c:
2018-03-13 David Pagan <dave.pagan@oracle.com>
PR c/46921
* c-typeck.c (output_init_element): Ensure field initializer
expression is always evaluated if there are side effects.
gcc/testsuite:
2018-03-13 David Pagan <dave.pagan@oracle.com>
Martin Sebor [Tue, 13 Mar 2018 15:33:16 +0000 (15:33 +0000)]
PR tree-optimization/84725 - enable attribute nonstring for all narrow character types
gcc/c-family/ChangeLog:
PR tree-optimization/84725
* c-attribs.c (handle_nonstring_attribute): Allow attribute nonstring
with all three narrow character types, including their qualified forms.
gcc/testsuite/ChangeLog:
PR tree-optimization/84725
* c-c++-common/Wstringop-truncation-4.c: New test.
* c-c++-common/attr-nonstring-5.c: New test.
[SLP/AArch64] Fix unpack handling for big-endian SVE
I hadn't realised that on big-endian targets, VEC_UNPACK*HI_EXPR unpacks
the low-numbered lanes and VEC_UNPACK*LO_EXPR unpacks the high-numbered
lanes. This meant that both the SVE patterns and the handling of
fully-masked loops were wrong.
The patch deals with that by making sure that all vec_unpack* optabs
are define_expands, using BYTES_BIG_ENDIAN to choose the appropriate
define_insn. This in turn meant that we can get rid of the duplication
between the signed and unsigned patterns for predicates. (We provide
implementations of both the signed and unsigned optabs because the sign
doesn't matter for predicates: every element contains only one
significant bit.)
Also, the float unpacks need to unpack one half of the input vector,
but the unpacked upper bits are "don't care". There are two obvious
ways of handling that: use an unpack (filling with zeros) or use a ZIP
(filling with a duplicate of the low bits). The code previously used
unpacks, but the sequence involved a subreg that is semantically an
element reverse on big-endian targets. Using the ZIP patterns avoids
that, and at the moment there's no reason to prefer one over the other
for performance reasons, so the patch switches to ZIP unconditionally.
As the comment says, it would be easy to optimise this later if UUNPK
turns out to be better for some implementations.
2018-03-13 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-vect-loop-manip.c (vect_maybe_permute_loop_masks):
Reverse the choice between VEC_UNPACK_LO_EXPR and VEC_UNPACK_HI_EXPR
for big-endian.
* config/aarch64/iterators.md (hi_lanes_optab): New int attribute.
* config/aarch64/aarch64-sve.md
(*aarch64_sve_<perm_insn><perm_hilo><mode>): Rename to...
(aarch64_sve_<perm_insn><perm_hilo><mode>): ...this.
(*extend<mode><Vwide>2): Rename to...
(aarch64_sve_extend<mode><Vwide>2): ...this.
(vec_unpack<su>_<perm_hilo>_<mode>): Turn into a define_expand,
renaming the old pattern to...
(aarch64_sve_punpk<perm_hilo>_<mode>): ...this. Only define
unsigned packs.
(vec_unpack<su>_<perm_hilo>_<SVE_BHSI:mode>): Turn into a
define_expand, renaming the old pattern to...
(aarch64_sve_<su>unpk<perm_hilo>_<SVE_BHSI:mode>): ...this.
(*vec_unpacku_<perm_hilo>_<mode>_no_convert): Delete.
(vec_unpacks_<perm_hilo>_<mode>): Take BYTES_BIG_ENDIAN into
account when deciding which SVE instruction the optab should use.
(vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Likewise.
gcc/testsuite/
* gcc.target/aarch64/sve/unpack_fcvt_signed_1.c: Expect zips rather
than unpacks.
* gcc.target/aarch64/sve/unpack_fcvt_unsigned_1.c: Likewise.
* gcc.target/aarch64/sve/unpack_float_1.c: Likewise.
tlsdesc calls are guaranteed to preserve all Advanced SIMD registers,
but are not guaranteed to preserve the SVE extension of them.
The calls also don't preserve the SVE predicate registers.
The long-term plan for handling the SVE vector registers is CLOBBER_HIGH,
which adds a clobber equivalent of TARGET_HARD_REGNO_CALL_PART_CLOBBERED.
The pattern can then directly model the fact that the low 128 bits are
preserved and the upper bits are clobbered.
However, it's too late now for that to be included in GCC 8, so this
patch conservatively treats the whole vector register as being clobbered.
This has the obvious disadvantage that compiling for SVE can make NEON
code worse, but I don't think there's much we can do about that until
CLOBBER_HIGH is in.
2018-03-13 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/aarch64/aarch64.md (V4_REGNUM, V8_REGNUM, V12_REGNUM)
(V20_REGNUM, V24_REGNUM, V28_REGNUM, P1_REGNUM, P2_REGNUM, P3_REGNUM)
(P4_REGNUM, P5_REGNUM, P6_REGNUM, P8_REGNUM, P9_REGNUM, P10_REGNUM)
(P11_REGNUM, P12_REGNUM, P13_REGNUM, P14_REGNUM): New define_constants.
(tlsdesc_small_<mode>): Turn a define_expand and use
tlsdesc_small_sve_<mode> for SVE. Rename original define_insn to...
(tlsdesc_small_advsimd_<mode>): ...this.
(tlsdesc_small_sve_<mode>): New pattern.
gcc/testsuite/
* gcc.target/aarch64/sve/tls_1.c: New test.
* gcc.target/aarch64/sve/tls_2.C: Likewise.
One advantage of the new permute handling compared to the old way is
that we can now easily take advantage of the vectoriser's divmod patterns
for SVE.
2018-03-13 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/aarch64/iterators.md (UNSPEC_SMUL_HIGHPART)
(UNSPEC_UMUL_HIGHPART): New constants.
(MUL_HIGHPART): New int iteraor.
(su): Handle UNSPEC_SMUL_HIGHPART and UNSPEC_UMUL_HIGHPART.
* config/aarch64/aarch64-sve.md (<su>mul<mode>3_highpart): New
define_expand.
(*<su>mul<mode>3_highpart): New define_insn.
gcc/testsuite/
* gcc.target/aarch64/sve/mul_highpart_1.c: New test.
* gcc.target/aarch64/sve/mul_highpart_1_run.c: Likewise.
Martin Liska [Tue, 13 Mar 2018 08:20:27 +0000 (09:20 +0100)]
Fix PTA info in IPA ICF (PR ipa/84658).
2018-03-13 Martin Liska <mliska@suse.cz>
PR ipa/84658.
* (sem_item_optimizer::sem_item_optimizer): Initialize new
vector.
(sem_item_optimizer::~sem_item_optimizer): Release it.
(sem_item_optimizer::merge_classes): Register variable aliases.
(sem_item_optimizer::fixup_pt_set): New function.
(sem_item_optimizer::fixup_points_to_sets): Likewise.
* ipa-icf.h: Declare new variables and functions.
2018-03-13 Martin Liska <mliska@suse.cz>
Jakub Jelinek [Tue, 13 Mar 2018 08:12:59 +0000 (09:12 +0100)]
re PR middle-end/84834 (ICE: tree check: expected integer_cst, have complex_cst in to_wide, at tree.h:5527)
PR middle-end/84834
* match.pd ((A & C) != 0 ? D : 0): Use INTEGER_CST@2 instead of
integer_pow2p@2 and test integer_pow2p in condition.
(A < 0 ? C : 0): Similarly for @1.
Jakub Jelinek [Tue, 13 Mar 2018 08:04:54 +0000 (09:04 +0100)]
re PR target/84828 (ICE in verify_flow_info at gcc/cfghooks.c:265)
PR target/84828
* reg-stack.c (change_stack): Change update_end var from int to
rtx_insn *, if non-NULL don't update just BB_END (current_block), but
also call set_block_for_insn on the newly added insns and rescan.
Jakub Jelinek [Mon, 12 Mar 2018 23:40:20 +0000 (00:40 +0100)]
re PR c++/84808 (ICE with constexpr and array)
PR c++/84808
* constexpr.c (find_array_ctor_elt): Don't use elt reference after
first potential CONSTRUCTOR_ELTS reallocation. Convert dindex to
sizetype. Formatting fixes.
rs6000: sysv: Don't pass SFmode in varargs in FPRs
This makes the float32-basic.c testcase work on sysv (32-bit Linux).
"float" is promoted to "double" for varargs. The ABI also only defines
the use of double precision in varargs. But _Float32 is not promoted.
Since there is no way of passing single-precision float in FPRs we
should pass SFmode in GPRs (or memory) instead. This is similar to
the 64-bit ABI.
There still are situations where we have stale LOG_LINKS. This causes
combine to try two-insn combinations I2->I3 where the register set by
I2 is used before I3 as well. Not good.
This patch fixes it by checking for this situation in can_combine_p
(similar to what we already do for three and four insn combinations).
Paul Thomas [Sun, 11 Mar 2018 22:25:11 +0000 (22:25 +0000)]
re PR fortran/84546 (Bad sourced allocation of CLASS(*) with source with CLASS(*) component)
2018-03-11 Paul Thomas <pault@gcc.gnu.org>
PR fortran/84546
* trans-array.c (structure_alloc_comps): Make sure that the
vptr is copied and that the unlimited polymorphic _len is used
to compute the size to be allocated.
* trans-expr.c (gfc_get_class_array_ref): If unlimited, use the
unlimited polymorphic _len for the offset to the element.
(gfc_copy_class_to_class): Set the new 'unlimited' argument.
* trans.h : Add the boolean 'unlimited' to the prototype.
2018-03-11 Paul Thomas <pault@gcc.gnu.org>
PR fortran/84546
* gfortran.dg/unlimited_polymorphic_29.f90 : New test.
Steven G. Kargl [Sun, 11 Mar 2018 21:34:40 +0000 (21:34 +0000)]
check.c (gfc_check_kill): Check pid and sig are scalar.
2018-03-11 Steven G. Kargl <kargls@gcc.gnu.org>
* check.c (gfc_check_kill): Check pid and sig are scalar.
(gfc_check_kill_sub): Restrict kind to 4 and 8.
* intrinsic.c (add_function): Sort keyword list. Add pid and sig
keywords for KILL. Remove redundant *back="back" in favor of the
original *bck="back".
(add_subroutines): Sort keyword list. Add pid and sig keywords
for KILL.
* intrinsic.texi: Fix documentation to consistently use pid and sig.
* iresolve.c (gfc_resolve_kill): Kind can only be 4 or 8. Choose the
correct function.
(gfc_resolve_rename_sub): Add comment.
Jakub Jelinek [Sun, 11 Mar 2018 16:50:08 +0000 (17:50 +0100)]
re PR debug/58150 (debug info about definition of enum class not emitted if the declaration was already used in a class)
PR debug/58150
* dwarf2out.c (gen_enumeration_type_die): Don't guard adding
DW_AT_declaration for ENUM_IS_OPAQUE on -gdwarf-4 or -gno-strict-dwarf,
but on TYPE_SIZE. Don't do anything for ENUM_IS_OPAQUE if not creating
a new die. Don't set TREE_ASM_WRITTEN if ENUM_IS_OPAQUE. Guard
addition of most attributes on !orig_type_die or the attribute not
being present already. Assert TYPE_VALUES is NULL for ENUM_IS_OPAQUE.
Vladimir Makarov [Sat, 10 Mar 2018 16:32:21 +0000 (16:32 +0000)]
revert: re PR target/83712 ("Unable to find a register to spill" when compiling for thumb1)
2018-03-10 Vladimir Makarov <vmakarov@redhat.com>
Reverting patch:
2018-03-09 Vladimir Makarov <vmakarov@redhat.com>
PR target/83712
* lra-assigns.c (assign_by_spills): Return a flag of reload
assignment failure. Do not process the reload assignment
failures. Do not spill other reload pseudos if they has the same
reg class.
(lra_assign): Add a return arg. Set up from the result of
assign_by_spills call.
(find_reload_regno_insns, lra_split_hard_reg_for): New functions.
* lra-constraints.c (split_reg): Add a new arg. Use it instead of
usage_insns if it is not NULL.
(spill_hard_reg_in_range): New function.
(split_if_necessary, inherit_in_ebb): Pass a new arg to split_reg.
* lra-int.h (spill_hard_reg_in_range, lra_split_hard_reg_for): New
function prototypes.
(lra_assign): Change prototype.
* lra.c (lra): Add code to deal with fails by splitting hard reg
live ranges.
Alexandre Oliva [Sat, 10 Mar 2018 06:42:40 +0000 (06:42 +0000)]
[IEPM] [PR debug/84620] use constant form for DW_AT_GNU_entry_view
When outputting entry views in symbolic mode, we used to use a lbl_id,
but that outputs the view as an addr, perhaps even in an indirect one,
which is all excessive and undesirable for a small assembler-computed
constant.
Introduce a new value class for symbolic views, so that we can output
the labels as constant data, using as narrow forms as possible, but
wide enough for any symbolic views output in the compilation. We
don't know exactly where the assembler will reset views, but we count
the symbolic views since known reset points and use that as an upper
bound for view numbers.
Ideally, we'd use uleb128, but then the compiler would have to defer
.debug_info offset computation to the assembler. I'm not going there
for now, so a symbolic uleb128 assembler constant in an attribute is
not something GCC can deal with ATM.
Peter Bergner [Fri, 9 Mar 2018 22:43:59 +0000 (16:43 -0600)]
re PR target/83969 (ICE in final_scan_insn, at final.c:2997 (error: could not split insn) for powerpc targets)
gcc/
PR target/83969
* config/rs6000/rs6000.c (rs6000_offsettable_memref_p): New prototype.
Add strict argument and use it.
(rs6000_split_multireg_move): Update for new strict argument.
(mem_operand_gpr): Disallow all non-offsettable addresses.
* config/rs6000/rs6000.md (*movdi_internal64): Use YZ constraint.
gcc/testsuite/
PR target/83969
* gcc.target/powerpc/pr83969.c: New test.
Jason Merrill [Fri, 9 Mar 2018 20:39:14 +0000 (21:39 +0100)]
re PR c++/84076 (Warning about objects through POD mistakenly claims the object is a pointer)
PR c++/84076
* call.c (convert_arg_to_ellipsis): Instead of cp_build_addr_expr
build ADDR_EXPR with REFERENCE_TYPE.
(build_over_call): For purposes of check_function_arguments, if
argarray[j] is ADDR_EXPR with REFERENCE_TYPE created above, use
its operand rather than the argument itself.
Martin Sebor [Fri, 9 Mar 2018 19:06:26 +0000 (19:06 +0000)]
re PR tree-optimization/84526 (ICE in generic_overlap at gcc/gimple-ssa-warn-restrict.c:927 since r257860)
gcc/ChangeLog:
PR tree-optimization/84526
* gimple-ssa-warn-restrict.c (builtin_memref::set_base_and_offset):
Remove dead code.
(builtin_access::generic_overlap): Be prepared to handle non-array
base objects.
gcc/testsuite/ChangeLog:
PR tree-optimization/84526
* gcc.dg/Wrestrict-10.c: New test.
* gcc.dg/Wrestrict-11.c: New test.
The internal/trace package is only imported by tests (specifically the
tests in runtime/trace) so it must be in noinst_DATA to ensure that it
is built before running the tests.
This was mostly working because internal/trace has tests itself, and
is listed in check-packages.txt before runtime/trace, so typical
invocations of make would build internal/trace for checking purposes
before checking runtime/trace. But we need this change to make that
reliable.
Jakub Jelinek [Fri, 9 Mar 2018 18:01:22 +0000 (19:01 +0100)]
re PR c++/84724 (internal compiler error: in single_succ_edge, at basic-block.h:339 with a declaration of __builtin_trap)
PR c++/84724
* decl.c (duplicate_decls): Don't override __* prefixed builtins
except for __[^b]*_chk, instead issue permerror and for -fpermissive
also a note and return olddecl.
re PR target/83712 ("Unable to find a register to spill" when compiling for thumb1)
2018-03-09 Vladimir Makarov <vmakarov@redhat.com>
PR target/83712
* lra-assigns.c (assign_by_spills): Return a flag of reload
assignment failure. Do not process the reload assignment
failures. Do not spill other reload pseudos if they has the same
reg class.
(lra_assign): Add a return arg. Set up from the result of
assign_by_spills call.
(find_reload_regno_insns, lra_split_hard_reg_for): New functions.
* lra-constraints.c (split_reg): Add a new arg. Use it instead of
usage_insns if it is not NULL.
(spill_hard_reg_in_range): New function.
(split_if_necessary, inherit_in_ebb): Pass a new arg to split_reg.
* lra-int.h (spill_hard_reg_in_range, lra_split_hard_reg_for): New
function prototypes.
(lra_assign): Change prototype.
* lra.c (lra): Add code to deal with fails by splitting hard reg
live ranges.
Kyrylo Tkachov [Fri, 9 Mar 2018 15:42:10 +0000 (15:42 +0000)]
[arm] PR target/83193: Do not print arch/cpu hints twice on invalid -march/-mcpu
Currently when handling an invalid -march or -mcpu option on a toolchain without an explicit --with-mode configuration
and compiling without an explicit -mthumb or -marm the arm specs end up calling arm_target_thumb_only to determine
the "thumbness" of the target, which involves parsing the architecture or cpu name. But the functions doing that
parsing also emit error messages and hints on invalid arguments. Later when we parse the architecture or cpu string to
as part of the canonicalisation process (arm_canon_arch_option) we end up emitting the errors again.
The solution in this patch is to silence the errors during the arm_target_thumb_only processing so that they are not emitted
twice. arm_canon_arch_option is guaranteed to run as well, so it can emit the errors and hints that it needs.
Bootstrapped and tested on arm-none-linux-gnueabihf.
Checked that we emit the arch/cpu hints for invalid -march/-mcpu options only once when no "thumbness" options were specified
during configuration or invocation.
PR target/83193
* common/config/arm/arm-common.c (arm_parse_arch_option_name):
Accept complain bool parameter. Only emit errors if it is true.
(arm_parse_cpu_option_name): Likewise.
(arm_target_thumb_only): Adjust callers of the above.
* config/arm/arm-protos.h (arm_parse_cpu_option_name): Adjust
prototype to take a default true bool parameter.
(arm_parse_arch_option_name): Likewise.
projects / thirdparty / gcc.git / log
