Douglas Anderson [Thu, 23 Mar 2023 17:30:13 +0000 (10:30 -0700)]
arm64: dts: qcom: sc7180: Remove superfluous "input-enable"s from trogdor
As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should
use output-disable, not input-enable"), using "input-enable" in
pinctrl states for Qualcomm TLMM pinctrl devices was either
superfluous or there to disable a pin's output.
Looking at trogdor:
* ap_ec_int_l, fp_to_ap_irq_l, h1_ap_int_odl, p_sensor_int_l:
Superfluous. The pins will be configured as inputs automatically by
the Linux GPIO subsystem (presumably the reference for other OSes
using these device trees).
* bios_flash_wp_l: Superfluous. This pin is exposed to userspace
through the kernel's GPIO API and will be configured automatically.
That means that in none of the cases for trogdor did we need to change
"input-enable" to "output-disable" and we can just remove these
superfluous properties.
Douglas Anderson [Thu, 23 Mar 2023 17:30:08 +0000 (10:30 -0700)]
arm64: dts: qcom: sc7180: Annotate l13a on trogdor to always-on
The l13a rail on trogdor devices has always been intended to be
always-on on both S0 and S3. Different trogdor variants use l13a in
slightly different ways, but the overall theme is that it's a 1.8V
rail that the board uses for things that it wants powered in on S0 and
S3. On many boards this includes the boot SPI (AKA qspi).
For all intents and purposes this patch is actually a no-op since
something else in the system seems to already be keeping the rail on
all the time (confirmed via multimeter). That "something else" was
postulated to be the modem but the rail is on / stays on even without
the modem/wifi coming up so it's likely the boot config. In any case,
making the fact that this is always-on explicit seems like a good
idea.
Douglas Anderson [Thu, 23 Mar 2023 17:30:07 +0000 (10:30 -0700)]
arm64: dts: sdm845: Rename qspi data12 as data23
There are 4 qspi data pins: data0, data1, data2, and data3. Currently
we have a shared pin state for data0 and data1 (2 lane config) and a
pin state for data2 and data3 (you'd enable both this and the 2 lane
state for 4 lanes). The second state is obviously misnamed. Fix it.
Douglas Anderson [Thu, 23 Mar 2023 17:30:06 +0000 (10:30 -0700)]
arm64: dts: sc7280: Rename qspi data12 as data23
There are 4 qspi data pins: data0, data1, data2, and data3. Currently
we have a shared pin state for data0 and data1 (2 lane config) and a
pin state for data2 and data3 (you'd enable both this and the 2 lane
state for 4 lanes). The second state is obviously misnamed. Fix it.
Douglas Anderson [Thu, 23 Mar 2023 17:30:05 +0000 (10:30 -0700)]
arm64: dts: sc7180: Rename qspi data12 as data23
There are 4 qspi data pins: data0, data1, data2, and data3. Currently
we have a shared pin state for data0 and data1 (2 lane config) and a
pin state for data2 and data3 (you'd enable both this and the 2 lane
state for 4 lanes). The second state is obviously misnamed. Fix it.
Merge branch 'ib-qcom-quad-spi' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into arm64-for-6.4
Merge the support for output-enable/disable in the pinctrl-msm driver,
to ensure that bisection across the following SC7180/SC7280 DeviceTree
changes result in something electrically sound.
Angler's cont_splash_mem mapping is shorter in downstream [1],
therefore 380cd3a34b7f was wrong. Obviously also 0e5ded926f2a was wrong
(workaround which fixed booting at the time).
This fixes error:
[ 0.000000] memory@3401000 (0x0000000003401000--0x0000000005601000) overlaps with tzapp@4800000 (0x0000000004800000--0x0000000006100000)
Douglas Anderson [Thu, 30 Mar 2023 21:11:00 +0000 (14:11 -0700)]
MAINTAINERS: qcom: Add reviewer for Qualcomm Chromebooks
Developers on the ChromeOS team generally want to be notified to
review changes that affect Chromebook device tree files. While we
could individually add developers, the set of developers and the time
each one has available to review patches will change over time. Let's
try adding a group list as a reviewer and see if that's an effective
way to manage things.
A few notes:
* Though this email address is actually backed by a mailing list, I'm
adding it as "R"eviewer and not "L"ist since it's not a publicly
readable mailing list and it's intended just to have a few people on
it. This also hopefully conveys a little more responisbility for the
people that are part of this group.
* I've added all sc7180 and sc7280 files here. At the moment I'm not
aware of any non-Chromebooks being supported that use these
chips. If later something shows up then we can try to narrow down.
* I've added "sdm845-cheza" to this list but not the rest of
"sdm845". Cheza never shipped but some developers still find the old
developer boards useful and thus it continues to get minimal
maintenance. Most sdm845 device tree work, however, seems to be for
non-Chromebooks.
Cc: Stephen Boyd <swboyd@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230330141051.1.If8eb4f30cb53a00a5bef1b7d3cc645c3536615ec@changeid
Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on
Qualcomm SM8550. The nodes are very similar to SM8450, except missing
NPL clock which is not exposed on SM8550 and should not be touched.
arm64: dts: qcom: Remove "iommus" property from PCIe nodes
Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map"
properties for the PCIe nodes. First one passes the SMR mask to the iommu
driver and the latter specifies the SID for each PCIe device.
But with "iommus" property, the PCIe controller will be added to the
iommu group along with the devices. This makes no sense because the
controller will not initiate any DMA transaction on its own. And moreover,
it is not strictly required to pass the SMR mask to the iommu driver. If
the "iommus" property is not present, then the default mask of "0" would be
used which should work for all PCIe devices.
On the other side, if the SMR mask specified doesn't match the one expected
by the hypervisor, then all the PCIe transactions will end up triggering
"Unidentified Stream Fault" by the SMMU.
So to get rid of these hassles and also prohibit PCIe controllers from
adding to the iommu group, let's remove the "iommus" property from PCIe
nodes.
arm64: dts: qcom: sm8450: label the Soundwire nodes
Use labels, instead of comments, for Soundwire controllers. Naming them
is useful, because they are specialized and have also naming in
datasheet/programming guide.
arm64: dts: qcom: sc8280xp: label the Soundwire nodes
Use labels, instead of comments, for Soundwire controllers. Naming them
is useful, because they are specialized and have also naming in
datasheet/programming guide.
arm64: dts: qcom: sa8775p: sort soc nodes by reg property
Sort all children of the soc node by the first address in their reg
property. This was mostly already the case but there were some nodes
that didn't follow it so fix it now for consistency.
Add required pins and RMI4 node to the common DT and remove it
from Akatsuki, as it uses a different touch.
Since the panels are super high tech proprietary incell, they
need to be handled with very precise timings. As such the panel
driver sets up the power rails and GPIOs and the touchscreen
driver *has to* probe afterwards.
Neil Armstrong [Fri, 24 Mar 2023 09:28:47 +0000 (10:28 +0100)]
arm64: dts: qcom: sm8450: remove invalid properties in cluster-sleep nodes
Fixes the following DT bindings check error:
domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes:
'pinctrl-[0-9]+'
domain-idle-states: cluster-sleep-1: 'idle-state-name', 'local-timer-stop' do not match any of the regexes:
'pinctrl-[0-9]+'
arm64: dts: qcom: sm6375: drop incorrect domain idle states properties
Domain idle states do not use 'idle-state-name' and 'local-timer-stop':
sm6375-sony-xperia-murray-pdx225.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+'
Konrad Dybcio [Tue, 14 Mar 2023 13:28:35 +0000 (14:28 +0100)]
arm64: dts: qcom: msm8998-yoshino: Use actual pin names for pin nodes
With the gpio-line-names in place coming from SONY themselves, we can
now make the pin nodes and their labels to more closely resemble the
actual thing. 4k has been renamed to four_k due to dtc limitations.
Konrad Dybcio [Tue, 14 Mar 2023 13:28:34 +0000 (14:28 +0100)]
arm64: dts: qcom: msm8998-yoshino: Use SONY GPIO names
Sony ever so graciously provides GPIO line names in their downstream
kernel (though sometimes they are not 100% accurate and you can judge
that by simply looking at them and with what drivers they are used).
Add these to the Yoshino devices DTs to better document the hardware.
Lilac and Poplar have identical pin assignments.
Diff between these two and maple:
TLMM:
- "NC",
+ "TS_VDDIO_EN",
PMI8998:
- "NC"
+ "USB_SWITCH_SEL"
- "NC"
+ "4K_DISP_DCDC_EN"
PM8005:
- "NC"
+ "EAR_EN"
Which is probably due to Maple being designed and released quite a bit
earlier than the other two and it having a super high tech true-4K
display.
Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on QDU1000
and QRU1000 SoCs.
arm64: dts: qcom: apq8096-db820c: drop unit address from PMI8994 regulator
The PMIC regulators are not supposed to have unit addresses.
Fixes: 2317b87a2a6f ("arm64: dts: qcom: db820c: Add vdd_gfx and tie it into mmcc") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230312183622.460488-8-krzysztof.kozlowski@linaro.org
This reverts commit 46546f28825cf3a5ef6873b9cf947cd85c8a7258 because it
mistakenly took PMIC pinctrl/GPIO as TLMM. The TLMM pinctrl uses "gpio"
function, but PMIC uses "normal", so original code was correct:
msm8998-oneplus-cheeseburger.dtb: pmic@2: gpio@c000:button-backlight-state: 'oneOf' conditional failed, one must be fixed:
'gpio' is not one of ['normal', 'paired', 'func1', 'func2', 'dtest1', 'dtest2', 'dtest3', 'dtest4', 'func3', 'func4']
The hid-over-i2c takes VDD, not VCC supply. Fix copy-pasta from other
Herobrine boards which use elan,ekth3000 with valid VCC:
sc7280-herobrine-villager-r1-lte.dtb: trackpad@2c: 'vcc-supply' does not match any of the regexes: 'pinctrl-[0-9]+'
Fixes: ee2a62116015 ("arm64: dts: qcom: sc7280: Add device tree for herobrine villager") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230312183622.460488-2-krzysztof.kozlowski@linaro.org
Stephan Gerhold [Thu, 9 Mar 2023 09:14:52 +0000 (10:14 +0100)]
arm64: dts: qcom: msm8916: Move WCN compatible to boards
On MSM8916 the wireless connectivity functionality (WiFi/Bluetooth) is
split into the digital part inside the SoC and the analog RF part inside
a supplementary WCN36xx chip. For MSM8916, three different options
exist:
Choosing one of these is up to the board vendor. This means that the
compatible belongs into the board-specific DT part so people porting
new boards pay attention to set the correct compatible.
Right now msm8916.dtsi sets "qcom,wcn3620" as default compatible,
which does not work at all for boards that have WCN3660B or WCN3680B.
Remove the default compatible from msm8196.dtsi and move it to the board
DT as follows:
- Boards with only &pronto { status = "okay"; } used the default
"qcom,wcn3620" so far. They now set this explicitly for &wcnss_iris.
- Boards with &pronto { ... iris { compatible = "qcom,wcn3660b"; }};
already had an override that just moves to &wcnss_iris now.
- For msm8916-samsung-a2015-common.dtsi the WCN compatible differs for
boards making use of it (a3u: wcn3620, a5u: wcn3660b, e2015: wcn3620)
so the definitions move to the board-specific DT part.
Since this requires touching all the board DTs, use this as a chance to
name the WCNSS-related labels consistently, so everything is grouped
properly when sorted alphabetically.
No functional change, just clean-up for more clarity & easier porting.
Aside from ordering the generated DTBs are identical.
Douglas Anderson [Thu, 23 Mar 2023 17:30:12 +0000 (10:30 -0700)]
pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLE
The Qualcomm pinctrl driver has been violating the documented meaning
of PIN_CONFIG_INPUT_ENABLE. That documentation says:
Note that this does not affect the pin's ability to drive output.
...yet the Qualcomm driver's sole action when asked to "enable input"
on a pin is to disable its output.
The Qualcomm driver's implementation stems from the fact that
"output-disable" is a "new" property from 2017. It was introduced in
commit 425562429d4f ("pinctrl: generic: Add output-enable
property"). The "input-enable" handling in Qualcomm drivers is from
2015 introduced in commit 407f5e392f9c ("pinctrl: qcom: handle
input-enable pinconf property").
Let's change the Qualcomm driver to move us in the right direction. As
part of this:
1. We'll now support PIN_CONFIG_OUTPUT_ENABLE
2. We'll still support using PIN_CONFIG_INPUT_ENABLE to disable a
pin's output (in violation of the docs) with a big comment in the
code. This is needed because old device trees have "input-enable"
in them and, in some cases, people might need the old
behavior. While we could programmatically change all old device
trees, it doesn't really hurt to keep supporting the old behavior
and we're _supposed_ to try to be compatible with old device trees
anyway.
It can also be noted that the PIN_CONFIG_INPUT_ENABLE handling code
seems to have purposefully ignored its argument. That means that old
boards that had _either_ "input-disable" or "input-enable" in them
would have had the effect of disabling a pin's output. While we could
change this behavior, since we're only leaving the
PIN_CONFIG_INPUT_ENABLE there for backward compatibility we might as
well be fully backward compatible.
NOTE: despite the fact that we'll still support
PIN_CONFIG_INPUT_ENABLE for _setting_ config, we take it away from
msm_config_group_get(). This appears to be only used for populating
debugfs and fixing debugfs to "output enabled" where relevant instead
of "input enabled" makes more sense and has more truthiness.
Douglas Anderson [Thu, 23 Mar 2023 17:30:11 +0000 (10:30 -0700)]
dt-bindings: pinctrl: qcom: Add output-enable
In the patch ("dt-bindings: pinctrl: qcom: tlmm should use
output-disable, not input-enable") we allowed setting "output-disable"
for TLMM pinctrl states. Let's also add "output-enable".
At first blush this seems a needless thing to do. Specifically:
- In Linux (and presumably any other OSes using the same device trees)
the GPIO/pinctrl driver knows to automatically enable the output
when a GPIO is changed to an output. Thus in most cases specifying
"output-enable" is superfluous and should be avoided.
- If we need to set a pin's default state we already have
"output-high" and "output-low" and these properties already imply
"output-enabled" (at least on the Linux Qualcomm TLMM driver).
However, there is one instance where "output-enable" seems like it
could be useful: sleep states. It's not uncommon to want to configure
pins as inputs (with appropriate pulls) when the driver controlling
them is in a low power state. Then we want the pins back to outputs
when the driver wants things running normally. To accomplish this we'd
want to be able to use "output-enable". Then the "default" state could
have "output-enable" and the "sleep" state could have
"output-disable".
NOTE: in all instances I'm aware of, we'd only want to use
"output-enable" on pins that are configured as "gpio". The Qualcomm
documentation that I have access to says that "output-enable" only
does something useful when in GPIO mode.
Douglas Anderson [Thu, 23 Mar 2023 17:30:10 +0000 (10:30 -0700)]
dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable
As evidenced by the Qualcomm TLMM Linux driver, the TLMM IP block in
Qualcomm SoCs has a bit to enable/disable the output for a pin that's
configured as a GPIO but _not_ a bit to enable/disable an input
buffer. Current device trees that are specifying "input-enable" for
pins managed by TLMM are either doing so needlessly or are using it to
mean "output-disable".
Presumably the current convention of using "input-enable" to mean
"output-disable" stems from the fact that "output-disable" is a "new"
property from 2017. It was introduced in commit 425562429d4f
("pinctrl: generic: Add output-enable property"). The "input-enable"
handling in Qualcomm drivers is from 2015 introduced in commit 407f5e392f9c ("pinctrl: qcom: handle input-enable pinconf property").
Given that there's no other use for "input-enable" for TLMM, we can
still handle old device trees in code, but let's encourage people to
move to the proper / documented property by updating the bindings.
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