Jason Merrill [Mon, 14 Oct 2024 20:22:34 +0000 (16:22 -0400)]
c++: rename -fmodules-ts to -fmodules
The C++ modules support is not targeting the Modules TS, so it doesn't make
much sense to refer to the TS in the option name. But keep the old spelling
as an undocumented alias for now.
gcc/ChangeLog:
* doc/invoke.texi: Rename -fmodules-ts to -fmodules.
gcc/c-family/ChangeLog:
* c.opt: Add -fmodules with same effect as -fmodules-ts.
gcc/cp/ChangeLog:
* lang-specs.h: Check fmodules* instead of fmodules-ts.
Jason Merrill [Mon, 11 Nov 2024 02:42:48 +0000 (21:42 -0500)]
opts: fix narrowing warning
The init-list initialization of cl_deferred_option p had a couple of
narrowing warnings: first of opt_index from int to size_t and then of value
from HOST_WIDE_INT to int. Fixed by making the types more consistent.
gcc/ChangeLog:
* opts.h (cl_deferred_option::value): Change to HOST_WIDE_INT.
(set_option): Change opt_index parm to size_t.
* opts-common.cc (set_option): Likewise.
Simon Martin [Mon, 11 Nov 2024 19:22:32 +0000 (20:22 +0100)]
c++: Fix another crash with invalid new operators [PR117463]
Even though this PR is very close to PR117101, it's not addressed by the
fix I made through r15-4958-g5821f5c8c89a05 because cxx_placement_new_fn
has the very same issue as std_placement_new_fn_p used to have.
As suggested by Jason, this patch changes both functions so that
cxx_placement_new_fn leverages std_placement_new_fn_p which reduces code
duplication and fixes the PR.
PR c++/117463
gcc/cp/ChangeLog:
* constexpr.cc (cxx_placement_new_fn): Implement in terms of
std_placement_new_fn_p.
* cp-tree.h (std_placement_new_fn_p): Declare.
* init.cc (std_placement_new_fn_p): Add missing checks to ensure
that fndecl is a non-replaceable ::operator new.
Jakub Jelinek [Mon, 11 Nov 2024 18:54:32 +0000 (19:54 +0100)]
c++: Add __builtin_operator_{new,delete} support
clang++ adds __builtin_operator_{new,delete} builtins which as documented
work similarly to ::operator {new,delete}, except that it is an error
if the called ::operator {new,delete} is not a replaceable global operator
and allow optimizations which C++ normally allows just when those are used
from new/delete expressions https://eel.is/c++draft/expr.new#14
When using these builtins, the same optimizations can be done even when
using those builtins.
For GCC we note that in the CALL_FROM_NEW_OR_DELETE_P flag on CALL_EXPRs.
The following patch implements it as a C++ FE keyword (because passing
references through ... changes the argument and so BUILT_IN_FRONTEND
builtin can't be used), just attempts to call the ::operator {new,delete}
and if it isn't replaceable, diagnoses it.
libstdc++ already uses the builtin in some cases.
2024-11-11 Jakub Jelinek <jakub@redhat.com>
gcc/c-family/
* c-common.h (enum rid): Add RID_BUILTIN_OPERATOR_NEW
and RID_BUILTIN_OPERATOR_DELETE.
(names_builtin_p): Change return type from bool to int.
* c-common.cc (c_common_reswords): Add __builtin_operator_new
and __builtin_operator_delete.
gcc/c/
* c-decl.cc (names_builtin_p): Change return type from
bool to int, adjust return statments.
gcc/cp/
* parser.cc (cp_parser_postfix_expression): Handle
RID_BUILTIN_OPERATOR_NEW and RID_BUILTIN_OPERATOR_DELETE.
* cp-objcp-common.cc (names_builtin_p): Change return type from
bool to int, adjust return statments. Handle
RID_BUILTIN_OPERATOR_NEW and RID_BUILTIN_OPERATOR_DELETE.
* pt.cc (tsubst_expr) <case CALL_EXPR>: Handle
CALL_FROM_NEW_OR_DELETE_P.
gcc/
* doc/extend.texi (New/Delete Builtins): Document
__builtin_operator_new and __builtin_operator_delete.
gcc/testsuite/
* g++.dg/ext/builtin-operator-new-1.C: New test.
* g++.dg/ext/builtin-operator-new-2.C: New test.
* g++.dg/ext/builtin-operator-new-3.C: New test.
Jonathan Wakely [Mon, 11 Nov 2024 11:54:00 +0000 (11:54 +0000)]
libstdc++: Fix typos in iterator increment for std::text_encoding [PR117520]
The intended behaviour for std::text_encoding::aliases_view's iterator
is that it incrementing or decrementing too far sets it to a
value-initialized state, or fails an assertion when those are enabled.
There were typos that used == instead of = which meant that instead of
becoming singular or aborting, an out-of-range increment just did
nothing. This meant erroneous operations were well-defined and didn't
produce any undefined behaviour, but were not diagnosed with assertions
enabled, as had been intended.
This change fixes the bugs and adds more tests to verify the intended
behaviour.
libstdc++-v3/ChangeLog:
PR libstdc++/117520
* include/std/text_encoding (aliases_view:_Iterator::operator+=):
Fix typos that caused == to be used instead of =.
(aliases_view::_Iterator): Fix friend declaration.
* testsuite/std/text_encoding/members.cc: Adjust expected
behaviour of invalid subscript. Add tests for other erroneous
operations on iterators.
Dimitar Dimitrov [Sun, 27 Oct 2024 07:49:49 +0000 (09:49 +0200)]
testsuite: Require atomic operations for c2y-if-decls-*
Since some of the c2y-if-decls tests use _Atomic, add a
requirement for target to support atomic operations on
int and long types.
This fixes spurious test link failures on pru-unknown-elf,
which lacks atomic ops. The tests still pass on x86_64-linux-gnu.
gcc/testsuite/ChangeLog:
* gcc.dg/c2y-if-decls-1.c: Require target that supports atomic
operations on int and long types.
* gcc.dg/c2y-if-decls-11.c: Ditto.
* gcc.dg/c2y-if-decls-4.c: Ditto.
* gcc.dg/c2y-if-decls-8.c: Ditto.
According to the aapcs64: If the argument is an 8-bit (...) precision
Floating-point or short vector type and the NSRN is less than 8, then the
argument is allocated to the least significant bits of register v[NSRN].
gcc/
* config/aarch64/aarch64.cc
(aarch64_vfp_is_call_or_return_candidate): use fp registers to
return svmfloat8_t parameters.
Jason Merrill [Tue, 5 Nov 2024 15:27:39 +0000 (10:27 -0500)]
c++: reduce unnecessary tree_common
Lewis' r15-5067 fixing the marking of TRAIT_EXPR led me to compare some
other front-end type definitions to their marking in cp_common_init_ts; it
seems we can change tree_common to something smaller in several cases, to
match how they are marked.
gcc/cp/ChangeLog:
* cp-tree.h (struct ptrmem_cst): Change tree_common to tree_typed.
(struct tree_trait_expr): Likewise.
(struct tree_static_assert): Change tree_common to tree_base.
(struct tree_argument_pack_select): Likewise.
Tobias Burnus [Mon, 11 Nov 2024 16:22:20 +0000 (17:22 +0100)]
libgomp.c-c++-common/pr109062.c: Fix expected spin count for hybrid x86
On my system with E and P cores (hybrid) x86, the spincount is by default 1
and not 300000, cf. PR109812 and r14-4571-ge1e127de18dbee.
Hence, this commit updates the expected value of the testcase to also
accept omp_display_env showing "GOMP_SPINCOUNT = '1'" - but only for
x86-64, which might be hybrid.
libgomp/ChangeLog:
* testsuite/libgomp.c-c++-common/pr109062.c: Update dg-output
to also accept GOMP_SPINCOUNT = 1 for x86-64.
Richard Biener [Fri, 8 Nov 2024 12:59:05 +0000 (13:59 +0100)]
Add missing SLP discovery for CFN[_MASK][_LEN]_SCATTER_STORE
This was responsible for a bunch of SVE FAILs with --param vect-force-slp=1
* tree-vect-slp.cc (arg1_arg3_map): New.
(arg1_arg3_arg4_map): Likewise.
(vect_get_operand_map): Handle IFN_SCATTER_STORE,
IFN_MASK_SCATTER_STORE and IFN_MASK_LEN_SCATTER_STORE.
(vect_build_slp_tree_1): Likewise.
* tree-vect-stmts.cc (vectorizable_store): For SLP masked
gather/scatter record the mask with proper number of copies.
* tree-vect-loop.cc (vectorizable_recurr): Avoid costing
the initial value construction in the prologue twice with SLP.
This patch adds the instructions that are new to FEAT_SVE2p1.
It mostly contains simple additions, so it didn't seem worth
splitting up further.
It's likely that we'll find more autovec uses for some of these
instructions, but for now this patch just deals with one obvious case:
using the new hybrid-VLA permutations to handle "stepped" versions of
some Advanced SIMD permutations. See aarch64_evpc_hvla for details.
The patch also continues the existing practice of lowering ACLE
permutation intrinsics to VEC_PERM_EXPR. That's admittedly a bit
inconsistent with the approach I've been advocating for when it comes
to arithmetic, but I think the difference is that (a) these are pure
data movement, and so there's limited scope for things like gimple
canonicalisations to mess with the instruction selection or operation
mix; and (b) there are no added UB rules to worry about.
Another new thing in the patch is the concept of "memory-only"
SVE vector modes. These are used to represent the memory operands
of the new LD1[DW] (to .Q), LD[234]Q, ST1[DW] (from .Q), and ST[234]Q
instructions. We continue to use .B, .H, .S, and .D modes for the
registers, since there's no predicated contiguous LD1Q instruction,
and since there's no arithmetic that can be done on TI. (The new
instructions are instead intended for hybrid VLA, i.e. for vectors
of vectors.)
For now, all of the new instructions are non-streaming-only.
Some of them are streaming-compatible with SME2p1, but that's
a later patch.
gcc/
* config/aarch64/aarch64-modes.def (VNx1SI, VNx1DI): New modes.
* config/aarch64/aarch64-sve-builtins-base.cc
(svdup_lane_impl::expand): Update generation of TBL instruction.
(svtbl_impl): Delete.
(svtbl): Use unspec_based_uncond_function instead.
* config/aarch64/aarch64-sve-builtins-functions.h
(permute::fold_permute): Handle trailing immediate arguments.
* config/aarch64/aarch64-sve-builtins-shapes.h (extq): Declare.
(load_gather64_sv_index, load_gather64_sv_offset): Likewise.
(load_gather64_vs_index, load_gather64_vs_offset): Likewise.
(pmov_from_vector, pmov_from_vector_lane, pmov_to_vector_lane)
(reduction_neonq, store_scatter64_index, store_scatter64_offset)
(unary_lane): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc
(load_gather64_sv_base, store_scatter64_base): New classes.
(extq_def, ext): New shape.
(load_gather64_sv_index_def, load_gather64_sv_index): Likewise.
(load_gather64_sv_offset_def, load_gather64_sv_offset): Likewise.
(load_gather64_vs_index_def, load_gather64_vs_index): Likewise.
(load_gather64_vs_offset_def, load_gather64_vs_offset): Likewise.
(pmov_from_vector_def, pmov_from_vector): Likewise.
(pmov_from_vector_lane_def, pmov_from_vector_lane): Likewise.
(pmov_to_vector_lane_def, pmov_to_vector_lane): Likewise.
(reduction_neonq_def, reduction_neonq): Likewise.
(store_scatter64_index_def, store_scatter64_index): Likewise.
(store_scatter64_offset_def, store_scatter64_offset): Likewise.
(unary_lane_def, unary_lane): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.h (svaddqv, svandqv)
(svdup_laneq, sveorqv, svextq, svld1q_gather, svld1udq, svld1uwq)
(svld2q, svld3q, svld4q, svmaxnmqv, svmaxqv, svminnmqv, svminqv)
(svorqv, svpmov, svpmov_lane, svst1qd, svst1q_scatter, svst1wq)
(svst2q, svst3q, svst4q, svtblq, svtbx, svtbxq, svuzpq1, svuzpq2)
(svzipq1, svzipq2): Declare.
* config/aarch64/aarch64-sve-builtins-sve2.cc (ld1uxq_st1xq_base)
(ld234q_st234q_base, svdup_laneq_impl, svextq_impl): New classes.
(svld1q_gather_impl, svld1uxq_impl, svld234q_impl): Likewise.
(svpmov_impl, svpmov_lane_impl, svst1q_scatter_impl): Likewise.
(svst1xq_impl, svst234q_impl, svuzpq_impl, svzipq_impl): Likewise.
(svaddqv, svandqv, svdup_laneq, sveorqv, svextq, svld1q_gather)
(svld1udq, svld1uwq, svld2q, svld3q, svld4q, svmaxnmqv, svmaxqv)
(svminnmqv, svminqv, svorqv, svpmov, svpmov_lane, svst1qd)
(svst1q_scatter, svst1wq, svst2q, svst3q, svst4q, svtblq, svtbx)
(svtbxq, svuzpq1, svuzpq2, svzipq1, svzipq2): New function entries.
* config/aarch64/aarch64-sve-builtins-sve2.def (svaddqv, svandqv)
(svdup_laneq, sveorqv, svextq, svld2q, svld3q, svld4q, svmaxnmqv)
(svmaxqv, svminnmqv, svminqv, svorqv, svpmov, svpmov_lanes, vst2q)
(svst3q, svst4q, svtblq, svtbxq, svuzpq1, svuzpq2, svzipq1, svzipq2)
(svld1q_gather, svld1udq, svld1uwq, svst1dq, svst1q_scatter)
(svst1wq): New function definitions.
* config/aarch64/aarch64-sve-builtins.cc (TYPES_hsd_data)
(hsd_data, s_data): New type lists.
(function_resolver::infer_pointer_type): Give a specific error about
passing a pointer to 8-bit elements to an _index function.
(function_resolver::resolve_sv_displacement): Check whether the
function allows 32-bit bases.
* config/aarch64/iterators.md (UNSPEC_TBLQ, UNSPEC_TBXQ): New unspecs.
(UNSPEC_ADDQV, UNSPEC_ANDQV, UNSPEC_DUPQ, UNSPEC_EORQV, UNSPEC_EXTQ)
(UNSPEC_FADDQV, UNSPEC_FMAXQV, UNSPEC_FMAXNMQV, UNSPEC_FMINQV)
(UNSPEC_FMINNMQV, UNSPEC_LD1_EXTENDQ, UNSPEC_LD1Q_GATHER): Likewise.
(UNSPEC_LDNQ, UNSPEC_ORQV, UNSPEC_PMOV_PACK, UNSPEC_PMOV_PACK_LANE)
(UNSPEC_PMOV_UNPACK, UNSPEC_PMOV_UNPACK_LANE, UNSPEC_SMAXQV): Likewise.
(UNSPEC_SMINQV, UNSPEC_ST1_TRUNCQ, UNSPEC_ST1Q_SCATTER, UNSPEC_STNQ)
(UNSPEC_UMAXQV, UNSPEC_UMINQV, UNSPEC_UZPQ1, UNSPEC_UZPQ2): Likewise.
(UNSPEC_ZIPQ1, UNSPEC_ZIPQ2): Likewise.
(Vtype): Handle single-vector SVE modes.
(Vendreg): Handle SVE structure modes.
(VNxTI, LD1_EXTENDQ_MEM): New mode attributes.
(SVE_PERMUTE, SVE_TBL, SVE_TBX): New int iterators.
(SVE_INT_REDUCTION_128, SVE_FP_REDUCTION_128): Likewise.
(optab): Handle the new SVE2.1 reductions.
(perm_insn): Handle the new SVE2.1 permutations.
* config/aarch64/aarch64-sve.md
(@aarch64_sve_tbl<mode>): Generalize to...
(@aarch64_sve_<SVE_TBL:perm_insn><mode>): ...this.
(@aarch64_sve_<PERMUTE:perm_insn><mode>): Generalize to...
(@aarch64_sve_<SVE_PERMUTE:perm_insn><mode>): ...this.
* config/aarch64/aarch64-sve2.md (@aarch64_pmov_to_<mode>)
(@aarch64_pmov_lane_to_<mode>, @aarch64_pmov_from_<mode>)
(@aarch64_pmov_lane_from_<mode>, @aarch64_sve_ld1_extendq<mode>)
(@aarch64_sve_ldnq<mode>, aarch64_gather_ld1q): New patterns.
(@aarch64_sve_st1_truncq<mode>, @aarch64_sve_stnq<mode>): Likewise.
(aarch64_scatter_st1q, @aarch64_pred_reduc_<optab>_<mode>): Likewise.
(@aarch64_sve_dupq<mode>, @aarch64_sve_extq<mode>): Likewise.
(@aarch64_sve2_tbx<mode>): Generalize to...
(@aarch64_sve_<SVE_TBX:perm_insn><mode>): ...this.
* config/aarch64/aarch64.cc
(aarch64_classify_vector_memory_mode): New function.
(aarch64_regmode_natural_size): Use it.
(aarch64_classify_index): Likewise.
(aarch64_classify_address): Likewise.
(aarch64_print_address_internal): Likewise.
(aarch64_evpc_hvla): New function.
(aarch64_expand_vec_perm_const_1): Use it.
This patch handles the SVE2p1 instructions that are shared
with SME2. This includes the consecutive-register forms of
the 2-register and 4-register loads and stores, but not the
strided-register forms.
gcc/
* config/aarch64/aarch64.h (TARGET_SVE2p1_OR_SME2): New macro.
* config/aarch64/aarch64-early-ra.cc
(is_stride_candidate): Require TARGET_STREAMING_SME2
(early_ra::maybe_convert_to_strided_access): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.def: Mark instructions
that are common to both SVE2p1 and SME2.
* config/aarch64/aarch64-sve.md
(@aarch64_<sur>dot_prod_lane<SVE_FULL_SDI:mode><SVE_FULL_BHI:mode>):
Test TARGET_SVE2p1_OR_SME2 instead of TARGET_STREAMING_SME2.
(@aarch64_sve_<sve_fp_op>vnx4sf): Move TARGET_SVE_BF16 condition
into SVE_BFLOAT_TERNARY_LONG.
(@aarch64_sve_<sve_fp_op>_lanevnx4sf): Likewise
SVE_BFLOAT_TERNARY_LONG_LANE.
* config/aarch64/aarch64-sve2.md
(@aarch64_<LD1_COUNT:optab><mode>): Require TARGET_SVE2p1_OR_SME2
instead of TARGET_STREAMING_SME2.
(@aarch64_<ST1_COUNT:optab><mode>): Likewise.
(@aarch64_sve_ptrue_c<BHSD_BITS>): Likewise.
(@aarch64_sve_pext<BHSD_BITS>): Likewise.
(@aarch64_sve_pext<BHSD_BITS>x2): Likewise.
(@aarch64_sve_cntp_c<BHSD_BITS>): Likewise.
(@aarch64_sve_fclamp<mode>): Likewise.
(*aarch64_sve_fclamp<mode>_x): Likewise.
(<sur>dot_prodvnx4sivnx8hi): Likewise.
(aarch64_sve_fdotvnx4sfvnx8hf): Likewise.
(aarch64_fdot_prod_lanevnx4sfvnx8hf): Likewise.
(@aarch64_sve_while<while_optab_cmp>_b<BHSD_BITS>_x2): Likewise.
(@aarch64_sve_while<while_optab_cmp>_c<BHSD_BITS>): Likewise.
(@aarch64_sve_<optab><VNx8HI_ONLY:mode><VNx8SI_ONLY:mode>): Move
TARGET_STREAMING_SME2 condition into SVE_QCVTxN.
(@aarch64_sve_<sve_int_op><mode>): Likewise
SVE2_INT_SHIFT_IMM_NARROWxN, but also require TARGET_STREAMING_SME2
for the 4-register forms.
* config/aarch64/iterators.md (SVE_BFLOAT_TERNARY_LONG): Require
TARGET_SVE2p1_OR_SME2 rather than TARGET_STREAMING_SME2 for
UNSPEC_BFMLSLB and UNSPEC_BFMLSLT. Require TARGET_SVE_BF16
for the others.
(SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
(SVE2_INT_SHIFT_IMM_NARROWxN): Require TARGET_SVE2p1_OR_SME2 for
the interleaving forms and TARGET_STREAMING_SME2 for the rest.
(SVE_QCVTxN): Likewise.
Some instructions that were previously restricted to streaming mode
can also be used in non-streaming mode with SVE2.1. This patch adds
support for those, as well as the usual new-extension boilerplate.
A later patch will add the feature macro.
gcc/
* config/aarch64/aarch64-option-extensions.def (sve2p1): New extension.
* doc/invoke.texi (sve2p1): Document it.
* config/aarch64/aarch64-sve-builtins-sve2.def: Mark instructions
that are common to both SVE2p1 and SME.
* config/aarch64/aarch64.h (TARGET_SVE2p1): New macro.
(TARGET_SVE2p1_OR_SME): Likewise.
* config/aarch64/aarch64-sve2.md
(@aarch64_sve_psel<BHSD_BITS>): Require TARGET_SVE2p1_OR_SME
instead of TARGET_STREAMING.
(*aarch64_sve_psel<BHSD_BITS>_plus): Likewise.
(@aarch64_sve_<su>clamp<mode>): Likewise.
(*aarch64_sve_<su>clamp<mode>_x): Likewise.
(@aarch64_pred_<optab><mode>): Likewise.
(@cond_<optab><mode>): Likewise.
This patch moves the scalar and single-vector Advanced SIMD types
from arm_neon.h into a private header, so that they can be defined
by arm_sve.h as well. This is needed for the upcoming SVE2.1
hybrid-VLA reductions, which return 128-bit Advanced SIMD vectors.
The approach follows Claudio's patch for FP8.
gcc/
* config.gcc (extra_headers): Add arm_private_neon_types.h.
* config/aarch64/arm_private_neon_types.h: New file, split out
from...
* config/aarch64/arm_neon.h: ...here.
* config/aarch64/arm_sve.h: Include arm_private_neon_types.h
This patch adds an svboolx4_t type, to go alongside the existing
svboolx2_t type. It doesn't require any special ISA support beyond
SVE itself and it currently has no associated instructions.
All extending gather load intrinsics encode the source type in
their name (e.g. svld1sb for an extending load from signed bytes).
The type of the extension result has to be specified using an
explicit type suffix; it isn't something that can be inferred
from the arguments, since there are multiple valid choices for
the same arguments.
This meant that type inference for gather loads was only needed for
non-extending loads, in which case the pointer target had to be a
32-bit or 64-bit element type. The gather_scatter_p argument to
function_resolver::infer_pointer_type therefore controlled two things:
how we should react to vector base addresses, and whether we should
require a minimum element size of 32.
The element size restriction doesn't apply to the upcomding SVE2.1
svld1q intrinsic, so this patch adds a separate argument for the minimum
element size requirement.
gcc/
* config/aarch64/aarch64-sve-builtins.h
(function_resolver::target_type_restrictions): New enum.
(function_resolver::infer_pointer_type): Add an extra argument
that specifies what the target type can be.
* config/aarch64/aarch64-sve-builtins.cc
(function_resolver::infer_pointer_type): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc
(load_gather_sv_base::get_target_type_restrictions): New virtual
member function.
(load_gather_sv_base::resolve): Use it. Update call to
infer_pointer_type.
aarch64: Add an abstraction for scatter store type inference
Until now, all data arguments to a scatter store needed to have
32-bit or 64-bit elements. This isn't true for the upcoming SVE2.1
svst1q scatter intrinsic, so this patch adds an abstraction around the
restriction.
gcc/
* config/aarch64/aarch64-sve-builtins-shapes.cc
(store_scatter_base::infer_vector_type): New virtual member function.
(store_scatter_base::resolve): Use it.
aarch64: Add an abstraction for vector base addresses
In the upcoming SVE2.1 svld1q and svst1q intrinsics, the relationship
between the base vector and the data vector differs from existing
gather/scatter intrinsics. This patch adds a new abstraction to
handle the difference.
gcc/
* config/aarch64/aarch64-sve-builtins.h
(function_shape::vector_base_type): New member function.
* config/aarch64/aarch64-sve-builtins.cc
(function_shape::vector_base_type): Likewise.
(function_resolver::resolve_sv_displacement): Use it.
(function_resolver::resolve_gather_address): Likewise.
GCC previously used the older assembly syntax for SVE TBL, with no
braces around the second operand. This patch switches to the newer,
official syntax, with braces around the operand.
The initial SVE binutils submission supported both syntaxes, so there
should be no issues with backwards compatibility.
gcc/
* config/aarch64/aarch64-sve.md (@aarch64_sve_tbl<mode>): Wrap
the second operand in braces.
Past extensions to SVE have required new subsets of all_data; the
SVE2.1 patches will add another. This patch tries to make this more
scalable by defining the multi-size *_data macros to be unions of
single-size *_data macros.
gcc/
* config/aarch64/aarch64-sve-builtins.cc (TYPES_all_data): Redefine
in terms of single-size *_data definitions.
(TYPES_bhs_data, TYPES_hs_data, TYPES_sd_data): Likewise.
(TYPES_b_data, TYPES_h_data, TYPES_s_data): New macros.
aarch64: Test TARGET_STREAMING instead of TARGET_STREAMING_SME
g:ede97598e2c recorded separate ISA requirements for streaming
and non-streaming mode. The premise there was that AARCH64_FL_SME
should not be included in the streaming mode requirements, since:
(a) an __arm_streaming_compatible function wouldn't be in streaming
mode if SME wasn't available.
(b) __arm_streaming_compatible functions only allow things that are
possible in non-streaming mode, so the non-streaming architecture
is enough to assemble the code, even if +sme isn't enabled.
(c) we reject __arm_streaming if +sme isn't enabled, so don't need
to test it for individual intrinsics as well.
Later patches lean into this further.
This patch applies the same reasoning to the .md constructs for
base streaming-only SME instructions, guarding them with
TARGET_STREAMING rather than TARGET_STREAMING_SME.
gcc/
* config/aarch64/aarch64.h (TARGET_SME): Expand comment.
(TARGET_STREAMING_SME): Delete.
* config/aarch64/aarch64-sme.md: Use TARGET_STREAMING instead of
TARGET_STREAMING_SME.
* config/aarch64/aarch64-sve2.md: Likewise.
Some code was checking TARGET_STREAMING and TARGET_SME2 separately,
but we now have a macro to test both at once.
gcc/
* config/aarch64/aarch64-sme.md: Use TARGET_STREAMING_SME2
instead of separate TARGET_STREAMING and TARGET_SME2 tests.
* config/aarch64/aarch64-sve2.md: Likewise.
* config/aarch64/iterators.md: Likewise.
For the aarch64 simd clones patches, it would be useful to be able to
push a function declaration onto the cfun stack, even though it has no
function body associated with it. That is, we want cfun to be null,
current_function_decl to be the decl itself, and the target and
optimisation flags to reflect the declaration.
This patch adds a push/pop_function_decl pair to do that.
I think the more direct way of doing what I want to do under the
existing interface would have been:
where invoke_set_current_function_hook would need to become public.
But it seemed safer to use the higher-level routines, since it makes
sure that the target/optimisation changes are synchronised with the
function changes. In particular, if cfun was null before the
sequence above, the pop_cfun would leave the flags unchanged,
rather than restore them to the state before the push_cfun.
gcc/
* function.h (push_function_decl, pop_function_decl): Declare.
* function.cc (set_function_decl): New function, extracted from...
(set_cfun): ...here.
(push_function_decl): New function, extracted from...
(push_cfun): ...here.
(pop_cfun_1): New function, extracted from...
(pop_cfun): ...here.
(pop_function_decl): New function.
Paul Thomas [Mon, 11 Nov 2024 12:21:57 +0000 (12:21 +0000)]
Fortran: Fix elemental array refs in SELECT TYPE [PR109345]
2024-11-10 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran
PR fortran/109345
* trans-array.cc (gfc_get_array_span): Unlimited polymorphic
expressions are now treated separately since the span need not
be the same as the element size.
For the loop in the testcase we currently fail to hoist the guard
check of the inner loop (m > 0) out of the outer loop because
find_loop_guard checks all blocks of the outer loop for side-effects,
including those that are skipped by the guard. This usually
is harmless as the guard does not skip any blocks in the outer loop
but in this case store-motion was applied to the inner loop and thus
there's now a skipped store in the outer loop.
The following properly skips blocks that are dominated by the
entry to the skipped region.
PR tree-optimization/117510
* tree-ssa-loop-unswitch.cc (find_loop_guard): Only check
not skipped blocks for side-effects.
* gcc.dg/vect/vect-outer-pr117510.c: New testcase.
Gaius Mulley [Mon, 11 Nov 2024 11:43:06 +0000 (11:43 +0000)]
modula2: Reimplement parameter declaration and checking.
This patch improves the parameter declaration by saving all parameter
kinds: proper procedure, definition module procedure and forward
procedures. This allows error messages to reference any parameter
in the three kinds of procedures. Variables and their declaration
are also stored. The expression, assignment and parameter checking
has been improved to highlight any variable or parameter and
its declaration causing a conflict.
gcc/m2/ChangeLog:
* gm2-compiler/M2Base.def (MixTypes): Rename parameters.
(MixTypesDecl): New procedure function.
* gm2-compiler/M2Base.mod (BuildOrdFunctions): Add
DefProcedure parameter to PutFunction.
(BuildTruncFunctions): Ditto.
(BuildFloatFunctions): Ditto.
(BuildIntFunctions): Ditto.
(InitBaseFunctions): Ditto.
(MixTypesDecl): New procedure function.
(MixTypes): Reimplement.
* gm2-compiler/M2Check.mod (checkProcType): Replace
NoOfParam with NoOfParamAny.
Replace IsVarParam with IsVarParamAny.
(checkProcedureProcType): Ditto.
* gm2-compiler/M2Error.def: Remove unnecessary export qualified list.
* gm2-compiler/M2GCCDeclare.mod: Replace NoOfParam with NoOfParamAny.
Replace IsVarParam with IsVarParamAny.
(DeclareProcedureToGccWholeProgram): Rename son to
Variable.
(DeclareProcedureToGccSeparateProgram): Ditto.
(PrintKind): New procedure.
(PrintProcedureParameters): Ditto.
(PrintProcedureReturnType): Ditto.
(PrintProcedure): Reimplement.
(PrintProcTypeParameters): New procedure.
(PrintProcType): Ditto.
(DeclareProcType): Rename Son to Parameter.
* gm2-compiler/M2GenGCC.mod: Replace NoOfParam with NoOfParamAny.
Replace IsVarParam with IsVarParamAny.
(ErrorMessageDecl): New procedure.
(checkIncorrectMeta): Replace call to MetaErrorT2 with
ErrorMessageDecl.
(ComparisonMixTypes): Add varleft and varright parameters.
Adjust all callers of ComparisonMixTypes.
* gm2-compiler/M2MetaError.def (MetaErrorDecl): New procedure.
* gm2-compiler/M2MetaError.mod (MetaErrorDecl): New procedure.
* gm2-compiler/M2Options.def (SetXCode): Add -fd flag description
to comment.
* gm2-compiler/M2Options.mod (SetXCode): Add -fd flag description
to comment.
* gm2-compiler/M2Quads.mod (CheckBreak): New procedure.
Replace NoOfParam with NoOfParamAny.
Replace IsVarParam with IsVarParamAny.
(FailParameter): Reimplement using GetVarDeclFullTok.
Generate message for formal parameter, actual parameter and
declaration of actual parameter.
(WarnParameter): Ditto.
(CheckBuildFunction): Reimplement error message using MetaErrorT1.
* gm2-compiler/M2Range.mod: Replace NoOfParam with NoOfParamAny.
Replace IsVarParam with IsVarParamAny.
* gm2-compiler/M2Scaffold.mod (DeclareScaffoldFunctions): Call
PutProcedureDefined after every procedure declaration.
(DeclareArgEnvParams): Add ProperProcedure parameter to PutParam.
* gm2-compiler/M2Size.mod (MakeSize): Add DefProcedure parameter
to PutFunction.
* gm2-compiler/M2Swig.mod: Replace NoOfParam with NoOfParamAny.
Replace IsVarParam with IsVarParamAny.
* gm2-compiler/M2SymInit.mod: Ditto.
* gm2-compiler/M2System.mod (InitSystem): Add DefProcedure
parameter to PutFunction.
* gm2-compiler/P1SymBuild.mod (StartBuildProcedure): Reimplement.
(EndBuildProcedure): Ditto.
(EndBuildForward): Ditto.
* gm2-compiler/P2Build.bnf (BuildProcedureDefinedByForward):
Remove.
(BuildProcedureDefinedByProper): Ditto.
(ForwardDeclaration): Remove BuildProcedureDefinedByForward.
(BuildNoReturnAttribute): Remove parameter.
* gm2-compiler/P2SymBuild.def (BuildNoReturnAttribute): Remove
parameter.
(BuildProcedureDefinedByForward): Remove.
(BuildProcedureDefinedByProper): Ditto.
* gm2-compiler/P2SymBuild.mod (Import): Remove
AreParametersDefinedInDefinition,
AreParametersDefinedInImplementation,
AreProcedureParametersDefined,
ParametersDefinedInDefinition,
ParametersDefinedInImplementation,
GetProcedureDeclaredDefinition,
GetProcedureDeclaredForward,
GetProcedureDeclaredProper,
GetParametersDefinedByForward,
GetParametersDefinedByProper and
PutProcedureNoReturn.
Add PutProcedureParametersDefined,
GetProcedureParametersDefined,
GetProcedureKindDesc,
GetProcedureDeclaredTok,
GetProcedureKind,
GetReturnTypeTok,
SetReturnOptional,
IsReturnOptional,
PutProcedureNoReturn and
PutProcedureDefined.
(Debug): New procedure.
(P2StartBuildDefModule): Space formatting.
(BuildVariable): Reimplement to record full declaration.
(StartBuildProcedure): Reimplement using token to determine
the kind of procedure.
(BuildProcedureHeading): Ditto.
(BuildFPSection): Ditto.
(BuildVarArgs): Ditto.
(BuildOptArg): Ditto.
(BuildProcedureDefinedByForward): Remove.
(BuildProcedureDefinedByProper): Ditto.
(BuildFormalParameterSection): Reimplement so that the
quad stack is unchanged.
(CheckFormalParameterSection): Ditto.
(RemoveFPParameters): New procedure.
(ParameterError): Reimplement.
(StartBuildFormalParameters): Add annotation.
(ParameterMismatch): Reimplement.
(EndBuildFormalParameters): Reimplement to check against
all procedure kinds.
(GetSourceDesc): Remove.
(GetCurSrcDesc): Ditto.
(GetDeclared): Ditto.
(ReturnTypeMismatch): Reimplement.
(BuildFunction): Ditto.
(BuildOptFunction): Ditto.
(CheckOptFunction): New procedure.
(BuildNoReturnAttribute): Remove parameter and obtain
procedure symbol from quad stack.
(CheckProcedureReturn): New procedure.
* gm2-compiler/P3SymBuild.mod (BuildOptArgInitializer):
Preserve ProcSym tok on the quad stack.
Add Assert.
* gm2-compiler/PCSymBuild.mod (fixupProcedureType): Replace
NoOfParam with NoOfParamAny.
* gm2-compiler/SymbolTable.def (GetNthParam): Add ProcedureKind
parameter.
(PutFunction): Ditto.
(PutOptFunction): Ditto.
(IsReturnOptional): Ditto.
(PutParam): Ditto.
(PutVarParam): Ditto.
(PutParamName): Ditto.
(PutProcedureNoReturn): Ditto.
(IsProcedureNoReturn): Ditto.
(IsVarParam): Ditto.
(IsUnboundedParam): Ditto.
(NoOfParam): Ditto.
(ForeachLocalSymDo): Ditto.
(GetProcedureKind): Ditto.
(GetProcedureDeclaredTok): Ditto.
(PutProcedureDeclaredTok): Ditto.
(GetReturnTypeTok): Ditto.
(PutReturnTypeTok): Ditto.
(PutParametersDefinedByForward): New procedure.
(PutProcedureParametersDefined): Ditto.
(PutProcedureDefined): Ditto.
(GetParametersDefinedByProper): Ditto.
(GetProcedureDeclaredForward): Ditto.
(GetProcedureDeclaredProper): Ditto.
(PutProcedureDeclaredProper): Ditto.
(GetProcedureDeclaredDefinition): Ditto.
(PutProcedureDeclaredDefinition): Ditto.
(GetProcedureDefined): Ditto.
(PutUseOptArg): Ditto.
(UsesOptArg): Ditto.
(PutOptArgInit): Ditto.
(SetReturnOptional): Ditto.
(UsesOptArgAny): Ditto.
(GetProcedureKindDesc): Ditto.
(IsReturnOptionalAny): New procedure function.
(GetNthParamAny): Ditto.
(NoOfParamAny): Ditto.
(IsProcedureAnyNoReturn): Ditto.
(AreParametersDefinedInImplementation): Remove.
(ParametersDefinedInImplementation): Ditto.
(AreParametersDefinedInDefinition): Ditto.
(AreProcedureParametersDefined): Ditto.
(ParametersDefinedInDefinition): Ditto.
(ProcedureParametersDefined): Ditto.
(PutParametersDefinedByProper): Ditto.
(PutProcedureDeclaredForward): Ditto.
(GetParametersDefinedByForward): Ditto.
(GetProcedureParametersDefined): Ditto.
(PushOffset): Ditto.
(PopSize): Ditto.
(PushParamSize): Ditto.
(PushSumOfLocalVarSize): Ditto.
(PushSumOfParamSize): Ditto.
(PopOffset): Ditto.
(PopSumOfParamSize): Ditto.
* gm2-compiler/SymbolTable.mod (MakeProcedure): Reimplement.
(PutProcedureNoReturn): Add ProcedureKind parameter.
(GetNthParam): Ditto.
(PutFunction): Ditto.
(PutOptFunction): Ditto.
(IsReturnOptional): Ditto.
(MakeVariableForParam): Ditto.
(PutParam): Ditto.
(PutVarParam): Ditto.
(PutParamName): Ditto.
(AddParameter): Ditto.
(IsVarParam): Ditto.
(IsVarParamAny): Ditto.
(NoOfParam): Ditto.
(HasVarParameters): Ditto.
(IsUnboundedParam): Ditto.
(PutUseVarArgs): Ditto.
(UsesVarArgs): Ditto.
(PutUseOptArg): Ditto.
(UsesOptArg): Ditto.
(UsesOptArgAny): Ditto.
(PutOptArgInit): Ditto.
(IsProcedure): Ditto.
(IsPointer): Ditto.
(IsRecord): Ditto.
(IsArray): Ditto.
(IsEnumeration): Ditto.
(IsUnbounded): Ditto.
(IsSet): Ditto.
(IsSetPacked): Ditto.
(CheckUnbounded): Ditto.
(IsOAFamily): Ditto.
(IsModuleWithinProcedure): Ditto.
(GetDeclaredDef): Ditto.
(GetDeclaredMod): Ditto.
(GetDeclaredFor): Ditto.
(GetProcedureDeclaredForward): Ditto.
(GetProcedureKind): Ditto.
(PutProcedureDeclaredForward): Ditto.
(GetProcedureDeclaredTok): Ditto.
(GetProcedureDeclaredProper): Ditto.
(PutProcedureDeclaredTok): Ditto.
(PutProcedureDeclaredProper): Ditto.
(GetReturnTypeTok): Ditto.
(GetProcedureDeclaredDefinition): Ditto.
(PutReturnTypeTok): Ditto.
(PutProcedureDeclaredDefinition): Ditto.
(GetProcedureKindDesc): Ditto.
(IsProcedureVariable): Ditto.
(IsAModula2Type): Ditto.
(GetParam): Ditto.
(ProcedureParametersDefined): Ditto.
(AreParametersDefinedInImplementation): Remove.
(AreParametersDefinedInDefinition): Ditto.
(AreProcedureParametersDefined): Ditto.
(IsSizeSolved): Ditto.
(IsOffsetSolved): Ditto.
(IsValueSolved): Ditto.
(IsSumOfParamSizeSolved): Ditto.
(PushSize): Ditto.
(PushOffset): Ditto.
(PopSize): Ditto.
(PushValue): Ditto.
(PushParamSize): Ditto.
(PushSumOfLocalVarSize): Ditto.
(PushSumOfParamSize): Ditto.
(PushVarSize): Ditto.
(PopValue): Ditto.
(PopSize): Ditto.
(PopOffset): Ditto.
(PopSumOfParamSize): Ditto.
(PutParametersDefinedByForward): New procedure.
(PutProcedureParametersDefined): Ditto.
(PutProcedureDefined): Ditto.
(GetParametersDefinedByProper): Ditto.
(GetProcedureDeclaredForward): Ditto.
(GetProcedureDeclaredProper): Ditto.
(PutProcedureDeclaredProper): Ditto.
(GetProcedureDeclaredDefinition): Ditto.
(PutProcedureDeclaredDefinition): Ditto.
(GetProcedureDefined): Ditto.
(PutUseOptArg): Ditto.
(UsesOptArg): Ditto.
(PutOptArgInit): Ditto.
(SetReturnOptional): Ditto.
(UsesOptArgAny): Ditto.
(GetProcedureKindDesc): Ditto.
(PutParametersDefinedByProper): Ditto.
(GetParametersDefinedByProper): Ditto.
(IsReturnOptionalAny): New procedure function.
(IsProcedureAnyDefaultBoolean): Ditto.
(IsProcedureAnyBoolean): Ditto.
(IsProcedureAnyNoReturn): Ditto.
(GetNthParamAny): Ditto.
(NoOfParamAny): Ditto.
(IsProcedureAnyNoReturn): Ditto.
(GetProcedureKind): Ditto.
(IsVarParamAny): Ditto.
(IsUnboundedParamAny): Ditto.
(ForeachParamSymDo): New comment.
* gm2-libs-coroutines/SYSTEM.mod: Reformat.
gcc/testsuite/ChangeLog:
* gm2/iso/fail/badexpression3.mod: New test.
* gm2/iso/fail/badparam4.def: New test.
* gm2/iso/fail/badparam4.mod: New test.
Pan Li [Mon, 11 Nov 2024 07:39:40 +0000 (15:39 +0800)]
RISC-V: Fix one nit indent issue of ustrunc pattern [NFC]
Just notice the indent is not that right for ustrunc pattern from
the md files. Thus, make it correct. It is somehow very obvious
and will commit it after next 48H if no more comments.
gcc/ChangeLog:
* config/riscv/autovec.md: Fix indent format issue.
Thomas Koenig [Sat, 9 Nov 2024 18:24:43 +0000 (19:24 +0100)]
Reject UNSIGNED for Complex, some documentation fixes.
gcc/fortran/ChangeLog:
* check.cc (gfc_check_complex): Reject UNSIGNED.
* gfortran.texi: Update example program. Note that
CMPLX, INT and REAL also take unsigned arguments.
* intrinsic.texi (CMPLX): Document UNSIGNED.
(INT): Likewise.
(REAL): Likewise.
The second source register of insn "*extzvsi-1bit_addsubx" cannot be the
same as the destination register, because that register will be overwritten
with an intermediate value after insn splitting.
/* example #1 */
int test1(int b, int a) {
return ((a & 1024) ? 4 : 0) + b;
}
;; result #1 (incorrect)
test1:
extui a2, a3, 10, 1 ;; overwrites A2 before used
addx4 a2, a2, a2
ret.n
This patch fixes that.
;; result #1 (correct)
test1:
extui a3, a3, 10, 1 ;; uses A3 and then overwrites
addx4 a2, a3, a2
ret.n
However, it should be noted that the first source register can be the same
as the destination without any problems.
/* example #2 */
int test2(int a, int b) {
return ((a & 1024) ? 4 : 0) + b;
}
;; result (correct)
test2:
extui a2, a2, 10, 1 ;; uses A2 and then overwrites
addx4 a2, a2, a3
ret.n
gcc/ChangeLog:
* config/xtensa/xtensa.md (*extzvsi-1bit_addsubx):
Add '&' to the destination register constraint to indicate that
it is 'earlyclobber', append '0' to the first source register
constraint to indicate that it can be the same as the destination
register, and change the split condition from 1 to reload_completed
so that the insn will be split only after RA in order to obtain
allocated registers that satisfy the above constraints.
liuhongt [Thu, 7 Nov 2024 02:15:42 +0000 (18:15 -0800)]
Guard truncate from vector float to vector __bf16 with !flag_rounding_math && HONOR_NANS (BFmode).
hw instruction doesn't raise exceptions, turns sNAN into qNAN quietly,
and always round to nearest (even). Output denormals are always
flushed to zero and input denormals are always treated as zero. MXCSR
is not consulted nor updated.
W/o native instructions, flag_unsafe_math_optimizations is needed for
the permutation instructions.
Similar guard extend from vector __bf16 to vector float with
!HONOR_NANS (BFmode).
gcc/ChangeLog:
* config/i386/i386.md (truncsf2bf2): Add !flag_rounding_math
to the condition, require flag_unsafe_math_optimizations when
native instruction is not available.
* config/i386/mmx.md: (truncv2sfv2bf2): Ditto.
(extendv2bfv2sf2): Add !HONOR_NANS (BFmode) to the condition.
* config/i386/sse.md: (truncv4sfv4sf2): Add
!flag_rounding_math to the condition, require
flag_unsafe_math_optimizations when native instruction is not
available.
(truncv8sfv8bf2): Ditto.
(truncv16sfv16bf2): Ditto.
(extendv4bfv4sf2): Add !HONOR_NANS (BFmode) to the condition.
(extendv8bfv8sf2): Ditto.
(extendv16bfv16sf2): Ditto.
Richard Biener [Fri, 8 Nov 2024 12:25:13 +0000 (13:25 +0100)]
Do not cost the permute node that are part of SLP load-lanes
There are some SVE testsuite fails when forcing SLP because costing
prevents VLA vectors from being used as we add permute cost for
the VEC_PERM nodes that are part of a SLP load-lanes node. The
permutes only exist for representational reasons and pessimize SLP
vs non-SLP so the following makes sure to cost them as zero.
* tree-vect-slp.cc (vectorizable_slp_permutation_1): Return
zero for the permute nodes part of load-lanes.
Avoid these FAILs via 'only_for_offload_target [...]'. Also, for consistency
with other libgomp test cases, use effective-target specifiers of the libgomp
test suite. Fix-up for recent commit d334f729e53867b838e867375b3f475ba793d96e
"openmp: Add testcases for omp_max_vf".
Lewis Hyatt [Sun, 3 Nov 2024 01:59:24 +0000 (21:59 -0400)]
c++: Fix tree_contains_struct for TRAIT_EXPR
CODE_CONTAINS_STRUCT () currently reports that a TRAIT_EXPR contains a
TS_EXP struct, but it does not actually start with a TS_EXP as an initial
sequence. In modules.cc, when we stream out a tree, we explicitly check for the
TS_EXP case and call note_location(t->exp.locus) if so. Currently, this
actually queries the tree_common::chain field of a tree_trait_expr, which
seems not to be used, returning 0, which is interpreted as UNKNOWN_LOCATION
and does no harm.
If location_t will change to be 64 bytes, as is under discussion, then on
32-bit platforms (well those, such as sparc, on which uint64_t has higher
alignment requirement than a pointer), reading t->exp.locus will end up
reading a different field (tree_trait_expr::type1) due to padding
offsets. That field is not generally 0, and the resulting bogus location_t
is sufficiently problematic to cause an ICE in the line_map code. Pretty
much any modules testcase displays the issue, such as partial-2_a.C.
Resolve by initializing tree_contains_struct with the correct value for
TRAIT_EXPR, namely TS_TYPED.
gcc/cp/ChangeLog:
* cp-objcp-common.cc (cp_common_init_ts): Change TRAIT_EXPR from
TS_EXP to TS_TYPED.
Andrew Pinski [Fri, 8 Nov 2024 22:46:18 +0000 (14:46 -0800)]
fold: Remove (rrotate (rrotate A CST) CST) folding [PR117492]
This removes an (broken) simplification from fold which is already handled in match.
The reason why it was broken is because of the use of wi::to_wide on the RHS of the
rotate which could be 2 different types even though the LHS was the same type.
Since it is already handled in match (by the patterns for
`Turn (a OP c1) OP c2 into a OP (c1+c2).`). It can be removed without losing any optimizations.
Bootstrapped and tested on x86_64-linux-gnu.
PR middle-end/117492
gcc/ChangeLog:
* fold-const.cc (fold_binary_loc): Remove `Two consecutive rotates adding up
to the some integer` simplifcation.
gcc/testsuite/ChangeLog:
* gcc.dg/torture/pr117492-1.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Andrew Pinski [Fri, 8 Nov 2024 21:39:05 +0000 (13:39 -0800)]
VN: Don't recurse on for the same value of `a | b` [PR117496]
After adding vn_valueize to the handle the `a | b ==/!= 0` case
of insert_predicates_for_cond, it would go into an infinite loop
as the Value number for either a or b could be the same as what it
is for the whole expression. This avoids that recursion so there is
no infinite loop here.
Bootstrapped and tested on x86_64-linux.
PR tree-optimization/117496
gcc/ChangeLog:
* tree-ssa-sccvn.cc (insert_predicates_for_cond): If the
valueization for the new lhs is the same as the old one,
don't recurse.
gcc/testsuite/ChangeLog:
* gcc.dg/torture/pr117496-1.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Andrew Pinski [Thu, 7 Nov 2024 17:40:15 +0000 (09:40 -0800)]
VN: Canonicalize compares before calling vn_nary_op_lookup_pieces
This is the followup as mentioned in
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/667987.html .
We need to canonicalize the compares using tree_swap_operands_p instead
of checking CONSTANT_CLASS_P.
Bootstrapped and tested on x86_64-linux-gnu.
gcc/ChangeLog:
* tree-ssa-sccvn.cc (visit_phi): Swap the operands
before calling vn_nary_op_lookup_pieces if
tree_swap_operands_p returns true.
(insert_predicates_for_cond): Use tree_swap_operands_p
instead of checking for CONSTANT_CLASS_P.
(process_bb): Swap the comparison and operands
if tree_swap_operands_p returns true.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Jakub Jelinek [Sat, 9 Nov 2024 15:45:44 +0000 (16:45 +0100)]
m2: Fix up dependencies some more
Every now and then my x86_64-linux bootstrap fails due to missing
dependencies somewhere in m2, usually during stage3. I'm using
make -j32 and run 2 bootstraps concurrently (x86_64-linux and i686-linux)
on the same box.
Last night the same happened to me again,
with the first error
In file included from ./tm.h:29,
from ../../gcc/backend.h:28,
from ../../gcc/m2/gm2-gcc/gcc-consolidation.h:27,
from m2/gm2-compiler-boot/M2AsmUtil.c:26:
../../gcc/config/i386/i386.h:2484:10: fatal error: insn-attr-common.h: No such file or directory
2484 | #include "insn-attr-common.h"
| ^~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[3]: *** [../../gcc/m2/Make-lang.in:1576: m2/gm2-compiler-boot/M2AsmUtil.o] Error 1
make[3]: *** Waiting for unfinished jobs....
Now, gcc/Makefile.in has a general rule:
# In order for parallel make to really start compiling the expensive
# objects from $(OBJS) as early as possible, build all their
# prerequisites strictly before all objects.
$(ALL_HOST_OBJS) : | $(generated_files)
which ensures that everything that might depend on the generated files
waits for those to be generated.
The above error clearly shows that such waiting didn't happen for
m2/gm2-compiler-boot/M2AsmUtil.o and some others.
ALL_HOST_OBJS includes $(ALL_HOST_FRONTEND_OBJS),
where the latter is
ALL_HOST_FRONTEND_OBJS = $(foreach v,$(CONFIG_LANGUAGES),$($(v)_OBJS))
m2_OBJS already includes various *.o files, for all those we wait until
the generated files are generated. Though, seems
cc1gm2 depends on m2/stage1/cc1gm2 (which is just copied there),
and that depends on m2/gm2-compiler-boot/m2flex.o,
$(GM2_C_OBJS) and m2/gm2-gcc/rtegraph.o already included in m2_OBJS,
but also on
$(GM2_LIBS_BOOT) $(MC_LIBS)
where
MC_LIBS=m2/mc-boot-ch/Glibc.o m2/mc-boot-ch/Gmcrts.o
GM2_LIBS_BOOT = m2/gm2-compiler-boot/gm2.a \
m2/gm2-libs-boot/libgm2.a \
$(GM2-BOOT-O)
GM2-BOOT-O isn't defined, and the 2 libraries depend on
$(BUILD-LIBS-BOOT) $(BUILD-COMPILER-BOOT)
So, the following patch adds those to m2_OBJS.
I'm not sure if something further is needed, like some objects
used to build the helper programs, mc and whatever else is needed,
I guess it depends on if they use or can use say tm.h or similar
headers which depend on the generated headers.
2024-11-09 Jakub Jelinek <jakub@redhat.com>
gcc/m2/
* Make-lang.in (m2_OBJS): Add $(BUILD-LIBS-BOOT),
$(BUILD-COMPILER-BOOT) and $(MC_LIBS).
arm: Fix ICE on arm_mve.h pragma without MVE types [PR117408]
Starting with r14-435-g00d97bf3b5a, doing `#pragma arm "arm_mve.h"
false` or `#pragma arm "arm_mve.h" true` without first doing
`#pragma arm "arm_mve_types.h"` causes GCC to ICE.
gcc/ChangeLog:
PR target/117408
* config/arm/arm-mve-builtins.cc(handle_arm_mve_h): Detect if MVE
types is missing and if so, return error.
gcc/testsuite/ChangeLog:
PR target/117408
* gcc.target/arm/mve/pr117408-1.c: New test.
* gcc.target/arm/mve/pr117408-2.c: Likewise.
Jakub Jelinek [Sat, 9 Nov 2024 10:42:30 +0000 (11:42 +0100)]
trans-mem: Fix ICE caused by expand_assign_tm
My https://gcc.gnu.org/pipermail/gcc-patches/2024-November/668065.html
patch regressed
+FAIL: g++.dg/tm/pr45940-3.C -std=gnu++11 (internal compiler error: in create_tmp_var, at gimple-expr.cc:484)
+FAIL: g++.dg/tm/pr45940-3.C -std=gnu++11 (test for excess errors)
+FAIL: g++.dg/tm/pr45940-3.C -std=gnu++14 (internal compiler error: in create_tmp_var, at gimple-expr.cc:484)
+FAIL: g++.dg/tm/pr45940-3.C -std=gnu++14 (test for excess errors)
...
+FAIL: g++.dg/tm/pr45940-4.C -std=gnu++26 (internal compiler error: in create_tmp_var, at gimple-expr.cc:484)
+FAIL: g++.dg/tm/pr45940-4.C -std=gnu++26 (test for excess errors)
+FAIL: g++.dg/tm/pr45940-4.C -std=gnu++98 (internal compiler error: in create_tmp_var, at gimple-expr.cc:484)
+FAIL: g++.dg/tm/pr45940-4.C -std=gnu++98 (test for excess errors)
tests, but it turns out it is a preexisting bug.
If I modify the pr45940-3.C testcase
--- gcc/testsuite/g++.dg/tm/pr45940-3.C 2020-01-12 11:54:37.258400660 +0100
+++ gcc/testsuite/g++.dg/tm/pr45940-3.C 2024-11-08 10:35:11.918390743 +0100
@@ -16,6 +16,7 @@ class sp_counted_base
{
protected:
int use_count_; // #shared
+ int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u, v, w, x, y, z, aa, ab, ac, ad, ae, af;
public:
__attribute__((transaction_safe))
virtual void dispose() = 0; // nothrow
then it ICEs already on vanilla trunk.
The problem is that expand_assign_tm just wants to force it into
TM memcpy argument, if is_gimple_reg (reg), then it creates a temporary,
stores the value there and takes temporary address, otherwise it takes
address of rhs. That doesn't work if rhs is an empty CONSTRUCTOR with
C++ non-POD type (TREE_ADDRESSABLE type), we ICE trying to create temporary,
because we shouldn't be creating a temporary.
Now before my patch with the CONSTRUCTOR only having a vtable pointer
(64bit) and 32-bit field, we gimplified the zero initialization just
as storing of 0s to the 2 fields, but as we are supposed to also clear
padding bits, we now gimplify it as MEM[...] = {}; to make sure
even the padding bits are cleared. With the adjusted testcase,
we gimplified it even before as MEM[...] = {}; because it was simply
too large and clearing everything looked beneficial.
The following patch fixes this ICE by using TM memset, it is both
wasteful to force zero constructor into a temporary just to TM memcpy
it into the lhs, and in C++ cases like this invalid.
2024-11-09 Jakub Jelinek <jakub@redhat.com>
* trans-mem.cc (expand_assign_tm): Don't take address
of empty CONSTRUCTOR, instead use BUILT_IN_TM_MEMSET
to clear lhs in that case. Formatting fixes.
Martin Uecker [Fri, 1 Nov 2024 09:15:44 +0000 (10:15 +0100)]
c: minor fixes related to arrays of unspecified size
The patch for PR117145 and PR117245 also fixed PR100420 and PR116284 which
are bugs related to arrays of unspecified size. Those are now represented
as variable size arrays with size (0, 0). There are still some loose ends,
which are resolved here by
1. adding a testcase for PR116284,
2. moving code related to creation and detection of arrays of unspecified
sizes in their own functions,
3. preferring a specified size over an unspecified size when forming
a composite type as required by C99 (PR118391)
4. removing useless code in comptypes_internal and composite_type_internal.
Andi Kleen [Thu, 31 Oct 2024 23:31:02 +0000 (16:31 -0700)]
Update gcc-auto-profile / gen_autofdo_event.py
- Fix warnings with newer python versions about bad escapes by
making all the python string raw.
- Add a fallback for using the builtin perf event list if the
CPU model number is unknown.
- Regenerate the shipped gcc-auto-profile with the changes.
contrib/ChangeLog:
* gen_autofdo_event.py: Convert strings to raw.
Add fallback to using builtin perf event list.
Marek Polacek [Thu, 31 Oct 2024 13:28:15 +0000 (09:28 -0400)]
c: Implement C2y N3356, if declarations [PR117019]
This patch implements C2y N3356, if declarations as described at
<https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3356.htm>.
This feature is cognate with C++17 Selection statements with initializer
<https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2016/p0305r1.html>,
but they are not the same yet. For example, C++17 allows
if (lock (); int i = getval ())
whereas C2y does not.
The proposal adds new grammar productions. selection-header is handled
in c_parser_selection_header which is the gist of the patch.
simple-declaration is handled by c_parser_declaration_or_fndef, which
gets a new parameter.
PR c/117019
gcc/c/ChangeLog:
* c-parser.cc (c_parser_declaration_or_fndef): Adjust declaration.
(c_parser_external_declaration): Adjust a call to
c_parser_declaration_or_fndef.
(c_parser_declaration_or_fndef): New bool parameter. Return a tree
instead of void. Adjust for N3356. Adjust a call to
c_parser_declaration_or_fndef.
(c_parser_compound_statement_nostart): Adjust calls to
c_parser_declaration_or_fndef.
(c_parser_selection_header): New.
(c_parser_paren_selection_header): New.
(c_parser_if_statement): Call c_parser_paren_selection_header
instead of c_parser_paren_condition.
(c_parser_switch_statement): Call c_parser_selection_header instead of
c_parser_expression.
(c_parser_for_statement): Adjust calls to c_parser_declaration_or_fndef.
(c_parser_objc_methodprotolist): Likewise.
(c_parser_oacc_routine): Likewise.
(c_parser_omp_loop_nest): Likewise.
(c_parser_omp_declare_simd): Likewise.
gcc/testsuite/ChangeLog:
* gcc.dg/c23-if-decls-1.c: New test.
* gcc.dg/c23-if-decls-2.c: New test.
* gcc.dg/c2y-if-decls-1.c: New test.
* gcc.dg/c2y-if-decls-2.c: New test.
* gcc.dg/c2y-if-decls-3.c: New test.
* gcc.dg/c2y-if-decls-4.c: New test.
* gcc.dg/c2y-if-decls-5.c: New test.
* gcc.dg/c2y-if-decls-6.c: New test.
* gcc.dg/c2y-if-decls-7.c: New test.
* gcc.dg/c2y-if-decls-8.c: New test.
* gcc.dg/c2y-if-decls-9.c: New test.
* gcc.dg/c2y-if-decls-10.c: New test.
* gcc.dg/c2y-if-decls-11.c: New test.
* gcc.dg/gnu2y-if-decls-1.c: New test.
* gcc.dg/gnu99-if-decls-1.c: New test.
* gcc.dg/gnu99-if-decls-2.c: New test.
hppa: Fix handling of secondary reloads involving a SUBREG
This is fairly subtle.
When handling spills for SUBREG arguments in pa_emit_move_sequence,
alter_subreg may be called. It in turn calls adjust_address_1 and
change_address_1. change_address_1 calls pa_legitimate_address_p
to validate the new spill address. change_address_1 generates an
internal compiler error if the address is not valid. We need to
allow 14-bit displacements for all modes when reload_in_progress
is true and strict is false to prevent the internal compiler error.
SUBREGs are only used with the general registers, so the spill
should result in an integer access. 14-bit displacements are okay
for integer loads and stores but not for floating-point loads and
stores.
Potentially, the change could break the handling of spills for the
floating point-registers but I believe these are handled separately
in pa_emit_move_sequence.
This change fixes the build of symmetrica-3.0.1+ds.
2024-11-08 John David Anglin <danglin@gcc.gnu.org>
gcc/ChangeLog:
PR target/117443
* config/pa/pa.cc (pa_legitimate_address_p): Allow any
14-bit displacement when reload is in progress and strict
is false.
Jakub Jelinek [Fri, 8 Nov 2024 21:07:33 +0000 (22:07 +0100)]
ibstdc++: Add some further attributes to ::operator new in <new>
I've noticed alloc_align attribute is missing on the non-vector
::operator new with std::align_val_t and const std::nothrow_t&
arguments, this patch adds it. The last hunk is just
an attempt to make the line shorter.
The first hunk originally added also __alloc_size__ (1) attribute,
but seems that regresses
FAIL: g++.dg/tm/pr46270.C -std=gnu++98 (test for excess errors)
with
Excess errors:
.../libstdc++-v3/libsupc++/new:137:26: warning: new declaration 'void* operator new(std::size_t)' ambiguates built-in declaration 'void* operator new(long unsigned int)
+transaction_safe' [-Wbuiltin-declaration-mismatch]
.../libstdc++-v3/libsupc++/new:140:26: warning: new declaration 'void* operator new [](std::size_t)' ambiguates built-in declaration 'void* operator new [](long unsigned int)
+transaction_safe' [-Wbuiltin-declaration-mismatch]
I must say I have no clue why that happens only in C++98 (C++11 and
above are quiet) and why only with -fgnu-tm, tried to debug that but
am lost. It is some conflict with the predeclared ::operator new, but
those clearly do have the externally_visible attribute, and alloc_size (1)
attributes:
extvisattr = build_tree_list (get_identifier ("externally_visible"),
NULL_TREE);
newattrs = tree_cons (get_identifier ("alloc_size"),
build_tree_list (NULL_TREE, integer_one_node),
extvisattr);
newtype = cp_build_type_attribute_variant (ptr_ftype_sizetype, newattrs);
newtype = build_exception_variant (newtype, new_eh_spec);
...
tree opnew = push_cp_library_fn (NEW_EXPR, newtype, 0);
DECL_IS_MALLOC (opnew) = 1;
DECL_SET_IS_OPERATOR_NEW (opnew, true);
DECL_IS_REPLACEABLE_OPERATOR (opnew) = 1;
and at C++98 I think libstdc++ doesn't add transaction_safe attribute:
// Conditionally enable annotations for the Transactional Memory TS on C++11.
// Most of the following conditions are due to limitations in the current
// implementation.
#if __cplusplus >= 201103L && _GLIBCXX_USE_CXX11_ABI \
&& _GLIBCXX_USE_DUAL_ABI && __cpp_transactional_memory >= 201500L \
&& !_GLIBCXX_FULLY_DYNAMIC_STRING && _GLIBCXX_USE_WEAK_REF \
&& _GLIBCXX_USE_ALLOCATOR_NEW
#define _GLIBCXX_TXN_SAFE transaction_safe
#define _GLIBCXX_TXN_SAFE_DYN transaction_safe_dynamic
#else
#define _GLIBCXX_TXN_SAFE
#define _GLIBCXX_TXN_SAFE_DYN
#endif
push_cp_library_fn adds transaction_safe attribute whenever -fgnu-tm
is used, regardless of the other conditionals:
if (flag_tm)
apply_tm_attr (fn, get_identifier ("transaction_safe"));
Anyway, omitting alloc_size (1) fixes that test and given that the
predeclared operator new already has alloc_size (1) attribute, I think it
can be safely left out.
2024-11-08 Jakub Jelinek <jakub@redhat.com>
* libsupc++/new (::operator new, ::operator new[]): Add malloc
attribute where missing. Add alloc_align attribute when
std::align_val_t is present and where it was missing. Formatting fix.
Jonathan Wakely [Fri, 8 Nov 2024 13:58:23 +0000 (13:58 +0000)]
libstdc++: Do not define _Insert_base::try_emplace before C++17
This is not a reserved name in C++11 and C++14, so must not be defined.
Also use the appropriate feature test macros for the try_emplace members
of the Debug Mode maps.
libstdc++-v3/ChangeLog:
* include/bits/hashtable_policy.h (_Insert_base::try_emplace):
Do not define for C++11 and C++14.
* include/debug/map.h (try_emplace): Use feature test macro.
* include/debug/unordered_map (try_emplace): Likewise.
* testsuite/17_intro/names.cc: Define try_emplace before C++17.
arm: Improvements to arm_noce_conversion_profitable_p call [PR 116444]
When not dealing with the special armv8.1-m.main conditional instructions case
make sure it uses the default_noce_conversion_profitable_p call to determine
whether the sequence is cost effective.
Also make sure arm_noce_conversion_profitable_p accepts vsel<cond> patterns for
Armv8.1-M Mainline targets.
gcc/ChangeLog:
PR target/116444
* config/arm/arm.cc (arm_noce_conversion_profitable_p): Call
default_noce_conversion_profitable_p when not dealing with the
armv8.1-m.main special case.
(arm_is_vsel_fp_insn): New function.
Jakub Jelinek [Fri, 8 Nov 2024 12:36:05 +0000 (13:36 +0100)]
c++: Fix ICE on constexpr virtual function [PR117317]
Since C++20 virtual methods can be constexpr, and if they are
constexpr evaluated, we choose tentative_decl_linkage for those
defer their output and decide at_eof again.
On the following testcases we ICE though, because if
expand_or_defer_fn_1 decides to use tentative_decl_linkage, it
returns true and the caller in that case cals emit_associated_thunks,
where use_thunk which it calls asserts DECL_INTERFACE_KNOWN on the
thunk destination, which isn't the case for tentative_decl_linkage.
The following patch fixes the ICE by not emitting the thunks
for the DECL_DEFER_OUTPUT fns just yet but waiting until at_eof
time when we return to those.
Note, the second testcase ICEs already since r0-110035 with -std=c++0x
before it gets a chance to diagnose constexpr virtual method.
2024-11-08 Jakub Jelinek <jakub@redhat.com>
PR c++/117317
* semantics.cc (emit_associated_thunks): Do nothing for
!DECL_INTERFACE_KNOWN && DECL_DEFER_OUTPUT fns.
* g++.dg/cpp2a/pr117317-1.C: New test.
* g++.dg/cpp2a/pr117317-2.C: New test.
testsuite: arm: Use effective-target for pr84556.cc test
Using "dg-do run" with a selector overrides the default selector set by
vect.exp that picks between "dg-do run" and "dg-do compile" based on the
target's support for simd operations for Arm targets.
The actual selection of default operation is performed in
check_vect_support_and_set_flags.
gcc/testsuite/ChangeLog:
* g++.dg/vect/pr84556.cc: Change from "dg-do run" with selector
to instead use dg-require-effective-target with the same
selector.
Jonathan Wakely [Fri, 1 Nov 2024 12:38:29 +0000 (12:38 +0000)]
libstdc++: Simplify __detail::__distance_fw using 'if constexpr'
This uses 'if constexpr' instead of tag dispatching, removing the need
for a second call using that tag, and simplifying the overload set that
needs to be resolved for calls to __distance_fw.
libstdc++-v3/ChangeLog:
* include/bits/hashtable_policy.h (__distance_fw): Replace tag
dispatching with 'if constexpr'.
aarch64: Extend support for the AE family of Cortex CPUs
Implement -mcpu options for:
- Cortex-A520AE
- Cortex-A720AE
- Cortex-R82AE
These all implement the same feature sets as their non-AE
counterparts, using the same scheduler and costs and differing only in
their respective part numbers.
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (cortex-a520ae,
cortex-a720ae, cortex-r82ae): Define new entries.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Document A520AE, A720AE and R82AE CPUs.
xuli [Wed, 6 Nov 2024 06:10:09 +0000 (06:10 +0000)]
RISC-V: Add testcases for unsigned imm vec SAT_SUB form1
form1:
void __attribute__((noinline)) \
vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
out[i] = (T)IMM >= in[i] ? (T)IMM - in[i] : 0; \
}
Passed the rv64gcv full regression test.
Signed-off-by: Li Xu <xuli1@eswincomputing.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: add data for vec sat_sub.
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: add unsigned imm vec sat_sub form1.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c: New test.
Jonathan Wakely [Tue, 5 Nov 2024 17:19:06 +0000 (17:19 +0000)]
libstdc++: Fix conversions to key/value types for hash table insertion [PR115285]
The conversions to key_type and value_type that are performed when
inserting into _Hashtable need to be fixed to do any required
conversions explicitly. The current code assumes that conversions from
the parameter to the key_type or value_type can be done implicitly,
which isn't necessarily true.
Remove the _S_forward_key function which doesn't handle all cases and
either forward the parameter if it already has type cv key_type, or
explicitly construct a temporary of type key_type.
Similarly, the _ConvertToValueType specialization for maps doesn't
handle all cases either, for std::pair arguments only some value
categories are handled. Remove _ConvertToValueType and for the _M_insert
function for unique keys, either forward the argument unchanged or
explicitly construct a temporary of type value_type.
For the _M_insert overload for non-unique keys we don't need any
conversion at all, we can just forward the argument directly to where we
construct a node.
libstdc++-v3/ChangeLog:
PR libstdc++/115285
* include/bits/hashtable.h (_Hashtable::_S_forward_key): Remove.
(_Hashtable::_M_insert_unique_aux): Replace _S_forward_key with
a static_cast to a type defined using conditional_t.
(_Hashtable::_M_insert): Replace _ConvertToValueType with a
static_cast to a type defined using conditional_t.
* include/bits/hashtable_policy.h (_ConvertToValueType): Remove.
* testsuite/23_containers/unordered_map/insert/115285.cc: New test.
* testsuite/23_containers/unordered_set/insert/115285.cc: New test.
* testsuite/23_containers/unordered_set/96088.cc: Adjust
expected number of allocations.
aarch64: Make PSEL dependent on SME rather than SME2
The svpsel_lane intrinsics were wrongly classified as SME2+ only,
rather than as base SME intrinsics. They should always be available
in streaming mode.
gcc/
* config/aarch64/aarch64-sve2.md (@aarch64_sve_psel<BHSD_BITS>)
(*aarch64_sve_psel<BHSD_BITS>_plus): Require TARGET_STREAMING
rather than TARGET_STREAMING_SME2.
There are two sets of patterns for FCLAMP: one set for single registers
and one set for multiple registers. The multiple-register set was
correctly gated on SME2, but the single-register set only required SME.
This doesn't matter for ACLE usage, since the intrinsic definitions
are correctly gated. But it does matter for automatic generation of
FCLAMP from separate minimum and maximum operations (either ACLE
intrinsics or autovectorised code).
gcc/
* config/aarch64/aarch64-sve2.md (@aarch64_sve_fclamp<mode>)
(*aarch64_sve_fclamp<mode>_x): Require TARGET_STREAMING_SME2
rather than TARGET_STREAMING_SME.
gcc/testsuite/
* gcc.target/aarch64/sme/clamp_3.c: Force sme2
* gcc.target/aarch64/sme/clamp_4.c: Likewise.
* gcc.target/aarch64/sme/clamp_5.c: New test.
David Faust [Thu, 7 Nov 2024 17:27:07 +0000 (09:27 -0800)]
bpf: avoid possible null deref in btf_ext_output [PR target/117447]
The BPF-specific .BTF.ext section is always generated for BPF programs
if -gbtf is specified, and generating it requires BTF information and
assumes that the BTF info has already been generated.
Compiling non-C languages to BPF is not supported, nor is generating
CTF/BTF for non-C. But, compiling another language like C++ to BPF
with -gbtf specified meant that we would try to generate the .BTF.ext
section anyway, and then ICE because no BTF information was available.
Add a check to bail out of btf_ext_output if the TU CTFC does not exist,
meaning no BTF info is available.
gcc/
PR target/117447
* config/bpf/btfext-out.cc (btf_ext_output): Bail if TU CTFC is null.
Andrew Pinski [Mon, 28 Oct 2024 23:40:34 +0000 (16:40 -0700)]
ifcombine: For short circuit case, allow 2 convert defining statements [PR85605]
r0-126134-g5d2a9da9a7f7c1 added support for circuiting and combing the ifs
into using either AND or OR. But it only allowed the inner condition
basic block having the conditional only. This changes to allow up to 2 defining
statements as long as they are just integer to integer conversions for
either the lhs or rhs of the conditional.
This should allow to use ccmp on aarch64 and x86_64 (APX) slightly more than before.
Boootstrapped and tested on x86_64-linux-gnu.
PR tree-optimization/85605
gcc/ChangeLog:
* tree-ssa-ifcombine.cc (can_combine_bbs_with_short_circuit): New function.
(ifcombine_ifandif): Use can_combine_bbs_with_short_circuit
instead of checking if iterator is one before the last statement.
gcc/testsuite/ChangeLog:
* g++.dg/tree-ssa/ifcombine-ccmp-1.C: New test.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-7.c: New test.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-8.c: New test.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-9.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Andrew Pinski [Sat, 2 Nov 2024 06:20:22 +0000 (23:20 -0700)]
VN: Lookup `val != 0` if we got back val when looking up the predicate for GIMPLE_COND [PR117414]
Sometimes we get back a full ssa name when looking up the comparison of the GIMPLE_COND
rather than a predicate. We then want to lookup the `val != 0` for the predicate.
Note this might happen with other boolean assignments and COND_EXPR but I am not sure
if it is as important; I have not found a testcase yet.
Bootstrapped and tested on x86_64-linux-gnu.
PR tree-optimization/117414
gcc/ChangeLog:
* tree-ssa-sccvn.cc (process_bb): Lookup
`val != 0` if got back a ssa name when looking the comparison.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/fre-predicated-4.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Andrew Pinski [Sat, 2 Nov 2024 06:12:52 +0000 (23:12 -0700)]
VN: Handle `(A CMP B) !=/== 0` for predicates [PR117414]
After the last patch, we also want to record `(A CMP B) != 0`
as `(A CMP B)` and `(A CMP B) == 0` as `(A CMP B)` with the
true/false edges swapped.
This shows up more due to the new handling of
`(A | B) ==/!= 0` in insert_predicates_for_cond
as now we can notice these comparisons which were not seen before.
This is enough to fix the original issue in `gcc.dg/tree-ssa/pr111456-1.c`
and make sure we don't regress it when enhancing ifcombine.
This adds that predicate and allows us to optimize f
in fre-predicated-3.c.
Changes since v1:
* v2: Use vn_valueize.
Bootstrapped and tested on x86_64-linux-gnu.
PR tree-optimization/117414
gcc/ChangeLog:
* tree-ssa-sccvn.cc (insert_predicates_for_cond): Handle `(A CMP B) !=/== 0`.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/fre-predicated-3.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Andrew Pinski [Sat, 2 Nov 2024 03:06:30 +0000 (20:06 -0700)]
VN: Handle `(a | b) !=/== 0` for predicates [PR117414]
For `(a | b) == 0`, we can "assert" on the true edge that
both `a == 0` and `b == 0` but nothing on the false edge.
For `(a | b) != 0`, we can "assert" on the false edge that
both `a == 0` and `b == 0` but nothing on the true edge.
This adds that predicate and allows us to optimize f0, f1,
and f2 in fre-predicated-[12].c.
Changes since v1:
* v2: Use vn_valueize. Also canonicalize the comparison
at the begining of insert_predicates_for_cond for
constants to be on the rhs. Return early for
non-ssa names on the lhs (after canonicalization).
Bootstrapped and tested on x86_64-linux-gnu.
PR tree-optimization/117414
gcc/ChangeLog:
* tree-ssa-sccvn.cc (insert_predicates_for_cond): Canonicalize the comparison.
Don't insert anything if lhs is not a SSA_NAME. Handle `(a | b) !=/== 0`.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/fre-predicated-1.c: New test.
* gcc.dg/tree-ssa/fre-predicated-2.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Andrew Pinski [Sat, 2 Nov 2024 02:28:19 +0000 (19:28 -0700)]
VN: Factor out inserting predicates for conditional
To make it easier to add more predicates in some cases,
factor out the code. Plus it makes the code slightly more
readable since it is not indented as much.
Bootstrapped and tested on x86_64.
gcc/ChangeLog:
* tree-ssa-sccvn.cc (insert_predicates_for_cond): New function, factored out from ...
(process_bb): Here.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
* libgomp.texi (OpenMP Technical Report 13): Remove 'iterator'
in 'map' clause of 'declare mapper' as it is already the list above.
(Interoperability Routines): Add.
(omp_target_memcpy_async, omp_target_memcpy_rect_async):
Document that depobj_list may be omitted in C++ and Fortran.
Paul Iannetta [Wed, 30 Oct 2024 10:21:09 +0000 (11:21 +0100)]
Unify registered_pp_pragmas and registered_pragmas
Until now, the structures that keep pragma information were different
when in preprocessing only mode and in normal mode. This change unifies
both so that the space and name of a pragma are always registered and
can be queried easily at a later time.
gcc/c-family/ChangeLog:
* c-pragma.cc (struct pragma_pp_data): Use (struct internal_pragma_handler);
(c_register_pragma_1): Always register name and space for all pragmas.
(c_invoke_pragma_handler): Adapt.
(c_invoke_early_pragma_handler): Likewise.
(c_pp_invoke_early_pragma_handler): Likewise.
Richard Biener [Tue, 5 Nov 2024 13:58:59 +0000 (14:58 +0100)]
Disable gather/scatter for non-first vectorized epilogue
We currently make vect_check_gather_scatter happy by replacing SSA
name references in DR_REF for gather/scatter DRs but the replacement
process only works once since for the second epilogue we have SSA
names from the first epilogue in DR_REF but as we copied from the
original loop the SSA mapping doesn't work.
The following simply punts for non-first epilogues, those gather/scatter
recognized by patterns to IFNs are already analyzed and should work
fine.
* tree-vect-data-refs.cc (vect_check_gather_scatter): Refuse
to analyze DR_REF if from an epilogue that's not first.
* tree-vect-loop.cc (update_epilogue_loop_vinfo): Add comment
how the substitution in DR_REF is broken.
Richard Biener [Mon, 4 Nov 2024 11:58:41 +0000 (12:58 +0100)]
Add LOOP_VINFO_MAIN_LOOP_INFO
The following introduces LOOP_VINFO_MAIN_LOOP_INFO alongside
LOOP_VINFO_ORIG_LOOP_INFO so one can have both access to the main
vectorized loop info and the preceeding vectorized epilogue.
This is critical for correctness as we need to disallow never
executed epilogues by costing in vect_analyze_loop_costing as
we assume those do not exist when deciding to add a skip-vector
edge during peeling. The patch also changes how multiple vector
epilogues are handled - instead of the epilogue_vinfos array in
the main loop info we now record the single epilogue_vinfo there
and further epilogues in the epilogue_vinfo member of the
epilogue info. This simplifies code.
* tree-vectorizer.h (_loop_vec_info::main_loop_info): New.
(LOOP_VINFO_MAIN_LOOP_INFO): Likewise.
(_loop_vec_info::epilogue_vinfo): Change from epilogue_vinfos
from array to single element.
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Initialize
main_loop_info and epilogue_vinfo. Remove epilogue_vinfos
allocation.
(_loop_vec_info::~_loop_vec_info): Do not release epilogue_vinfos.
(vect_create_loop_vinfo): Rename parameter, set
LOOP_VINFO_MAIN_LOOP_INFO.
(vect_analyze_loop_1): Rename parameter.
(vect_analyze_loop_costing): Properly distinguish between
the main vector loop and the preceeding epilogue.
(vect_analyze_loop): Change for epilogue_vinfos no longer
being a vector.
* tree-vect-loop-manip.cc (vect_do_peeling): Simplify and
thereby handle a vector epilogue of a vector epilogue.
Richard Biener [Mon, 4 Nov 2024 12:09:21 +0000 (13:09 +0100)]
Add LOOP_VINFO_DRS_ADVANCED_BY
The following remembers how we advanced DRs when vectorizing an
epilogue. When we want to vectorize the epilogue of such epilogue
we have to retain that advancement and add the advancement for this
vectorized epilogue. Due to the way we copy and re-associate
stmt_vec_infos and DRs recording this advancement and re-applying
it for the next epilogue is simplest.
* tree-vectorizer.h (_loop_vec_info::drs_advanced_by): New.
(LOOP_VINFO_DRS_ADVANCED_BY): Likewise.
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Initialize
drs_advanced_by.
(update_epilogue_loop_vinfo): Remember the DR advancement made.
(vect_transform_loop): Accumulate past advancements.
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