Patrick Palka [Fri, 5 Feb 2016 14:36:44 +0000 (14:36 +0000)]
Fix PR c++/68948 (wrong code generation due to invalid constructor call)
gcc/cp/ChangeLog:
PR c++/68948
* pt.c (tsubst_baselink): Diagnose an invalid constructor call
if lookup_fnfields returns NULL_TREE and the name being looked
up has the form A::A.
gcc/testsuite/ChangeLog:
PR c++/68948
* g++.dg/template/pr68948.C: New test.
Jeremy Bennett [Fri, 5 Feb 2016 14:27:26 +0000 (14:27 +0000)]
invoke.texi (Optimize Options): In table of --param options rename second occurrence of tracer-min-branch-ratio...
2016-01-05 Jeremy Bennett <jeremy.bennett@embecosm.com>
* doc/invoke.texi (Optimize Options): In table of --param options
rename second occurrence of tracer-min-branch-ratio to
tracer-min-branch-probability, rename
tracer-min-branch-ratio-feedback to
tracer-min-branch-probability-feedback and clarify description,
rename sched-spec-state-edge-prob-cutoff to
sched-state-edge-prob-cutoff, rename selsched-max-insns-to-rename
to selsched-insns-to-rename, rename lto-minpartition to
lto-min-partition, delete reorder-blocks-duplicate and
reorder-blocks-duplicate-feedback.
Dominik Vogt [Fri, 5 Feb 2016 10:25:08 +0000 (10:25 +0000)]
libstdc++: S/390: Add missing baseline_symbols.txt for s390x/-m31.
The attached patch copies the existing
libstdc++-v3/config/abi/post/s390-linux-gnu/baseline_symbols.txt
to .../s390x-linux-gnu/32/baseline_symbols.txt. This fixes the
abi test failure on s390x with -m31.
libstdc++-v3/ChangeLog
* config/abi/post/s390x-linux-gnu/32/baseline_symbols.txt (FUNC):
New file. Copied over from s390-linux-gnu.
Andreas Krebbel [Fri, 5 Feb 2016 10:08:17 +0000 (10:08 +0000)]
S/390: Fix r6 vararg handling.
This patch fixes a problem introduced with the GPR into FPR slot save
feature for leaf functions.
r6 is argument register as well as call-saved. Currently we might
decide that it will be a candidate for being saved into an FPR. If it
turns out later that r6 also needs to be saved due to being required
for vararg we undo the FPR save decision and put it on the stack
again. Unfortunately the code did not adjust the GPR restore range
accordingly so that the register does not get restored in the load
multiple.
This fixes the following testcases on s390x:
< FAIL: libgomp.c/doacross-1.c execution test
< FAIL: libgomp.c/doacross-2.c execution test
< FAIL: libgomp.c/doacross-3.c execution test
< FAIL: libgomp.c++/doacross-1.C execution test
gcc/ChangeLog:
2016-02-05 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
PR target/69625
* config/s390/s390.c (SAVE_SLOT_NONE, SAVE_SLOT_STACK): New
defines.
(s390_register_info_gprtofpr): Use new macros above.
(s390_register_info_stdarg_fpr): Adjust max_fpr to better match
its name.
(s390_register_info_stdarg_gpr): Adjust max_gpr to better match
its name. Adjust restore and save gpr ranges.
(s390_register_info_set_ranges): New function.
(s390_register_info): Use new macros above. Call
s390_register_info_set_ranges.
(s390_optimize_register_info): Likewise.
(s390_hard_regno_rename_ok): Use new macros.
(s390_hard_regno_scratch_ok): Likewise.
(s390_emit_epilogue): Likewise.
(s390_can_use_return_insn): Likewise.
(s390_optimize_prologue): Likewise.
* config/s390/s390.md (GPR2_REGNUM, GPR6_REGNUM): New constants.
combine: distribute_notes again (PR69567, PR64682)
As it happens the patch I did over a year ago for PR64682 isn't quite
correct. This is PR69567. This fixes it.
PR rtl-optimization/64682
PR rtl-optimization/69567
* combine.c (distribute_notes) <REG_DEAD>: Place the death note
before I2 only if the register is both used and set in I2.
Jonathan Wakely [Thu, 4 Feb 2016 21:43:40 +0000 (21:43 +0000)]
Update copyright years in libstdc++ manual and add link
* doc/xml/manual/containers.xml: Add cross-reference to Dual ABI.
* doc/xml/manual/spine.xml: Update copyright years and author blurb.
* doc/html/*: Regenerate.
re PR target/69667 (ppc64le -mlra: ICE: Max. number of generated reload insns per insn is achieved (90))
[gcc]
2016-02-04 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/69667
* config/rs6000/rs6000.md (mov<mode>_64bit_dm): Use 'd' constraint
instead of 'ws', and 'wh' instead of 'wm' since TFmode/IFmode are
not allowed into the traditional Altivec registers.
(movtd_64bit_nodm): Likewise.
(mov<mode>_32bit, FMOVE128_FPR iterator): Likewise.
[gcc/testsuite]
2016-02-04 Michael Meissner <meissner@linux.vnet.ibm.com>
Wilco Dijkstra [Thu, 4 Feb 2016 18:23:35 +0000 (18:23 +0000)]
This patch fixes an exponential issue in ccmp.c.
This patch fixes an exponential issue in ccmp.c. When deciding which ccmp
expansion to use, the tree nodes gs0 and gs1 are fully expanded twice. If
they contain more CCMP opportunities, their subtrees are also expanded twice.
When the trees are complex the expansion takes exponential time and memory.
As a workaround in GCC6 compute the cost of the first expansion early, and
only try the alternative expansion if the cost is low enough. This rarely
affects real code, eg. SPECINT2006 has identical codesize.
Mike Frysinger [Thu, 4 Feb 2016 17:32:11 +0000 (17:32 +0000)]
gcc: invoke: delete -mno-fma4 docs
We don't document the -mno-xxx variants for other flags here, and the
paragraph here specifically says "Each has a corresponding -mno- option
to disable use of these instructions". Drop the -mno-fma4 line.
X gets allocated to an AVX register, as usual for V2TI. The problem is
that the movti for B doesn't then preserve the other half of X, even
though the subreg semantics are supposed to guarantee that.
in which B2 is a no-op and therefore implicit. The handling ought
to be the same regardless of whether there is an rtl insn that
explicitly assigns to (subreg:TI (reg:V2TI X) 16).
This patch implements that idea. Hopefully the comments explain
what's going on.
Tested on x86_64-linux-gnu, aarch64-linux-gnu and arm-linux-gnueabihf.
gcc/
PR rtl-optimization/69577
* reginfo.c (record_subregs_of_mode): Add a partial_def parameter.
(find_subregs_of_mode): Update accordingly. Iterate over partial
definitions.
gcc/testsuite/
PR rtl-optimization/69577
* gcc.target/i386/pr69577.c: New test.
PR target/65932
PR target/67714
* gcc.target/arm/wmul-3.c: Simplify test to generate just
a single smulbb instruction.
* gcc.target/amr/wmul-1.c: Add -mtune=cortex-a9 to dg-options.
* gcc.target/amr/wmul-2.c: Likewise.
Kyrylo Tkachov [Thu, 4 Feb 2016 09:54:37 +0000 (09:54 +0000)]
[ARM][2/4] Fix operand costing logic for SMUL[TB][TB]
PR target/65932
PR target/67714
* config/arm/arm.c (arm_new_rtx_costs, MULT case): Properly extract
the operands of the SIGN_EXTENDs from a SMUL[TB][TB] rtx.
Jakub Jelinek [Thu, 4 Feb 2016 09:02:01 +0000 (10:02 +0100)]
re PR target/69454 (ix86_expand_prologue internal compiler error: Segmentation fault)
PR target/69454
* config/i386/i386.c (convert_scalars_to_vector): Remove
stack alignment fixes.
(ix86_option_override_internal): Disable TARGET_STV if stack
might not be aligned enough.
(ix86_minimum_alignment): Assert that TARGET_STV is false.
* gcc.target/i386/pr69454-1.c: New test.
* gcc.target/i386/pr69454-2.c: New test.
Martin Sebor [Thu, 4 Feb 2016 04:50:42 +0000 (21:50 -0700)]
PR c++/69251 - [6 Regression] ICE in unify_array_domain on a flexible array
PR c++/69251 - [6 Regression] ICE in unify_array_domain on a flexible array
member
PR c++/69253 - [6 Regression] ICE in cxx_incomplete_type_diagnostic initializing
a flexible array member with empty string
PR c++/69290 - [6 Regression] ICE on invalid initialization of a flexible array
member
PR c++/69277 - [6 Regression] ICE mangling a flexible array member
PR c++/69349 - template substitution error for flexible array members
gcc/testsuite/ChangeLog:
2016-02-03 Martin Sebor <msebor@redhat.com>
PR c++/69251
PR c++/69253
PR c++/69290
PR c++/69277
PR c++/69349
* g++.dg/ext/flexarray-mangle-2.C: New test.
* g++.dg/ext/flexarray-mangle.C: New test.
* g++.dg/ext/flexarray-subst.C: New test.
* g++.dg/ext/flexary11.C: New test.
* g++.dg/ext/flexary12.C: New test.
* g++.dg/ext/flexary13.C: New test.
* g++.dg/ext/flexary14.C: New test.
* g++.dg/other/dump-ada-spec-2.C: Adjust.
Jakub Jelinek [Wed, 3 Feb 2016 22:38:56 +0000 (23:38 +0100)]
re PR target/69644 (ICE with -O on __sync_bool_compare_and_swap with short in extract_insn, at recog.c:2286)
PR target/69644
* config/rs6000/rs6000.c (rs6000_expand_atomic_compare_and_swap):
Force oldval into register if it does not satisfy reg_or_short_operand
predicate. Fix up formatting.
Patrick Palka [Wed, 3 Feb 2016 20:14:43 +0000 (20:14 +0000)]
Fix PR c++/69056 (argument pack deduction failure during overload resolution)
gcc/cp/ChangeLog:
PR c++/69056
* pt.c (try_one_overload): Handle comparing argument packs so
that there is no conflict if we deduced more arguments of an
argument pack than were explicitly specified.
re PR target/69461 (ICE in lra_set_insn_recog_data, at lra.c:964)
2016-02-03 Vladimir Makarov <vmakarov@redhat.com>
Alexandre Oliva <aoliva@redhat.com>
PR target/69461
* lra-constraints.c (simplify_operand_subreg): Check additionally
address validity after potential reloading.
(process_address_1): Check insns validity. In case of failure do
nothing.
2016-02-03 Vladimir Makarov <vmakarov@redhat.com>
Alexandre Oliva <aoliva@redhat.com>
Uros Bizjak [Wed, 3 Feb 2016 17:01:01 +0000 (18:01 +0100)]
tsan-dg.exp (tsan_init): Move check if tsan executable works from here ...
* lib/tsan-dg.exp (tsan_init): Move check if tsan executable
works from here ...
(check_effective_target_fsanitize_thread): ... to here. Do not
specify additional compile flags for the test source.
* lib/asan-dg.exp (check_effective_target_fsanitize_address): Do not
specify additional compile flags for the test source.
Wilco Dijkstra [Wed, 3 Feb 2016 12:18:19 +0000 (12:18 +0000)]
Fix the ccmp_1.c test back to use '0' as regular expressions don't work correctly.
Fix the ccmp_1.c test back to use '0' as regular expressions don't work
correctly. '0' is right due to compare with zero now printing as
'CMP w0, 0' rather than 'CMP w0, wzr'.
2016-02-03 Wilco Dijkstra <wdijkstr@arm.com>
gcc/testsuite/
* gcc.target/aarch64/ccmp_1.c: Fix test issue.
re PR fortran/67451 ([F08] ICE with sourced allocation from coarray.)
gcc/testsuite/ChangeLog:
2016-02-03 Andre Vehreschild <vehre@gcc.gnu.org>
PR fortran/67451
PR fortran/69418
* gfortran.dg/coarray_allocate_2.f08: New test.
* gfortran.dg/coarray_allocate_3.f08: New test.
* gfortran.dg/coarray_allocate_4.f08: New test.
gcc/fortran/ChangeLog:
2016-02-03 Andre Vehreschild <vehre@gcc.gnu.org>
PR fortran/67451
PR fortran/69418
* trans-expr.c (gfc_copy_class_to_class): For coarrays just the
pointer is passed. Take it as is without trying to deref the
_data component.
* trans-stmt.c (gfc_trans_allocate): Take care of coarrays as
argument to source=-expression.
Excess errors:
/home/segher/src/gcc/gcc/testsuite/c-c++-common/vector-compare-4.c:31:1: warning: GCC vector returned by reference: non-standard ABI extension with no compatibility guarantee
Fix this as in vector-compare-2.c .
testsuite/
* c-c++-common/vector-compare-4.c: Prune "non-standard ABI extension"
warning.
Improve TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS target hook. It turns out there
is another case where the register allocator uses the union of register classes
without checking that the cost of the resulting register class is lower than
both (see https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01765.html ). This
happens when the cost of the best and alternative class are both lower than the
memory cost. In this case we typically end up with ALL_REGS as the allocno
class, which almost invariably results in bad allocations with many redundant
int<->FP moves (which are expensive on various cores). AArch64 is affected by
this significantly due to supporting many scalar integer operations in SIMD.
Currently the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook forces the class to
GENERAL_REGS if the allocno class is ALL_REGS and the register has an integer
mode. This is bad if the best class happens to be FP_REGS. To handle this
case as well, an extra argument is needed in the hook to pass the best class.
If the allocno class is ALL_REGS, but the best class isn't, we use the best
class instead (rather than using the mode to force to GENERAL_REGS or FP_REGS).
Previously this might happen:
r79: preferred FP_REGS, alternative GENERAL_REGS, allocno GENERAL_REGS
a1 (r79,l0) best GENERAL_REGS, allocno GENERAL_REGS
The proposed allocno is ALL_REGS (despite having the highest cost!) and is then
forced by the hook to GENERAL_REGS because r79 has integer mode. However
FP_REGS has the lowest cost. After this patch the choice is as follows:
r79: preferred FP_REGS, alternative GENERAL_REGS, allocno FP_REGS
a1 (r79,l0) best FP_REGS, allocno FP_REGS
As a result it is now no longer a requirement to use register move costs that
are larger than the memory move cost. So it will be feasible to use realistic
costs for both without a huge penalty.
2016-02-02 Wilco Dijkstra <wdijkstr@arm.com>
gcc/
* ira-costs.c (find_costs_and_classes): Add extra argument.
* target.def (ira_change_pseudo_allocno_class): Add parameter.
* targhooks.h (ira_change_pseudo_allocno_class): Likewise.
* targhooks.c (ira_change_pseudo_allocno_class): Likewise.
* config/aarch64/aarch64.c (aarch64_ira_change_pseudo_allocno_class)
Add best_class parameter, and return it if not ALL_REGS.
* config/mips/mips.c (mips_ira_change_pseudo_allocno_class):
Add parameter.
* doc/tm.texi (TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS):
Update target hook.
Wilco Dijkstra [Tue, 2 Feb 2016 17:03:05 +0000 (17:03 +0000)]
This patch adds support for the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook.
When the cost of GENERAL_REGS and FP_REGS is identical, the register allocator
always uses ALL_REGS even when it has a much higher cost. The hook changes the
class to either FP_REGS or GENERAL_REGS depending on the mode of the register.
This results in better register allocation overall, fewer spills and reduced
codesize - particularly in SPEC2006 gamess.
2016-02-02 Wilco Dijkstra <wdijkstr@arm.com>
gcc/
* config/aarch64/aarch64.c
(TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): New define.
(aarch64_ira_change_pseudo_allocno_class): New function.
gcc/testsuite/
* gcc.target/aarch64/scalar_shift_1.c
(test_corners_sisd_di): Improve force to SIMD register.
(test_corners_sisd_si): Likewise.
* gcc.target/aarch64/vect-ld1r-compile-fp.c:
Remove scan-assembler check for ldr.
Yuri Rumyantsev [Tue, 2 Feb 2016 09:46:26 +0000 (09:46 +0000)]
re PR middle-end/68542 (10% 481.wrf performance regression)
gcc/
2016-02-02 Yuri Rumyantsev <ysrumyan@gmail.com>
PR middle-end/68542
* config/i386/i386.c (ix86_expand_branch): Add support for conditional
branch with vector comparison.
* config/i386/sse.md (VI48_AVX): New mode iterator.
(define_expand "cbranch<mode>4): Add support for conditional branch
with vector comparison.
* tree-vect-loop.c (optimize_mask_stores): New function.
* tree-vect-stmts.c (vectorizable_mask_load_store): Initialize
has_mask_store field of vect_info.
* tree-vectorizer.c (vectorize_loops): Invoke optimaze_mask_stores for
vectorized loops having masked stores after vec_info destroy.
* tree-vectorizer.h (loop_vec_info): Add new has_mask_store field and
correspondent macros.
(optimize_mask_stores): Add prototype.
gcc/testsuite
2016-02-02 Yuri Rumyantsev <ysrumyan@gmail.com>
PR middle-end/68542
* gcc.dg/vect/vect-mask-store-move-1.c: New test.
* gcc.target/i386/avx2-vect-mask-store-move1.c: New test.
Alan Modra [Tue, 2 Feb 2016 00:01:16 +0000 (10:31 +1030)]
[RS6000] ABI_V4 init of toc section
Since 4c4a180d lto has turned off flag_pic when linking a fixed
position executable. So flag_pic is zero in rs6000_file_start.
However, when we get to actually emitting code, flag_pic may be on
again. This results in undefined references to ".LCTOC1".
PR target/68662
* config/rs6000/rs6000.c (need_toc_init): New var, set it
whenever toc_label_name used.
(rs6000_file_start): Don't set up toc section here,
(rs6000_output_function_epilogue): do so here instead,
(rs6000_xcoff_file_start): and here.
* config/rs6000/rs6000.md (load_toc_aix_si): Set need_toc_init.
(load_toc_aix_di): Likewise.
Jakub Jelinek [Mon, 1 Feb 2016 22:39:31 +0000 (23:39 +0100)]
re PR rtl-optimization/69592 (Compile-time and memory-use hog in combine)
PR rtl-optimization/69592
* rtlanal.c (nonzero_bits_binary_arith_p): New inline function.
(cached_nonzero_bits): Use it instead of ARITHMETIC_P.
(num_sign_bit_copies_binary_arith_p): New inline function.
(cached_num_sign_bit_copies): Use it instead of ARITHMETIC_P.
Jeff Law [Mon, 1 Feb 2016 22:03:57 +0000 (15:03 -0700)]
re PR testsuite/68580 (FAIL: c-c++-common/tsan/pr65400-1.c -O0 execution test)
PR tree-optimization/68580
* params.def (FSM_MAXIMUM_PHI_ARGUMENTS): New param.
* tree-ssa-threadbackward.c
(fsm_find_control_statement_thread_paths): Do not try to walk
through large PHI nodes.
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