Jason Merrill [Fri, 13 May 2016 19:18:35 +0000 (15:18 -0400)]
Fix type-dependence and the current instantiation.
PR c++/10200
PR c++/69753
* pt.c (tsubst_decl): Use uses_template_parms.
(instantiate_template_1): Handle non-dependent calls in templates.
(value_dependent_expression_p): Handle BASELINK, FUNCTION_DECL.
(type_dependent_expression_p): Only consider innermost template args.
(dependent_template_arg_p): Check enclosing class of a template here.
(dependent_template_p): Not here.
(type_dependent_object_expression_p): New.
* typeck.c (finish_class_member_access_expr): Use it.
* parser.c (cp_parser_postfix_expression): Use it.
(cp_parser_postfix_dot_deref_expression): Use it. Use comptypes
to detect the current instantiation.
(cp_parser_lookup_name): Really implement DR 141.
* search.c (lookup_field_r): Prefer a dependent using-declaration.
(any_dependent_bases_p): Split out from...
* name-lookup.c (do_class_using_decl): ...here.
* call.c (build_new_method_call_1): Use it.
* semantics.c (finish_call_expr): 'this' doesn't make a call dependent.
* tree.c (non_static_member_function_p): Remove.
* typeck2.c (build_x_arrow): Use dependent_scope_p.
Ilya Enkovich [Fri, 13 May 2016 09:55:58 +0000 (09:55 +0000)]
cse.c (rest_of_handle_cse): Use cleanup_cfg returned value cse_cfg_altered computation.
gcc/
* cse.c (rest_of_handle_cse): Use cleanup_cfg
returned value cse_cfg_altered computation.
(rest_of_handle_cse2): Likewise.
(rest_of_handle_cse_after_global_opts): Likewise.
The reason this caught my eye on aarch64 is because
the return value register (x0) is not identical to the register in which
the hidden parameter for AArch64 is set (x8). Thus setting this to true
seems to be quite reasonable and shaves off 100 odd mov x0, x8's from
cc1 in a bootstrap build.
I don't expect this to make a huge impact on performance but as they
say every little counts. The AAPCS64 is quite explicit about not
requiring that the contents of x8 be kept live.
Bootstrapped and regression tested on aarch64.
Ok to apply ?
Ramana
gcc/
* config/aarch64/aarch64.c (TARGET_OMIT_STRUCT_RETURN_REG): Set to
true.
Uros Bizjak [Thu, 12 May 2016 18:34:54 +0000 (20:34 +0200)]
i386.md (*call_got_x32): Change operand 0 to DImode before it is passed to ix86_output_call_operand.
* config/i386/i386.md (*call_got_x32): Change operand 0 to
DImode before it is passed to ix86_output_call_operand.
(*call_value_got_x32): Ditto for operand 1.
Marek Polacek [Thu, 12 May 2016 15:28:08 +0000 (15:28 +0000)]
re PR c/70756 (Wrong column number shown for "error: invalid use of flexible array member")
PR c/70756
* c-common.c (pointer_int_sum): Call size_in_bytes_loc instead of
size_in_bytes and pass LOC to it.
* c-decl.c (build_compound_literal): Pass LOC down to
c_incomplete_type_error.
* c-tree.h (require_complete_type): Adjust declaration.
(c_incomplete_type_error): Likewise.
* c-typeck.c (require_complete_type): Add location parameter, pass it
down to c_incomplete_type_error.
(c_incomplete_type_error): Add location parameter, pass it down to
error_at.
(build_component_ref): Pass location down to c_incomplete_type_error.
(default_conversion): Pass location down to require_complete_type.
(build_array_ref): Likewise.
(build_function_call_vec): Likewise.
(convert_arguments): Likewise.
(build_unary_op): Likewise.
(build_c_cast): Likewise.
(build_modify_expr): Likewise.
(convert_for_assignment): Likewise.
(c_finish_omp_clauses): Likewise.
* call.c (build_new_op_1): Pass LOC to cp_build_modify_expr.
* cp-tree.h (cp_build_modify_expr): Update declaration.
(cxx_incomplete_type_error, cxx_incomplete_type_diagnostic): New inline
overloads.
* cp-ubsan.c (cp_ubsan_dfs_initialize_vtbl_ptrs): Pass INPUT_LOCATION to
cp_build_modify_expr.
* decl2.c (set_guard): Likewise.
(handle_tls_init): Likewise.
* init.c (perform_member_init): Likewise.
(expand_virtual_init): Likewise.
(build_new_1): Likewise.
(build_vec_delete_1): Likewise.
(get_temp_regvar): Likewise.
(build_vec_init): Likewise.
* method.c (do_build_copy_assign): Likewise.
(assignable_expr): Likewise.
* semantics.c (finish_omp_for): Likewise.
* typeck.c (cp_build_binary_op): Pass LOCATION to pointer_diff and
cp_pointer_int_sum.
(cp_pointer_int_sum): Add location parameter. Pass it down to
pointer_int_sum.
(pointer_diff): Add location parameter. Use it.
(build_modify_expr): Pass location down to cp_build_modify_expr.
(cp_build_modify_expr): Add location parameter. Use it.
(build_x_modify_expr): Pass location down to cp_build_modify_expr.
* typeck2.c (cxx_incomplete_type_diagnostic,
cxx_incomplete_type_error): Add location parameter.
* langhooks-def.h (lhd_incomplete_type_error): Adjust declaration.
* langhooks.c (lhd_incomplete_type_error): Add location parameter.
* langhooks.h (incomplete_type_error): Likewise.
* tree.c (size_in_bytes_loc): Renamed from size_in_bytes. Add location
parameter, pass it down to incomplete_type_error.
* tree.h (size_in_bytes): New inline overload.
(size_in_bytes_loc): Renamed from size_in_bytes.
* c-c++-common/pr70756-2.c: New test.
* c-c++-common/pr70756.c: New test.
Richard Biener [Thu, 12 May 2016 13:46:26 +0000 (13:46 +0000)]
re PR tree-optimization/71059 (gcc ICE at -O3 on valid code on x86_64-linux-gnu in "vn_nary_op_insert_into")
2016-05-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/71059
* tree-ssa-pre.c (phi_translate_1): Fully fold translated
nary before looking up or entering the expression into the VN
hashes.
* tree-ssa-sccvn.c (vn_nary_build_or_lookup): Fix comment typo.
Make sure to re-use NARYs without result as inserted by
phi-translation.
Richard Biener [Thu, 12 May 2016 13:05:13 +0000 (13:05 +0000)]
re PR middle-end/71062 (r235622 and restrict pointers)
2016-05-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/71062
* tree-ssa-alias.h (struct pt_solution): Add vars_contains_restrict
field.
* tree-ssa-structalias.c (set_uids_in_ptset): Set vars_contains_restrict
if the var is a restrict tag.
* tree-ssa-alias.c (ptrs_compare_unequal): If vars_contains_restrict
do not disambiguate pointers against it.
(dump_points_to_solution): Re-structure and adjust for new
vars_contains_restrict flag.
* gimple-pretty-print.c (pp_points_to_solution): Likewise.
Kyrylo Tkachov [Thu, 12 May 2016 09:56:46 +0000 (09:56 +0000)]
[ARM] PR target/70830: Avoid POP-{reglist}^ when returning from interrupt handlers
PR target/70830
* config/arm/arm.c (arm_output_multireg_pop): Avoid POP instruction
when popping the PC and within an interrupt handler routine.
Add missing tab to output of "ldmfd".
(output_return_instruction): Output LDMFD with SP update rather
than POP when returning from interrupt handler.
* gcc.target/arm/interrupt-1.c: Change dg-compile to dg-assemble.
Add -save-temps to dg-options.
Scan for ldmfd rather than pop instruction.
* gcc.target/arm/interrupt-2.c: Likewise.
* gcc.target/arm/pr70830.c: New test.
Jakub Jelinek [Thu, 12 May 2016 08:35:20 +0000 (10:35 +0200)]
i386.md (isa): Add x64_avx512dq, enable if TARGET_64BIT && TARGET_AVX512DQ.
* config/i386/i386.md (isa): Add x64_avx512dq, enable if
TARGET_64BIT && TARGET_AVX512DQ.
* config/i386/sse.md (*vec_extract<mode>): Add avx512bw alternatives.
(*vec_extract<PEXTR_MODE12:mode>_zext): Add avx512bw alternative.
(*vec_extract<ssevecmodelower>_0, *vec_extractv4si_0_zext,
*vec_extractv2di_0_sse): Use v constraint instead of x constraint.
(*vec_extractv4si): Add avx512dq and avx512bw alternatives.
(*vec_extractv4si_zext): Add avx512dq alternative.
(*vec_extractv2di_1): Add x64_avx512dq and avx512bw alternatives,
use v instead of x constraint in other alternatives where possible.
* gcc.target/i386/avx512bw-vpextr-1.c: New test.
* gcc.target/i386/avx512dq-vpextr-1.c: New test.
Jakub Jelinek [Thu, 12 May 2016 08:34:11 +0000 (10:34 +0200)]
sse.md (pinsr_evex_isa): New mode attr.
* config/i386/sse.md (pinsr_evex_isa): New mode attr.
(<sse2p4_1>_pinsr<ssemodesuffix>): Add 2 alternatives with
v constraints instead of x and <pinsr_evex_isa> isa attribute.
* gcc.target/i386/avx512bw-vpinsr-1.c: New test.
* gcc.target/i386/avx512dq-vpinsr-1.c: New test.
* gcc.target/i386/avx512vl-vpinsr-1.c: New test.
Jakub Jelinek [Thu, 12 May 2016 08:33:14 +0000 (10:33 +0200)]
re PR target/71019 (AVX512BW instructions emitted even without AVX512BW)
PR target/71019
* config/i386/sse.md (<sse2_avx2>_packssdw<mask_name>,
<sse4_1_avx2>_packusdw<mask_name>): Make sure EVEX encoded insn
is not emitted unless TARGET_AVX512BW.
(<sse2_avx2>_packuswb<mask_name>, <sse2_avx2>_packsswb<mask_name>):
Likewise. For TARGET_AVX512BW, use "=v" constraint instead of "=x"
for the result operand.
* gcc.target/i386/avx512vl-pack-1.c: New test.
* gcc.target/i386/avx512vl-pack-2.c: New test.
* gcc.target/i386/avx512bw-pack-2.c: New test.
Jakub Jelinek [Thu, 12 May 2016 08:30:25 +0000 (10:30 +0200)]
constraints.md (Yv): New constraint.
* config/i386/constraints.md (Yv): New constraint.
* config/i386/i386.h (VALID_AVX512VL_128_REG_MODE): Allow
TFmode and V1TImode in xmm16+ registers for TARGET_AVX512VL.
* config/i386/i386.md (avx512fvecmode): New mode attr.
(*pushtf): Use v constraint instead of x.
(*movtf_internal): Likewise. For TARGET_AVX512VL and
xmm16+ registers, use vmovdqu64 or vmovdqa64 instructions.
(*absneg<mode>2): Use Yv constraint instead of x constraint.
(*absnegtf2_sse): Likewise.
(copysign<mode>3_const, copysign<mode>3_var): Likewise.
* config/i386/sse.md (*andnot<mode>3): Add avx512vl and
avx512f alternatives.
(*andnottf3, *<code><mode>3, *<code>tf3): Likewise.
* gcc.target/i386/avx512dq-abs-copysign-1.c: New test.
* gcc.target/i386/avx512vl-abs-copysign-1.c: New test.
* gcc.target/i386/avx512vl-abs-copysign-2.c: New test.
Richard Biener [Thu, 12 May 2016 07:29:33 +0000 (07:29 +0000)]
re PR tree-optimization/71060 (Compiler reports "loop vectorized" but actually it was not)
2016-05-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/71060
* tree-data-ref.c (initialize_data_dependence_relation): Do not
require exact match of DR_BASE_OBJECT but only matching address and
type.
Michael Meissner [Wed, 11 May 2016 18:38:10 +0000 (18:38 +0000)]
predicates.md (quad_memory_operand): Move most of the code into quad_address_p and call it to share code with...
[gcc]
2016-05-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (quad_memory_operand): Move most of
the code into quad_address_p and call it to share code with
vsx_quad_dform_memory_operand.
(vsx_quad_dform_memory_operand): New predicate for ISA 3.0 vector
d-form support.
* config/rs6000/rs6000.opt (-mlra): Switch to being an option mask
bit instead of being a separate word. Split -mpower9-dform into
two switches, -mpower9-dform-scalar and -mpower9-dform-vector.
* config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): New addr_mask
for the register class supporting 128-bit quad word memory
offsets.
(mode_supports_vsx_dform_quad): Helper function to return if the
register class uses quad word memory offsets.
(rs6000_debug_addr_mask): Add support for quad word memory
offsets.
(rs6000_debug_reg_global): Always print if we are using LRA or
not.
(rs6000_setup_reg_addr_masks): If ISA 3.0 vector d-form
instructions are enabled, set up the appropriate addr_masks for
128-bit types.
(rs6000_init_hard_regno_mode_ok): wb constraint is now based on
-mpower9-dform-scalar, instead of -mpower9-dform.
(rs6000_option_override_internal): Split -mpower9-dform into two
switches, -mpower9-dform-scalar and -mpower9-dform-vector. The
-mpower9-dform switch sets or clears both. If we are not using
the LRA register allocator, do not enable -mpower9-dform-vector by
default. If we are using LRA, enable -mpower9-dform-vector and
-mvsx-timode if it is appropriate. Issue a warning if either
-mpower9-dform-vector or -mvsx-timode are explicitly used without
enabling LRA.
(quad_address_offset_p): New helper function to return if the
offset is legal for quad word memory instructions.
(quad_address_p): New function to determin if GPR or vector
register quad word memory addresses are legal.
(mem_operand_gpr): Validate quad word address offsets.
(reg_offset_addressing_ok_p): Add support for ISA 3.0 vector
d-form (register + offset) instructions.
(offsettable_ok_by_alignment): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(legitimate_lo_sum_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Add more debug statements for
-mdebug=addr.
(rs6000_legitimate_address_p): Add support for ISA 3.0 vector
d-form instructions.
(rs6000_secondary_reload_memory): Add support for ISA 3.0 vector
d-form instructions. Distinguish different cases in debug
output. (rs6000_secondary_reload_inner): Add support for ISA 3.0 vector
d-form instructions.
(rs6000_preferred_reload_class): Likewise.
(rs6000_output_move_128bit): Add support for ISA 3.0 d-form
instructions. If ISA 3.0 is available, generate lxvx/stxvx instead
of the ISA 2.06 indexed memory instructions.
(rs6000_emit_prologue): If we have ISA 3.0 d-form instructions,
use them to save/restore the saved vector registers instead of
using Altivec instructions.
(rs6000_emit_epilogue): Likewise.
(rs6000_lra_p): Use TARGET_LRA instead of the old option word.
(rs6000_opt_masks): Split -mpower9-dform into
-mpower9-dform-scalar and -mpower9-dform-vector.
(rs6000_print_options_internal): Print -mno-<switch> if <switch>
was not selected.
* config/rs6000/vsx.md (p9_vecload_<mode>): Delete hack to emit
ISA 3.0 vector indexed memory instructions, and fold the code into
the normal mov<mode> patterns.
(p9_vecstore_<mode>): Likewise.
(vsx_mov<mode>): Add support for ISA 3.0 vector d-form
instructions.
(vsx_movti_64bit): Likewise.
(vsx_movti_32bit): Likewise.
* config/rs6000/constraints.md (wO constraint): New constraint for
ISA 3.0 vector d-form support.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Use
-mpower9-dform-scalar instead of -mpower9-dform. Add note not to
include -mpower9-dform-vector until we switch over to LRA.
(POWERPC_MASKS): Add -mlra. Split -mpower9-dform into two.
switches, -mpower9-dform-scalar and -mpower9-dform-vector.
* config/rs6000/rs6000-protos.h (quad_address_p): Add declaration.
* doc/invoke.texi (RS/6000 and PowerPC Options): Add documentation
for -mpower9-dform and -mlra.
* doc/md.texi (wO constraint): Document wO constraint.
[gcc/testsuite]
2016-05-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/dform-3.c: New test for ISA 3.0 vector d-form
support.
* gcc.target/powerpc/dform-1.c: Add -mlra option to silence
warning when using -mvsx-timode.
* gcc.target/powerpc/p8vector-int128-1.c: Likewise.
* gcc.target/powerpc/dform-2.c: Likewise.
* gcc.target/powerpc/pr68805.c: Likewise.
Richard Biener [Wed, 11 May 2016 14:04:32 +0000 (14:04 +0000)]
re PR tree-optimization/71055 (FAIL: gcc.dg/torture/pr53663-1.c -Os execution test)
2016-05-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/71055
* tree-ssa-sccvn.c (vn_reference_lookup_3): When native-interpreting
sth with precision not equal to access size verify we don't chop
off bits.
Richard Biener [Wed, 11 May 2016 10:24:11 +0000 (10:24 +0000)]
re PR middle-end/71002 (-fstrict-aliasing breaks Boost's short string optimization implementation)
2016-05-11 Richard Biener <rguenther@suse.de>
PR middle-end/71002
* alias.c (reference_alias_ptr_type): Preserve alias-set zero
if the langhook insists on it.
* fold-const.c (make_bit_field_ref): Add arg for the original
reference and preserve its alias-set.
(decode_field_reference): Take exp by reference and adjust it
to the original memory reference.
(optimize_bit_field_compare): Adjust callers.
(fold_truth_andor_1): Likewise.
* gimplify.c (gimplify_expr): Adjust in-SSA form test.
Alan Modra [Wed, 11 May 2016 02:09:38 +0000 (11:39 +0930)]
[RS6000] complex long double ABI_V4 fix
Revision 235794 regressed compat/scalar-by-value-6 for powerpc-linux
-m32 due to accidentally changing the ABI. By another historical
accident, complex long double is stupidly passed in gprs for -m32.
* config/rs6000/rs6000.c (is_complex_IBM_long_double,
abi_v4_pass_in_fpr): New functions.
(rs6000_function_arg_boundary): Exclude complex IBM long double
from 64-bit alignment when ABI_V4.
(rs6000_function_arg, rs6000_function_arg_advance_1,
rs6000_gimplify_va_arg): Use abi_v4_pass_in_fpr.
cfgcleanup: Handle a branch with just a return in both arms (PR71028)
If we have a conditional jump that has only a return in both the branch
path and the fallthrough path, and the return on the branch path can not
be made a conditional return, we will try to make a conditional return
from the fallthrough path, and that does not work because we then try
to redirect the (new) jump in the fallthrough block to the original
dest in the branch path, which is the exit block.
For the testcase on ARM we end up in this situation because before the
jump2 pass there are some other insns in the return blocks as well, but
the same insns in both, so those are moved above the conditional jump.
Only later (in the ce3 pass) are the conditional jump and two returns
melded into one return, so we need to handle this strange case here.
PR rtl-optimization/71028
* cfgcleanup.c (try_optimize_cfg): Do not flip a conditional
jump with just a return in the fallthrough block if the branch
block contains just a returns as well.
James Norris [Tue, 10 May 2016 18:05:02 +0000 (18:05 +0000)]
sysv4.h (CRTOFFLOADBEGIN): Define.
* config/rs6000/sysv4.h (CRTOFFLOADBEGIN): Define. Add crtoffloadbegin.o
if offloading is enabled and -fopenacc or -fopenmp is specified.
(CRTOFFLOADEND): Likewise.
(STARTFILE_LINUX_SPEC): Add CRTOFFLOADBEGIN.
(ENDFILE_LINUX_SPEC): Add CRTOFFLOADEND.
Uros Bizjak [Tue, 10 May 2016 17:17:20 +0000 (19:17 +0200)]
i386.c (legitimize_pic_address): Merge 64-bit and 32-bit gotoff_operand code paths.
* config/i386/i386.c (legitimize_pic_address): Merge 64-bit and 32-bit
gotoff_operand code paths. Use copy_to_suggested_regs and
expand_simple_binop where appropriate. Cleanup.
When the DWARF back-end generates DW_OP_neg operations in DWARF
procedures, we get an ICE because of inconsistent stack usage
computation for the embedding expression. This is because
resolve_args_picking_1 thinks DW_OP_neg is a binary operation (pops 2
stack slots, pushes 1) whereas it really is an unary one (one pop, one
push).
This change fixes resolve_args_picking_1 and adds a regression testcase
(which crashes with the current trunk). Bootstrapped and regtested
without regression on x86_64-linux.
gcc/
* dwarf2out.c (resolve_args_picking_1): Consider DW_OP_neg as an
unary operation, not a binary one.
gcc/testsuite/
* gnat.dg/debug6.adb, gnat.dg/debug6_pkg.ads: New testcase.
Ilya Enkovich [Tue, 10 May 2016 15:56:27 +0000 (15:56 +0000)]
re PR tree-optimization/70876 (ICE in chkp_find_bounds: Unexpected tree code with_size_expr)
gcc/
PR tree-optimization/70786
* tree-chkp.c (chkp_find_bounds_1): Support WITH_SIZE_EXPR.
* gcc/calls.c (initialize_argument_information): Bind bounds
with corresponding args passed by reference.
gcc/testsuite/
PR tree-optimization/70786
* gcc.target/i386/pr70876.c: New test.
Jonathan Wakely [Tue, 10 May 2016 15:39:20 +0000 (16:39 +0100)]
Test begin and end functions for directory iterators
* include/experimental/bits/fs_dir.h (begin, end): Add noexcept.
* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
Test begin and end functions.
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Likewise.
Jakub Jelinek [Tue, 10 May 2016 14:30:02 +0000 (16:30 +0200)]
re PR target/70927 ([6 only] avx512dq instructions emitted even with -mavx512vl -mno-avx512dq)
PR target/70927
* config/i386/sse.md (<sse>_andnot<mode>3<mask_name>),
*<code><mode>3<mask_name>): For !TARGET_AVX512DQ and EVEX encoding,
use vp*[dq] instead of v*p[sd] instructions and adjust mode attribute
accordingly.
* gcc.target/i386/avx512vl-logic-1.c: New test.
* gcc.target/i386/avx512vl-logic-2.c: New test.
* gcc.target/i386/avx512dq-logic-2.c: New test.
David Malcolm [Tue, 10 May 2016 13:28:41 +0000 (13:28 +0000)]
Add debugging ruler to diagnostic-show-locus.c
When debugging diagnostic-show-locus.c, it's invaluable to have a
"ruler" showing column numbers.
This patch adds in support via a new "show_ruler_p" flag within
the diagnostic_context. There's no direct way for end-users to enable
this, but plugins can enable it by setting the flag, so the
plugin that tests the diagnostic subsystem uses this to verify that
the ruler is correctly printed.
gcc/ChangeLog:
* diagnostic-show-locus.c (layout::layout): Call show_ruler
if show_ruler_p was set on the context.
(layout::show_ruler): New method.
* diagnostic.h (struct diagnostic_context): Add field
"show_ruler_p".
gcc/testsuite/ChangeLog:
* gcc.dg/plugin/diagnostic-test-show-locus-bw.c
(test_very_wide_line): Add ruler to expected output.
* gcc.dg/plugin/diagnostic-test-show-locus-color.c
(test_very_wide_line): Likewise.
* gcc.dg/plugin/diagnostic_plugin_test_show_locus.c
(test_show_locus): Within the handling of "test_very_wide_line",
enable show_ruler_p on the diagnostic context.
Richard Biener [Tue, 10 May 2016 13:13:59 +0000 (13:13 +0000)]
re PR tree-optimization/71039 (ICE: verify_ssa failed (error: definition in block 4 does not dominate use in block 5) w/ -O1 and above)
2016-05-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/71039
* tree-ssa-phiprop.c: Include tree-ssa-loop.h.
(chk_uses): New function.
(propagate_with_phi): Verify we can safely replicate the lhs of an
aggregate assignment on all incoming edges.
Jonathan Wakely [Tue, 10 May 2016 12:22:32 +0000 (13:22 +0100)]
libstdc++/71037 Add base path to filesystem::canonical exceptions
PR libstdc++/71037
* src/filesystem/ops.cc (canonical(const path&, const path&)): Add
base path to exception.
* testsuite/experimental/filesystem/operations/canonical.cc: Test
paths contained in exception.
Andreas Krebbel [Tue, 10 May 2016 09:00:53 +0000 (09:00 +0000)]
S/390: Disable scalar vector instructions with -mno-vx.
Although the scalar variants of the vector instructions aren't
actually vector instructions they are still executed in the vector
facility and therefore need to be disabled when disabling the facility
with -mno-vx.
Fixed with the attached patch. Committed to head, GCC 6, and GCC 5
branches.
gcc/ChangeLog:
2016-05-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
Richard Biener [Tue, 10 May 2016 08:20:43 +0000 (08:20 +0000)]
re PR tree-optimization/70497 (Missed CSE of subregs on GIMPLE)
2016-05-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/70497
PR tree-optimization/28367
* tree-ssa-sccvn.c (vn_nary_build_or_lookup): New function
split out from ...
(visit_reference_op_load): ... here.
(vn_reference_lookup_3): Use it to handle subreg-like accesses
with simplified BIT_FIELD_REFs.
* tree-ssa-pre.c (eliminate_insert): Handle inserting BIT_FIELD_REFs.
* tree-complex.c (extract_component): Handle BIT_FIELD_REFs
correctly.
* gcc.dg/torture/20160404-1.c: New testcase.
* gcc.dg/tree-ssa/ssa-fre-54.c: Likewise.
* gcc.dg/tree-ssa/ssa-fre-55.c: Likewise.
DWARF: add abstract origin links on lexical blocks DIEs
Track from which abstract lexical block concrete ones come from in DWARF
so that debuggers can inherit the former from the latter. This enables
debuggers to properly handle the following case:
* function Child2 is nested in a lexical block, itself nested in
function Child1;
* function Child1 is inlined into some call site;
* function Child2 is never inlined.
Here, Child2 is described in DWARF only in the abstract instance of
Child1. So when debuggers decode Child1's concrete instances, they need
to fetch the definition for Child2 in the corresponding abstract
instance: the DW_AT_abstract_origin link on the lexical block that
embeds Child1 enables them to do that.
Bootstrapped and regtested on x86_64-linux.
gcc/ChangeLog:
* dwarf2out.c (add_abstract_origin_attribute): Adjust
documentation comment. For BLOCK nodes, add a
DW_AT_abstract_origin attribute that points to the DIE generated
for the origin BLOCK.
(gen_lexical_block_die): Call add_abstract_origin_attribute for
blocks from inlined functions.
Joel Sherrill [Tue, 10 May 2016 07:11:00 +0000 (07:11 +0000)]
[RTEMS] Fix moxie libgcc support
libgcc/
PR libgcc/70720
* config.host (moxie-*-rtems*): Merge this stanza with other moxie
targets so the same extra_parts are built. Also have tmake_file add
on to its value rather than override.
Alan Modra [Mon, 9 May 2016 23:12:20 +0000 (08:42 +0930)]
[RS6000] Stop regrename twiddling with split-stack prologue
PR target/70947
* config/rs6000/rs6000.c (rs6000_expand_split_stack_prologue): Stop
regrename modifying insns saving lr before __morestack call.
* config/rs6000/rs6000.md (split_stack_return): Similarly for
insns restoring lr after __morestack call.
Aaron Sawdey [Mon, 9 May 2016 16:56:30 +0000 (16:56 +0000)]
rs6000.c (rs6000_reassociation_width): Add function for TARGET_SCHED_REASSOCIATION_WIDTH to enable parallel...
* config/rs6000/rs6000.c (rs6000_reassociation_width): Add
function for TARGET_SCHED_REASSOCIATION_WIDTH to enable
parallel reassociation for power8 and forward.
Uros Bizjak [Mon, 9 May 2016 15:37:30 +0000 (17:37 +0200)]
i386.md (absneg splitters with general regs): Use general_reg_operand predicate.
* config/i386/i386.md (absneg splitters with general regs): Use
general_reg_operand predicate.
(btsq peephole2): Use x86_64_immediate_operand to check if new
value is suitable for immediate operand. Generate emitted insn
using RTL expressions.
(btcq peephole2): Ditto.
(btrq peephole2): Ditto. Generate correct immediate operand
for AND masking.
Fix handling of negative bitpos in expand_debug_expr
expand_debug_expr handled negative bit positions using:
else if (bitpos < 0)
{
HOST_WIDE_INT units
= (-bitpos + BITS_PER_UNIT - 1) / BITS_PER_UNIT;
op0 = adjust_address_nv (op0, mode1, units);
bitpos += units * BITS_PER_UNIT;
}
Here "units" is the negative of the (negative) byte offset, so I think
we should be offsetting OP0 by -units instead. E.g. a bitpos of -17
would give units==3, so this code would move OP0 up by 3 bytes and set
bitpos to 7, giving a total bitpos of 31.
Just noticed by inspection. An assert triggered for:
to check whether we had previously seen a nonzero multiple, but "mult" is
a pointer to the previous value rather than the previous value itself.
Noticed by inspection while working on another patch, so I don't have a
testcase. I tried adding an assert for combinations that were wrongly
rejected before but it didn't trigger during a bootstrap and regtest.
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