Rewrite size_must_be_zero_p with irange infrastructure.
Rewrite size_must_be_zero_p with irange infrastructure. Previous
implementation did not get the bits in [7fff,ffff]. This fixes a
handful of regressions.
Andrew Macleod [Fri, 6 Apr 2018 13:26:51 +0000 (13:26 +0000)]
Add logical AND folding support, and do empty range check in fold(), otherwise we can never be sure of the required range type of the folded exprression
Steven G. Kargl [Wed, 21 Mar 2018 01:07:43 +0000 (01:07 +0000)]
re PR fortran/85001 (ICE in gfc_build_array_type, at fortran/trans-types.c:1420)
2018-03-20 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/85001
* interface.c (symbol_rank): Remove bogus null pointer check that
crept in when translating a ternary operator into an if-else
constructor.
2018-03-20 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/85001
* gfortran.dg/interface_41.f90: New test.
Kyrylo Tkachov [Tue, 20 Mar 2018 17:13:16 +0000 (17:13 +0000)]
This PR shows that we get the load/store_lanes logic wrong for arm big-endian.
It is tricky to get right. Aarch64 does it by adding the appropriate lane-swapping
operations during expansion.
I'd like to do the same on arm eventually, but we'd need to port and validate the VTBL-generating
code and add it to all the right places and I'm not comfortable enough doing it for GCC 8, but I am keen
in getting the wrong-code fixed.
As I say in the PR, vectorisation on armeb is already severely restricted (we disable many patterns on BYTES_BIG_ENDIAN)
and the load/store_lanes patterns really were not working properly at all, so disabling them is not
a radical approach.
The way to do that is to return false in ARRAY_MODE_SUPPORTED_P for BYTES_BIG_ENDIAN.
Bootstrapped and tested on arm-none-linux-gnueabihf.
Also tested on armeb-none-eabi.
PR target/82518
* config/arm/arm.c (arm_array_mode_supported_p): Return false for
BYTES_BIG_ENDIAN.
* lib/target-supports.exp (check_effective_target_vect_load_lanes):
Disable for armeb targets.
* gcc.target/arm/pr82518.c: New test.
Nathan Sidwell [Tue, 20 Mar 2018 16:01:08 +0000 (16:01 +0000)]
[PR c++/84962] ICE with anon-struct member
https://gcc.gnu.org/ml/gcc-patches/2018-03/msg00961.html
PR c++/84962
* name-lookup.c (pushdecl_class_level): Push anon-struct's
member_vec, if there is one.
Martin Liska [Tue, 20 Mar 2018 14:14:17 +0000 (15:14 +0100)]
Handle -fno-guess-branch-probability properly in predict.c (PR ipa/84825).
2018-03-20 Martin Liska <mliska@suse.cz>
PR ipa/84825
* predict.c (rebuild_frequencies): Handle case when we have
PROFILE_ABSENT, but flag_guess_branch_prob is false.
2018-03-20 Martin Liska <mliska@suse.cz>
Jakub Jelinek [Tue, 20 Mar 2018 10:59:26 +0000 (11:59 +0100)]
re PR target/84845 (ICE: in extract_insn, at recog.c:2304: unrecognizable insn at -O2 and above at aarch64)
PR target/84845
* config/aarch64/aarch64.md (*aarch64_reg_<mode>3_neg_mask2): Rename
to ...
(*aarch64_<optab>_reg_<mode>3_neg_mask2): ... this. If pseudos can't
be created, use lowpart_subreg of operands[0] rather than operands[0]
itself.
(*aarch64_reg_<mode>3_minus_mask): Rename to ...
(*aarch64_ashl_reg_<mode>3_minus_mask): ... this.
(*aarch64_<optab>_reg_di3_mask2): Use const_int_operand predicate
and n constraint instead of aarch64_shift_imm_di and Usd.
(*aarch64_reg_<optab>_minus<mode>3): Rename to ...
(*aarch64_<optab>_reg_minus<mode>3): ... this.
Sudakshina Das [Tue, 20 Mar 2018 10:54:42 +0000 (10:54 +0000)]
[ARM][PR82989] Fix unexpected use of NEON instructions for shifts
This patch fixes PR82989 so that we avoid NEON instructions when
-mneon-for-64bits is not enabled. This is more of a short term fix
for the real deeper problem of making an early decision of choosing
or rejecting NEON instructions. There is now a new ticket PR84467 to
deal with the longer term solution.
(Please refer to the discussion in the bug report for more details).
Sudi
*** gcc/ChangeLog ***
2018-03-20 Sudakshina Das <sudi.das@arm.com>
PR target/82989
* config/arm/neon.md (ashldi3_neon): Update ?s for constraints
to favor GPR over NEON registers.
(<shift>di3_neon): Likewise.
*** gcc/testsuite/ChangeLog ***
2018-03-20 Sudakshina Das <sudi.das@arm.com>
PR target/82989
* gcc.target/arm/pr82989.c: New test.
Jakub Jelinek [Tue, 20 Mar 2018 08:14:42 +0000 (09:14 +0100)]
re PR target/84945 (UBSAN: gcc/config/i386/i386.c:33312:22: runtime error: shift exponent 32 is too large for 32-bit type 'int')
PR target/84945
* config/i386/i386.c (fold_builtin_cpu): For features above 31
use __cpu_features2 variable instead of __cpu_model.__cpu_features[0].
Use 1U instead of 1. Formatting fixes.
* gcc.target/i386/pr84945.c: New test.
* config/i386/cpuinfo.h (__cpu_features2): Declare.
* config/i386/cpuinfo.c (__cpu_features2): New variable for
ifndef SHARED only.
(set_feature): Define.
(get_available_features): Use set_feature macro. Set __cpu_features2
to the second word of features ifndef SHARED.
Jakub Jelinek [Mon, 19 Mar 2018 20:49:57 +0000 (21:49 +0100)]
re PR tree-optimization/84946 (UBSAN: in mem_valid_for_store_merging ../../gcc/gimple-ssa-store-merging.c:3951)
PR tree-optimization/84946
* gimple-ssa-store-merging.c (mem_valid_for_store_merging): Compute
bitsize + bitsize in poly_uint64 rather than poly_int64.
Jakub Jelinek [Mon, 19 Mar 2018 20:48:39 +0000 (21:48 +0100)]
re PR sanitizer/78651 (Incorrect exception handling when catch clause uses local class and PIC and sanitizer are active)
PR sanitizer/78651
* dwarf2asm.c: Include fold-const.c.
(dw2_output_indirect_constant_1): Set DECL_INITIAL (decl) to ADDR_EXPR
of decl rather than decl itself.
Jakub Jelinek [Mon, 19 Mar 2018 20:47:29 +0000 (21:47 +0100)]
re PR sanitizer/84761 (AddressSanitizer is not compatible with glibc 2.27 on x86)
PR sanitizer/84761
* sanitizer_common/sanitizer_linux_libcdep.cc (__GLIBC_PREREQ):
Define if not defined.
(DL_INTERNAL_FUNCTION): Don't define.
(InitTlsSize): For __i386__ if not compiled against glibc 2.27+
determine at runtime whether to use regparm(3), stdcall calling
convention for older glibcs or normal calling convention for
newer glibcs for call to _dl_get_tls_static_info.
Nathan Sidwell [Mon, 19 Mar 2018 18:56:22 +0000 (18:56 +0000)]
[PR c++/84835] ICE with generic lambda in extern "C"
https://gcc.gnu.org/ml/gcc-patches/2018-03/msg00890.html
PR c++/84835
* lambda.c (maybe_add_lambda_conv_op): Force C++ linkage.
* pt.c (build_template_decl): Propagate language linkage.
Sudakshina Das [Mon, 19 Mar 2018 18:50:32 +0000 (18:50 +0000)]
[PR81647][AARCH64] Fix handling of Unordered Comparisons in aarch64-simd.md
This patch fixes the inconsistent behavior observed at -O3 for the unordered
comparisons. According to the online docs (https://gcc.gnu.org/onlinedocs
/gcc-7.2.0/gccint/Unary-and-Binary-Expressions.html), all of the following
should not raise an FP exception:
- UNGE_EXPR
- UNGT_EXPR
- UNLE_EXPR
- UNLT_EXPR
- UNEQ_EXPR
Also ORDERED_EXPR and UNORDERED_EXPR should only return zero or one.
The aarch64-simd.md handling of these were generating exception raising
instructions such as fcmgt. This patch changes the instructions that are
emitted in order to not give out the exceptions. We first check each
operand for NaNs and force any elements containing NaN to zero before using
them in the compare.
Example: UN<cc> (a, b) -> UNORDERED (a, b)
| (cm<cc> (isnan (a) ? 0.0 : a, isnan (b) ? 0.0 : b))
The ORDERED_EXPR is now handled as (cmeq (a, a) & cmeq (b, b)) and
UNORDERED_EXPR as ~ORDERED_EXPR and UNEQ as (~ORDERED_EXPR | cmeq (a,b)).
ChangeLog Entries:
*** gcc/ChangeLog ***
2018-03-19 Sudakshina Das <sudi.das@arm.com>
PR target/81647
* config/aarch64/aarch64-simd.md (vec_cmp<mode><v_int_equiv>): Modify
instructions for UNLT, UNLE, UNGT, UNGE, UNEQ, UNORDERED and ORDERED.
Jim Wilson [Mon, 19 Mar 2018 18:08:24 +0000 (18:08 +0000)]
RISC-V: Fix bootstrap failure.
gcc/
PR bootstrap/84856
* config/riscv/riscv.c (riscv_function_arg_boundary): Use
PREFERRED_STACK_BOUNDARY instead of STACK_BOUNDARY.
(riscv_first_stack_step): Likewise.
(riscv_option_override): Use STACK_BOUNDARY instead of
MIN_STACK_BOUNDARY.
* config/riscv/riscv.h (STACK_BOUNDARY): Renamed from
MIN_STACK_BOUNDARY.
(BIGGEST_ALIGNMENT): Set to 128.
(PREFERRED_STACK_BOUNDARY): Renamed from STACK_BOUNDARY.
(RISCV_STACK_ALIGN): Use PREFERRED_STACK_BOUNDARY instead of
STACK_BOUNDARY.
Richard Biener [Mon, 19 Mar 2018 14:11:05 +0000 (14:11 +0000)]
re PR tree-optimization/84933 (ICE in set_value_range, at tree-vrp.c:288 since r257852)
2018-03-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/84933
* tree-vrp.c (set_and_canonicalize_value_range): Treat out-of-bound
values as -INF/INF when canonicalizing an ANTI_RANGE to a RANGE.
Richard Biener [Mon, 19 Mar 2018 14:08:58 +0000 (14:08 +0000)]
re PR tree-optimization/84859 (bogus -Warray-bounds on a memcpy in a loop)
2018-03-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/84859
* tree-ssa-phiopt.c (single_trailing_store_in_bb): New function.
(cond_if_else_store_replacement): Perform sinking operation on
single-store BBs regardless of MAX_STORES_TO_SINK setting.
Generalize what a BB with a single eligible store is.
Richard Biener [Mon, 19 Mar 2018 12:49:30 +0000 (12:49 +0000)]
re PR tree-optimization/84929 (ICE at -O3 on valid code on x86_64-linux-gnu: tree check: expected polynomial_chrec, have nop_expr in analyze_siv_subscript_cst_affine, at tree-data-ref.c:3018)
2018-03-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/84929
* tree-data-ref.c (analyze_siv_subscript_cst_affine): Guard
chrec_is_positive against non-chrec arg.
Steven G. Kargl [Sun, 18 Mar 2018 17:51:57 +0000 (17:51 +0000)]
re PR fortran/77414 (ICE in create_function_arglist, at fortran/trans-decl.c:2410)
2018-03-18 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/77414
* decl.c (get_proc_name): Check for a subroutine re-defined in
the contain portion of a subroutine. Change language of existing
error message to better describe the issue. While here fix whitespace
issues.
Don't try to vectorise COND_EXPR reduction chains (PR 84913)
The testcase ICEd for both SVE and AVX512 because we were trying
to vectorise a chain of COND_EXPRs as a reduction and getting
confused by reduc_index == -1.
2018-03-18 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
PR tree-optimization/84913
* tree-vect-loop.c (vectorizable_reduction): Don't try to
vectorize chains of COND_EXPRs.
gcc/testsuite/
PR tree-optimization/84913
* gfortran.dg/vect/pr84913.f90: New test.
Jakub Jelinek [Sat, 17 Mar 2018 11:12:00 +0000 (12:12 +0100)]
re PR target/84902 (549.fotonik3d_r from SPEC2017 fails verification with -Ofast -march=native on Zen since r258518)
PR target/84902
* config/i386/i386.c (initial_ix86_tune_features,
initial_ix86_arch_features): Use unsigned HOST_WIDE_INT rather than
unsigned long long.
(set_ix86_tune_features): Change ix86_tune_mask from unsigned int
to unsigned HOST_WIDE_INT, initialize to HOST_WIDE_INT_1U << ix86_tune
rather than 1u << ix86_tune. Formatting fix.
(ix86_option_override_internal): Change ix86_arch_mask from
unsigned int to unsigned HOST_WIDE_INT, initialize to
HOST_WIDE_INT_1U << ix86_arch rather than 1u << ix86_arch.
(ix86_function_specific_restore): Likewise.
Jakub Jelinek [Fri, 16 Mar 2018 21:01:16 +0000 (22:01 +0100)]
re PR target/84899 (ICE: in final_scan_insn_1, at final.c:3139 (error: could not split insn))
PR target/84899
* postreload.c (reload_combine_recognize_pattern): Perform
INTVAL addition in unsigned HOST_WIDE_INT type to avoid UB and
truncate_int_for_mode the result for the destination's mode.
Ian Lance Taylor [Fri, 16 Mar 2018 19:01:40 +0000 (19:01 +0000)]
libgo: add runtime/pprof/internal/profile.gox to noinst_DATA
Also add noinst_DATA to CHECK_DEPS; it's not needed in practice since
`make` will build noinst_DATA, but it's logically required and will
make a difference if any of the noinst_DATA sources change between
`make` and `make check`.
Tony Reix figured out why omitting packages from noinst_DATA didn't
seem to matter: because if gccgo can't find foo.gox, it will fall back
to reading the export data in foo.o, and foo.o will exist because
these packages go into libgo.a.
Vladimir Makarov [Fri, 16 Mar 2018 18:48:26 +0000 (18:48 +0000)]
re PR target/84876 (ICE on invalid code in lra_assign at gcc/lra-assigns.c:1601 since r258504)
2018-03-16 Vladimir Makarov <vmakarov@redhat.com>
PR target/84876
* lra-assigns.c (lra_split_hard_reg_for): Don't use
regno_allocno_class_array and sorted_pseudos.
* lra-constraints.c (spill_hard_reg_in_range): Ignore hard regs in
insns where regno is used.
2018-03-16 Vladimir Makarov <vmakarov@redhat.com>
PR target/84876
* gcc.target/i386/pr84876.c: New test.
Jakub Jelinek [Fri, 16 Mar 2018 12:46:12 +0000 (13:46 +0100)]
re PR c++/79937 (ICE in replace_placeholders_r)
PR c++/79937
PR c++/82410
* tree.h (TARGET_EXPR_NO_ELIDE): Define.
* gimplify.c (gimplify_modify_expr_rhs): Don't elide TARGET_EXPRs with
TARGET_EXPR_NO_ELIDE flag set unless *expr_p is INIT_EXPR.
* cp-tree.h (CONSTRUCTOR_PLACEHOLDER_BOUNDARY): Define.
(find_placeholder): Declare.
* tree.c (struct replace_placeholders_t): Add exp member.
(replace_placeholders_r): Don't walk into ctors with
CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag set, unless they are equal to
d->exp. Replace PLACEHOLDER_EXPR with unshare_expr (x) rather than x.
(replace_placeholders): Initialize data.exp.
(find_placeholders_r, find_placeholders): New functions.
* typeck2.c (process_init_constructor_record,
process_init_constructor_union): Set CONSTRUCTOR_PLACEHOLDER_BOUNDARY
if adding NSDMI on which find_placeholder returns true.
* call.c (build_over_call): Don't call replace_placeholders here.
* cp-gimplify.c (cp_genericize_r): Set TARGET_EXPR_NO_ELIDE on
TARGET_EXPRs with CONSTRUCTOR_PLACEHOLDER_BOUNDARY set on
TARGET_EXPR_INITIAL.
(cp_fold): Copy over CONSTRUCTOR_PLACEHOLDER_BOUNDARY bit to new
ctor.
* g++.dg/cpp1y/pr79937-1.C: New test.
* g++.dg/cpp1y/pr79937-2.C: New test.
* g++.dg/cpp1y/pr79937-3.C: New test.
* g++.dg/cpp1y/pr79937-4.C: New test.
* g++.dg/cpp1y/pr82410.C: New test.
projects / thirdparty / gcc.git / log
