I measured the latency and throughput of vcipher/vncipher/vxor instructions
for POWER8
vcipher/vncipher
throughput 6 instructions per cycle
latency 0.91 clock cycles
vxor
throughput 6 instructions per cycle
latency 0.32 clock cycles
So the ideal option for POWER8 is processing 8 blocks, it has +12%
performance over processing 4 blocks.
test/gostdsa-vko: add hashed test vectors from RFC 7836
It was not possible to check gostdsa_vko test vectors with the outputs
from RFC 7836 because Nettle lacked Streebog hash function. Now as the
function is supported, add full test vectors.
Emil Velikov [Mon, 11 May 2020 08:43:22 +0000 (09:43 +0100)]
examples: don't use deprecated OpenSSL hashing API
The direct $HASH_{Init,Update,Final} has been discouraged for a while.
With the upcoming OpenSSL 3.0 it will be officially deprecated.
Add a handy macro, to avoid repetition and mistakes like in the current
code. Namely - we're using SHA cblock/digest_len for md5 :-\
The macro will also make it easier to add more, as seen with next patch.
v2: Align it with the crypto implementations, namely:
- use openssh_hash_ctx::evp, use correct sizeof()
- move hash_update out of the macro
- remove forward declarations for hash functions
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Niels Möller [Tue, 31 Mar 2020 17:52:15 +0000 (19:52 +0200)]
Rework setting of LD_LIBRARY_PATH for tests.
* testsuite/Makefile.in (check): Pass only TEST_SHLIB_DIR
to the run-tests script, and leave setting of LD_LIBRARY_PATH and
related variables to that script.
* examples/Makefile.in (check): Likewise.
* run-tests: Check TEST_SHLIB_DIR, and set up LD_LIBRARY_PATH and
related member variables.
* config.make.in (abs_top_builddir, TEST_SHLIB_DIR): New variables.
H.J. Lu [Mon, 16 Mar 2020 12:17:34 +0000 (05:17 -0700)]
x86: Add x86-ibt-test.c
On Linux/x86, when CET is enabled, all indirect branch targets must
start with ENDBR instruction. Add x86-ibt-test.c to verify that missing
ENDBR instruction at indirect branch target will trigger SIGSEGV on CET
platforms.
contains shadow stack (SHSTK) and indirect branch tracking (IBT). When
CET is enabled, ELF object files must be marked with .note.gnu.property
section. Also when IBT is enabled, all indirect branch targets must
start with ENDBR instruction.
This patch adds ASM_X86_ENDBR and the x86 CET marker to config.m4.in when
CET is enabled. It updates PROLOGUE with ASM_X86_ENDBR.
Michael Weiser [Thu, 5 Mar 2020 19:13:07 +0000 (20:13 +0100)]
arm: Fix memxor for non-armv6+ big-endian systems
ARM assembly adjustments for big-endian systems contained armv6+-only
instructions (rev) in generic arm memxor code. Replace those with an
actual conversion of the leftover byte store routines for big-endian
systems. This also provides a slight optimisation by removing the
additional instruction as well as increased symmetry between little- and
big-endian implementations.
Signed-off-by: Michael Weiser <michael.weiser@gmx.de>
Daiki Ueno [Mon, 9 Mar 2020 12:01:18 +0000 (13:01 +0100)]
chacha: add variant that treats counter value as 32-bit
The ChaCha-Poly1305 implementation previously used the chacha_crypt
function that assumes the block counter is 64-bit long, while RFC 8439
defines that the counter is 32-bit long. Although this should be fine
as long as up to 256 gigabytes of data is encrypted with the same key,
it would be nice to use a separate functions (chacha_set_counter32 and
chacha_crypt32) that assume the counter is 32-bit long.
Daiki Ueno [Mon, 9 Mar 2020 12:01:17 +0000 (13:01 +0100)]
chacha: add function to set initial block counter
The ChaCha20 based header protection algorithm in QUIC requires a way
to set the initial value of counter:
https://quicwg.org/base-drafts/draft-ietf-quic-tls.html#name-chacha20-based-header-prote
This will add a new function chacha_set_counter, which takes an
8-octet initial value of the block counter.