Mike Frysinger [Wed, 18 May 2011 17:14:24 +0000 (13:14 -0400)]
sim: bfin: add new UART model (bf60x)
This models the latest UART implementation found on BF60x processors.
2012-08-28 Mike Frysinger <vapier@gentoo.org>
* configure.ac (SIM_AC_OPTION_HARDWARE): Add bfin_uart4.
* configure: Regenerated.
* dv-bfin_uart.c (bfin_uart_poll): Call bfin_uart_get_status with
new second argument.
(bfin_uart_get_status): Change to take a 2nd argument. Replace
TEMT | THRE with new txs argument.
* dv-bfin_uart.h: Include new dv-bfin_uart_core.h header.
(struct bfin_uart, bfin_uart_get_next_byte, bfin_uart_write_byte,
bfin_uart_get_status, bfin_uart_write_buffer, bfin_uart_read_buffer,
bfin_uart_reschedule): Delete.
* dv-bfin_uart2.c (bfin_uart_io_read_buffer): Call
bfin_uart_get_status with new second argument.
* dv-bfin_uart4.c, dv-bfin_uart4.h: New UART model.
* dv-bfin_uart_core.h: New file.
* machs.h (BFIN_MMR_UART4_SIZE): Define.
Mike Frysinger [Tue, 26 Apr 2011 02:15:32 +0000 (22:15 -0400)]
sim: bfin: make the core timer output port an edge
The output port of the core timer is currently always high and never goes
low, so make sure we lower the level after sending it out. This way the
other side (the CEC) knows when to delatch things.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-26 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_ctimer.c (bfin_ctimer_expire): Call hw_port_event a 2nd
time with a level of 0.
Mike Frysinger [Tue, 26 Apr 2011 01:42:17 +0000 (21:42 -0400)]
sim: bfin: keep output port levels from SIC level and up-to-date
When the internal interrupt routes get updated (via the IAR MMRs), we need
to resend all the output levels as they might have changed. We also need
to do this after the MMR write is committed instead of before so that we
send out the most up-to-date value.
Further, we need to send both high and low levels so that when a line goes
low, the other side is made aware of this.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-25 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_sic.c (bfin_sic_forward_interrupts): Declare new local
"levels" array. Drop empty ipend if check. Set levels to 1 instead
of calling hw_port_event directly. Add a new loop over the levels
array at the end of the func and move the HW_TRACE/hw_port_event
call there.
(bfin_sic_52x_io_write_buffer): Move the forward interrupts call
after the value32p write, and run this code for IAR MMRs too.
(bfin_sic_537_io_write_buffer, bfin_sic_54x_io_write_buffer,
bfin_sic_561_io_write_buffer): Likewise.
Mike Frysinger [Mon, 25 Apr 2011 23:12:51 +0000 (19:12 -0400)]
sim: bfin: separate port levels from isa levels in the CEC
Since the input ports are level based (coming from the SIC/ctimer), make
sure we keep those values separate from levels manually raised via insns
(like RAISE and EXCPT) or cleared via MMRs (writes to ILAT). This way
the peripherals can raise/lower their interrupt lines without affecting
manual tweaking, and we get behavior that matches the hardware.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-25 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_cec.c (bfin_cec): Add "plat" member.
(bfin_cec_io_read_buffer): Merge "plat" with "ilat" when reading
the ILAT MMR.
(bfin_cec_port_event): Use the incoming level to set/clear bits
in "plat". When the bit isn't yet set, also call _cec_raise.
(_cec_raise): Merge "plat" with "ilat" when calling __cec_get_ivg.
Mike Frysinger [Sat, 10 Apr 2010 20:52:32 +0000 (16:52 -0400)]
sim: tweak signed to unsigned local vars
This tweaks a lot of hardware code to use "unsigned" instead of "int" to
fix gcc warnings about signed/unsigned comparisons. In these cases, the
code is already working with unsigned variables, so there shouldn't be a
problem converting the local variables from "int".
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-04-10 Mike Frysinger <vapier@gentoo.org>
* dv-sockser.c (dv_sockser_init): Change local tmp var to unsigned.
* hw-ports.c, hw-ports.h (hw_port_encode): Change sizeof_buf arg to
unsigned.
* hw-properties.c (hw_add_range_array_property): Change local i var
to unsigned.
(hw_add_reg_array_property): Likewise.
(hw_add_string_array_property): Change local vars sizeof_array and
string_nr to unsigned.
(hw_find_string_array_property): Change local vars nr_entries to
unsigned.
* hw-tree.c (split_device_specifier): Change local len var to
unsigned.
(print_properties): Change local cell_nr var to unsigned.
* sim-core.c (sim_core_read_buffer): Change local nr_bytes var to
unsigned.
(sim_core_write_buffer): Likewise.
Mike Frysinger [Mon, 1 Jan 2024 23:14:13 +0000 (18:14 -0500)]
sim: ppc: merge misc igen APIs
The common igen code provides the same misc APIs as the ppc version,
so delete the ppc code and pull in the common one. There is one
minor difference: the ppc code has a unique dumpf function. The
common code switched to lf_printf for the same functionality, but
since that requires changes throughout the igen codebase, delay that
cleanup for now so we can merge the rest.
Mike Frysinger [Mon, 1 Jan 2024 22:17:50 +0000 (17:17 -0500)]
sim: ppc: rename igen max_insn_bit_size
We want to avoid conflicts with the common igen enums. This should
get migrated over to the common parsing logic, but for now, switch
the name to avoid redefinition.
Mike Frysinger [Mon, 1 Jan 2024 21:44:50 +0000 (16:44 -0500)]
sim: ppc: unify igen filter_filename implementations
Now that both igen implementations are in the top-level, we can unify
the filter_filename implementation between them since they're the same
(literally the same code).
Mike Frysinger [Mon, 1 Jan 2024 21:32:48 +0000 (16:32 -0500)]
sim: ppc: replace filter_filename with lbasename
The lbasename function from libiberty provides the same API as this
custom function. The common/ code already made the switch, so make
the same change to the ppc code to avoid target duplication.
Mike Frysinger [Mon, 1 Jan 2024 20:48:15 +0000 (15:48 -0500)]
sim: ppc: hoist igen compilation into top-level
This simplifies the build a bit (especially for deps in port subdirs),
and avoids recursive make. This in turn speeds up the build, and lets
us reuse existing build-time vs host-time logic from Makefile.am.
Mike Frysinger [Mon, 1 Jan 2024 20:26:21 +0000 (15:26 -0500)]
sim: ppc: drop build-config.h usage
This header is only used by the igen tool, and none of the igen code
depends on the configure-time checks. Delete the logic to simplify
to prepare for moving it to the local.mk code.
Mike Frysinger [Mon, 1 Jan 2024 20:24:12 +0000 (15:24 -0500)]
sim: ppc: simplify filter_host.c logic
Switch this from a build-time generation to a static include. This
makes the build rules a bit simpler, especially as we move them to
Automake from hand-written makefiles.
Mike Frysinger [Sun, 24 Dec 2023 10:21:30 +0000 (05:21 -0500)]
sim: frv: fix cmpb uninitialized variable usage
This code sets up the cc variable based on the comparison of other
registers, but it does so incrementally with bit operations, and it
never initializes the cc variable. Initialize it to 0 which the
cmpba insn is already doing.
Tom Tromey [Sun, 31 Dec 2023 23:36:44 +0000 (16:36 -0700)]
Run 'black' on tui-window.py
Mark pointed out that a recent patch of mine caused the buildbot to
complain about the formatting of some Python test code. This patch
re-runs 'black' to fix the problem.
Tom de Vries [Sun, 31 Dec 2023 08:39:45 +0000 (09:39 +0100)]
[gdb/testsuite] Fix typo in gdb.base/catch-syscall.exp
On aarch64-linux with a gdb build without libexpat, I run into:
...
(gdb) PASS: gdb.base/catch-syscall.exp: determine pipe syscall: \
catch syscall 59
continue
Continuing.
Catchpoint 5 (call to syscall 59), 0x0000fffff7e04578 in pipe () from \
/lib64/libc.so.6
(gdb) FAIL: gdb.base/catch-syscall.exp: determine pipe syscall: continue
...
In the test-case, this pattern handles either the syscall name or number for
the pipe syscall:
...
-re -wrap "Catchpoint $decimal \\(call to syscall (pipe|$SYS_pipe)\\).*" {
...
but the pattern for the pipe2 syscall mistakenly uses SYS_pipe instead of
SYS_pipe2:
...
-re -wrap "Catchpoint $decimal \\(call to syscall (pipe2|$SYS_pipe)\\).*" {
...
and consequently doesn't handle the pipe2 syscall number.
Tom Tromey [Wed, 13 Dec 2023 05:49:52 +0000 (22:49 -0700)]
Add keywords to TuiWindow.write
The gdb docs promise that methods with more than two or more arguments
will accept keywords. However, I found that TuiWindow.write didn't
allow them. This patch adds the missing support.
Tom de Vries [Sat, 30 Dec 2023 19:04:10 +0000 (20:04 +0100)]
[gdb/testsuite] Fix gdb.base/gdb-index-err.exp for root user
When running test-case gdb.base/gdb-index-err.exp in a container as root user,
I run into:
...
FAIL: gdb.base/gdb-index-err.exp: flag=: \
try to write index to a non-writable directory
FAIL: gdb.base/gdb-index-err.exp: flag=-dwarf-5: \
try to write index to a non-writable directory
...
The test-case creates a directory without write permissions:
...
$ ls -ald private
dr-xr-xr-x 2 root root 4096 Dec 29 06:26 private/
...
but apparently the root user is still able to write in it.
Fix this by making the test unsupported for the root user.
Tested on x86_64-linux.
Reviewed-By: Lancelot SIX <lancelot.six@amd.com>
PR testsuite/31197
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31197
dwarf, fortran: add support for DW_TAG_entry_point
Fortran provides additional entry points for subroutines and functions.
These entry points may use only a subset (or a different set) of the
parameters of the original subroutine. The entry points may be described
via the DWARF tag DW_TAG_entry_point.
This commit adds support for parsing the DW_TAG_entry_point DWARF tag.
Currently, between ifx/ifort/gfortran, only ifort is actually emitting
this tag. Both, ifx and gfortran use the DW_TAG_subprogram tag as
workaround/alternative. Thus, this patch really only adds more ifort
support. Even so, some of the attached tests still fail for ifort, due
to some wrong line info generated for the entry points in ifort.
After this patch it is possible to set a breakpoint in gdb with the
ifort compiled example at the entry points 'foo' and 'foobar', which was not
possible before.
As gcc and ifx do not emit the tag I also added a test to gdb.dwarf2
which uses some underlying c compiled code and adds some Fortran style DWARF
to it emitting the DW_TAG_entry_point. Before this patch it was not
possible to actually define breakpoint at the entry point tags.
For gfortran there actually exists a bug on bugzilla, asking for the use
of DW_TAG_entry_point over DW_TAG_subprogram:
but its review/pinging got lost after a while. I reworked it to fit the
current GDB.
Co-authored-by: Bernhard Heckel <bernhard.heckel@intel.com> Co-authored-by: Tim Wiederhake <tim.wiederhake@intel.com> Approved-by: Tom Tromey <tom@tromey.com>
gdb, dwarf: move part of dwarf2_get_pc_bounds into separate function
This commit is in preparation of the next commit. There, we will add
a second variation to retrieve the pc bounds for DIEs tagged with
DW_TAG_entry_point. Instead of dwarf_get_pc_bounds_ranges_or_highlow_pc
we will call a separate method for entry points. As the validity checks
at the endo f dwarf2_get_pc_bounds are the same for both variants,
we introduced the new dwarf_get_pc_bounds_ranges_or_highlow_pc method,
outsourcing part of dwarf2_get_pc_bounds.
This commit should have no functional impact on GDB.
changjiachen [Thu, 28 Dec 2023 11:59:39 +0000 (19:59 +0800)]
LoongArch: gas: Add support for tls le relax.
Add tls le relax related relocs support and testsuites in gas.
The main test is three new relocation items,
R_LARCH_TLS_LE_ADD_R, R_LARCH_TLS_LE_HI20_R,
R_LARCH_TLS_LE_LO12_R can be generated properly
and tls le insn format check.
gas/ChangeLog:
* config/tc-loongarch.c:
(loongarch_args_parser_can_match_arg_helper): Add support for relax.
* gas/testsuite/gas/loongarch/reloc.d: Likewise.
* gas/testsuite/gas/loongarch/reloc.s: Likewise.
* gas/testsuite/gas/loongarch/loongarch.exp: Likewise.
* gas/testsuite/gas/loongarch/tls_le_insn_format_check.s: New test.
Handle problems caused by symbol extensions in TLS LE, The processing
is similar to the macro RELOCATE_CALC_PC32_HI20 method.
3. Implement the tls le relax function.
bfd/ChangeLog:
* bfd-in2.h: Add relocs related to tls le relax.
* elfnn-loongarch.c:
(loongarch_relax_tls_le): New function.
(RELOCATE_TLS_TP32_HI20): New macro.
(loongarch_elf_check_relocs): Add new reloc support.
(perform_relocation): Likewise.
(loongarch_elf_relocate_section): Handle new relocs related to relax.
(loongarch_elf_relax_section): Likewise.
* elfxx-loongarch.c:
(LOONGARCH_HOWTO (R_LARCH_TLS_LE_ADD_R)): New reloc how to type.
(LOONGARCH_HOWTO (R_LARCH_TLS_LE_HI20_R)): Likewise.
(LOONGARCH_HOWTO (R_LARCH_TLS_LE_LO12_R)): Likewise.
* libbfd.h: Add relocs related to tls le relax.
* reloc.c: Likewise.
Jin Ma [Mon, 25 Dec 2023 08:49:21 +0000 (16:49 +0800)]
RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extension
In order to make it easier to complete the compiler's support for
the XTheadVector extension and to be as compatible as possible
with the programming model of the 'V' extension ([1]), we consider
adding a few pseudo instructions ([2]).
if the instruction starts at 4 bytes before the relocation offset.
They are similar to R_X86_64_GOTTPOFF and R_X86_64_GOTPC32_TLSDESC,
respectively. Linker can covert GOTTPOFF to
H.J. Lu [Thu, 8 Jun 2023 17:01:03 +0000 (10:01 -0700)]
x86-64: Add R_X86_64_CODE_4_GOTPCRELX
For
mov name@GOTPCREL(%rip), %reg
test %reg, name@GOTPCREL(%rip)
binop name@GOTPCREL(%rip), %reg
where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions,
add
# define R_X86_64_CODE_4_GOTPCRELX 43
if the instruction starts at 4 bytes before the relocation offset. It
similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX
as R_X86_64_GOTPCREL or convert the above instructions to
Define NT_X86_SHSTK which is the note for x86 Shadow Stack (SHSTK) to
support Intel SHSTK in Linux kernel.
For now only userspace shadow stack and kernel IBT are supported by the
linux kernel. This note should be used instead of NT_X86_CET introduced
in the commit "x86: Add NT_X86_CET note", as it is outdated and only
used by old binutils versions.
* i386-dis.c (JMPABS_Fixup): New Fixup function to disassemble jmpabs.
(print_insn): Add #UD exception for jmpabs.
(dis386): Modify a1 unit for support jmpabs.
* i386-mnem.h: Regenerated.
* i386-opc.tbl: New insns.
* i386-tbl.h: Regenerated.
Hu, Lin1 [Thu, 28 Dec 2023 01:06:41 +0000 (01:06 +0000)]
Support APX NDD optimized encoding.
This patch aims to optimize:
add %r16, %r15, %r15 -> add %r16, %r15
gas/ChangeLog:
* config/tc-i386.c (check_Rex_required): New function.
(can_convert_NDD_to_legacy): Ditto.
(match_template): If we can optimzie APX NDD insns, so rematch
template.
* testsuite/gas/i386/x86-64.exp: Add test.
* testsuite/gas/i386/x86-64-apx-ndd-optimize.d: New test.
* testsuite/gas/i386/x86-64-apx-ndd-optimize.s: Ditto.
* gas/config/tc-i386.c (operand_size_match):
Support APX NDD that the number of operands is 3.
(build_apx_evex_prefix): Change for ndd encode.
(process_operands): Ditto.
(build_modrm_byte): Ditto.
(match_template): Support swap the first two operands for
APX NDD.
* testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd.
* testsuite/gas/i386/x86-64-apx-ndd.d: New test.
* testsuite/gas/i386/x86-64-apx-ndd.s: Ditto.
* testsuite/gas/i386/x86-64-pseudos.d: Add test.
* testsuite/gas/i386/x86-64-pseudos.s: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
Cui, Lili [Thu, 28 Dec 2023 01:06:40 +0000 (01:06 +0000)]
Add tests for APX GPR32 with extend evex prefix
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* testsuite/gas/i386/x86-64-apx-egpr-inval.l: Add some insn don't
support gpr32.
* testsuite/gas/i386/x86-64-apx-egpr-inval.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Add new test.
* testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: New test.
* testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-egpr.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-egpr.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted.s: New test.
Cui, Lili [Thu, 28 Dec 2023 01:06:40 +0000 (01:06 +0000)]
Support APX GPR32 with extend evex prefix
This patch adds non-ND, non-NF forms of EVEX promotion insn.
EVEX extension of legacy instructions:
All promoted legacy instructions are placed in EVEX map 4, which is
currently reserved.
EVEX extension of EVEX instructions:
All existing EVEX instructions are extended by APX using the extended
EVEX prefix, so that they can access all 32 GPRs.
EVEX extension of VEX instructions:
Promoting a VEX instruction into the EVEX space does not change the map
id, the opcode, or the operand encoding of the VEX instruction.
Note: The promoted versions of MOVBE will be extended to include the “MOVBE
reg1, reg2”.
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
Cui, Lili [Thu, 28 Dec 2023 01:06:39 +0000 (01:06 +0000)]
Support APX GPR32 with rex2 prefix
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy
instructions. We added the NoEgpr flag in i386-gen.c for instructions
that do not support EGPR.
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* config/tc-i386.c
(enum i386_error): Add unsupported_EGPR_for_addressing
and invalid_pseudo_prefix.
(struct _i386_insn): Add rex2 and rex2_encoding for
gpr32.
(cpu_arch): Add apx_f.
(is_cpu): Ditto.
(register_number): Handle RegRex2 for gpr32.
(is_apx_rex2_encoding): New func. Test rex2 prefix encoding.
(build_rex2_prefix): New func. Build legacy insn in
opcode 0/1 use gpr32 with rex2 prefix.
(establish_rex): Handle rex2 and rex2_encoding.
(optimize_encoding): Handel add r16-r31 for registers.
(md_assemble): Handle apx encoding.
(parse_insn): Handle Prefix_REX2.
(check_EgprOperands): New func. Check if Egprs operands
are valid for the instruction
(match_template): Handle Egpr operands check.
(set_rex_rex2): New func. set i.rex and i.rex2.
(build_modrm_byte): Ditto.
(output_insn): Handle rex2 2-byte prefix output.
(check_register): Handle check egpr illegal without
target apx, 64-bit mode and with rex_prefix.
* doc/c-i386.texi: Document .apx.
* testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid
in 64-bit mode.
* testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto.
* testsuite/gas/i386/rex-bad: Adjust rex testcase.
* testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto.
* testsuite/gas/i386/x86-64-opcode-inval.d: Ditto.
* testsuite/gas/i386/x86-64-opcode-inval.s: Ditto.
* testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test.
* testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto.
* testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test.
* testsuite/gas/i386/x86-64-pseudos.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Run APX tests.
* testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test.
* testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test.
* testsuite/gas/i386/x86-64-apx-rex2.d: New test.
* testsuite/gas/i386/x86-64-apx-rex2.s: New test.
The PRU architecture documentation [1] was used for the initial GNU
simulator implementation. But recently [2] TI confirmed the carry
behaviour was wrongly documented. In reality, the PRU carry behaves
like the carry in ARM processors.
This patch fixes simulator to align with latest recommendations from TI.
The new carry.s test was also validated to pass on real hardware -
a BeaglePlay board [3]. That test is a bit long because TI still
has not released official updates for the PRU documents. And I wanted
to ensure simulator handles all edge cases exactly as the real hardware
does.
The addend of SUB_ULEB128 should be zero if using .uleb128, but we make it
non-zero by accident in assembler before. This causes troubles by applying
the above commit, since the calculation is changed to support .reloc *SUB*
relocations with non-zero addend.
We encourage people to rebuild their stuff to get the non-zero addend of
SUB_ULEB128, but that might need some times, so report warnings to inform
people need to rebuild their stuff if --check-uleb128 is enabled.
Since the failed .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use,
it may acceptable that stop supproting them until people rebuld their stuff,
maybe half-year or a year later. Or maybe we should teach people that don't
write the .reloc R_RISCV_SUB* with non-zero constant, and then report
warnings/errors in assembler.
bfd/
* elfnn-riscv.c (perform_relocation): Ignore the non-zero addend of
R_RISCV_SUB_ULEB128.
(riscv_elf_relocate_section): Report warnings to inform people need
to rebuild their stuff if --check-uleb128 is enabled. So that can
get the right non-zero addend of R_RISCV_SUB_ULEB128.
* elfxx-riscv.h (struct riscv_elf_params): Added bool check_uleb128.
ld/
* NEWS: Updated.
* emultempl/riscvelf.em: Added linker risc-v target options,
--[no-]check-uleb128, to enable/disable checking if the addend of
uleb128 is non-zero or not. So that people will know they need to
rebuild the objects with binutils 2.42 and up, to get the right zero
addend of SUB_ULEB128 relocation, or they may get troubles if using
.reloc.
* ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* ld/testsuite/ld-riscv-elf/pr31179*: New test cases.
Alan Modra [Tue, 26 Dec 2023 12:16:56 +0000 (22:46 +1030)]
asan: buffer overflow in loongarch_elf_rtype_to_howto
Seen when running ld-loongarch-elf/tlsdesc-dso test.
elfxx-loongarch.c:1844:32: runtime error: index 125 out of bounds for
type 'loongarch_reloc_howto_type [124]'
So either the loongarch_howto_table needs three more
LOONGARCH_EMPTY_HOWTO entries, or loongarch_elf_rtype_to_howto should
be testing for r_type < ARRAY_SIZE (loongarch_howto_table). I figure
it's worth wasting a little more space to get faster lookup.
* elfxx-loongarch.c (loongarch_howto_table): Add
LOONGARCH_EMPTY_HOWTO entries for 121..123.
(loongarch_elf_rtype_to_howto): Don't support slow lookup.
Assert exact table size and r_type indexing. Omit return cast.
(loongarch_reloc_name_lookup): Omit assertion and return cast.
(loongarch_reloc_type_lookup): Likewise.
Alan Modra [Tue, 26 Dec 2023 05:50:34 +0000 (16:20 +1030)]
PR31191, objcopy leaves temporary files
Fix the ENOTDIR rmdir too.
PR 31191
* objcopy.c (copy_archive): Localise uses of "l". Remove
const from name_list.name. Unlink output element on bfd_close
error, and NULL list->name to indicate file is removed. Adjust
cleanup to prevent rmdir on non-existent file.
Mike Frysinger [Wed, 27 Dec 2023 03:53:31 +0000 (22:53 -0500)]
sim: common: pull in newlib extensions for Linux compatibility
Since newlib allows people to opt-in to extra errno names, pull them
into our table too. The values don't conflict with each other -- the
newlib names & values are distinct from newlib's Linux compatibility.
Lulu Cai [Tue, 31 Oct 2023 08:11:56 +0000 (16:11 +0800)]
LoongArch: Add support for TLSDESC in ld.
1.The linker for each DESC generates a R_LARCH_TLS_DESC64 dynamic
relocation, which relocation is placed at .rela.dyn.
TLSDESC always allocates two GOT slots and one dynamic relocation
space to TLSDESC.
2. When using multiple ways to access the same TLS variable, a
maximum of 5 GOT slots are used. For example, using GD, TLSDESC,
and IE to access the same TLS variable, GD always uses the first
two of the five GOT, TLSDESC uses the third and fourth, and IE
uses the last.
Alan Modra [Sun, 24 Dec 2023 04:11:06 +0000 (14:41 +1030)]
Re: LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">
This fixes the buffer overflow added in commit 22b78fad28, and a few
other problems.
* loongarch-coder.c (loongarch_split_args_by_comma): Don't
overflow buffer when args == "". Don't remove unbalanced
quotes. Don't trim last arg if max number of args exceeded.
Simon Marchi [Thu, 21 Dec 2023 16:51:38 +0000 (16:51 +0000)]
gdb: make value::allocate_register_lazy store id of next non-inline frame
Some spots loop on the frame chain to find the first next non-inline
frame, and pass that as the "next frame" to
value::allocate_register_lazy / value::allocate_register. This is
necessary if the value is used in the process of computing the id of
"this frame". If the frame next to "this frame" is inlined into "this
frame", then you that next frame won't have a computed id yet. You have
to go past that to find the next non-inline frame, which will have a
computed id.
In other cases, it's fine to store the id of an inline frame as the
"next frame id" in a register struct value. When trying to unwind a
register from it, it will just call inline_frame_prev_register, which
will forward the request to the next next frame, until we hit the next
physical frame.
I think it would make things simpler to just never store the id of an
inline frame as the next frame id of register struct values, and go with
the first next non-inline frame directly. This way, we don't have to
wonder which code paths have to skip inline frames when creating
register values and which don't.
So, change value::allocate_register_lazy to do that work, and remove the
loops for the callers that did it.
Simon Marchi [Sun, 24 Dec 2023 15:38:35 +0000 (10:38 -0500)]
gdb: remove VALUE_REGNUM, add value::regnum
Remove VALUE_REGNUM, replace it with a method on struct value. Set
`m_location.reg.regnum` directly from value::allocate_register_lazy,
which is fine because allocate_register_lazy is a static creation
function for struct value.
Remove VALUE_NEXT_FRAME_ID, replace it with a method on struct value. Set
`m_location.reg.next_frame_id` directly from value::allocate_register_lazy,
which is fine because allocate_register_lazy is a static creation
function for struct value.
Simon Marchi [Thu, 21 Dec 2023 16:32:55 +0000 (16:32 +0000)]
gdb: implement address_from_register using value_from_register
As explained in the comment removed by the previous commit "gdb: pass
non-nullptr frame to gdbarch_value_from_register in
address_from_register", address_from_register copies some implementation
bits from value_from_register:
/* This routine may be called during early unwinding, at a time
where the ID of FRAME is not yet known. Calling value_from_register
would therefore abort in get_frame_id. However, since we only need
a temporary value that is never used as lvalue, we actually do not
really need to set its VALUE_NEXT_FRAME_ID. Therefore, we re-implement
the core of value_from_register, but use the null_frame_id. */
This is no longer relevant, since we now create a value with a valid next
frame id, so change address_from_register to use value_from_register.
projects / thirdparty / binutils-gdb.git / log
