Works:
------
- (24) RJ-45 ethernet ports
- Switch functions
- Buttons
- LEDs (partial support, the wrong LEDs light up)
- Manual fan control
Not yet enabled:
----------------
- PoE (requires patches to realtek-poe to support i2c)
- Combo ports (link is up, but no data is transferred)
Fans:
-----
After boot, the fans are running in full speed mode. You can interact
with the fan controller at /sys/class/hwmon/
Installation:
-------------
This device uses ZyNOS instead of Linux, this makes installation a bit
more cumbersome. Serial console is required!
1. Set the switch to boot from the first image. This step is crucial,
it will fail to boot if this is not set properly.
2. Connect to the switch using serial and interrupt the boot process
to enter debug/recovery mode.
3. Load the OpenWrt initramfs image via XMODEM. You need to obtain an
unlock code, based on your MAC address, first. See the excellent write
up at https://www.ixo.de/info/zyxel_uclinux/ for details. Replace
unlock_code in the commands below by the code obtained.
After running ATBA5, the terminal needs to be closed and re-opened
with 115200 baud. This speeds up the file transfer significantly!
The file length in bytes need to be given instead of file_length below.
You also need an XMODEM upload utility like "lrzsz-sx -X" to transfer
the file. Start the XMODEM upload after running the ATUPxxxx command:
NB: You do not need to touch the loader binary unless it's recommended.
The loader is not part of a regular sysupgrade file and will be left
untouched. The boot loader only checks if the loader is valid to be
able to boot.
Recovery/ Return to stock:
--------------------------
Just spam the "u" key during (or "z" for 9600 baud) during memory testing
to trigger a recovery XMODEM upload at 115200 baud. A standard OEM upgrade
image works properly.
1. Obtain the original MAC address table from the stock bootlog, for
example:
setting device eth0 to 00:90:7f:00:00:01
setting device eth1 to 00:90:7f:00:00:02
setting device eth2 to 00:90:7f:00:00:03
setting device eth3 to 00:90:7f:00:00:04
setting device eth4 to 00:90:7f:00:00:05
setting device eth5 to 00:90:7f:00:00:06
setting device eth6 to 00:90:7f:00:00:07
2. Open the case and move jumper JP1 from 2-3 to 1-2 to enter FAILSAFE
mode.
3. Power on the device and interrupt the boot process to access the U-Boot
shell.
4. Program the MAC base address into the EEPROM (text after '#' is a
comment):
mac ports 3
mac 2 00:90:7f:00:00:01 # first MAC address from bootlog
mac save
5. Reset the device and enter the U-Boot console again.
6. Connect a TFTP server to port 6 and boot the initramfs image:
7. (Optional) Backup all MTD partitions if you want the ability to restore
stock firmware.
8. Perform a normal sysupgrade from the initramfs environment.
9. Power off the device and move jumper JP1 back to 2-3.
10. The device will now boot OpenWrt.
Known issues:
- LCD, buttons and LEDs are controlled by an external MCU; the protocol is
currently unknown.
- The internal connection between the two Marvell switches is unused by
OpenWrt.
- The stock firmware uses an empty U-Boot environment; saving variables
modifies the environment and prevents a normal boot. FAILSAFE U-Boot
remains functional.
- WatchGuard configuration is encrypted; DSA MAC addresses are stored in
this configuration.
- Failsafe Ethernet works on port1.
JINLIANG GU [Sat, 10 Jan 2026 01:45:58 +0000 (09:45 +0800)]
netifd: dhcp: suppress udhcpc default vendor class if specified in sendopts
When DHCP Option 60 is specified via sendopts (hex, decimal, or named
formats), udhcpc sends its default "udhcp <version>" string alongside
the custom value, which causes authentication failures with some ISPs.
This fix detects Option 60 in sendopts and automatically passes -V ""
to udhcpc to suppress the default version string while allowing
multiple user-defined vendor classes.
Goetz Goerisch [Fri, 9 Jan 2026 20:14:47 +0000 (21:14 +0100)]
feeds: revert to git.openwrt.org
This reverts the feeds.conf.default to git.openwrt.org
Fixes: 66e6ebbc1ea6c661bcbc85702066e2654da9c26a (microchipsw: drop source-only) Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21475 Signed-off-by: Robert Marko <robimarko@gmail.com>
Installation via bootloader:
* open serial console (baud rate 115200)
* interrupt boot process by pressing any key during boot
* boot the OpenWrt initramfs:
# rtk network on
# tftpboot 0x8f000000 /tftpboot/openwrt-realtek-rtl839x-edgecore_ecs4100-12ph-initramfs-kernel.bin
# bootm
* copy openwrt-realtek-rtl839x-edgecore_ecs4100-12ph-squashfs-sysupgrade.bin
to /tmp and use sysupgrade to install it:
# sysupgrade /tmp/openwrt-realtek-rtl839x-edgecore_ecs4100-12ph-squashfs-sysupgrade.bin
Even though U-Boot claims the switch is based on the RTL8392M SoC, my
device is based on the RTL8393M SoC. I have confirmed this by removing
the heatsink, and the Linux kernel agrees with this. Therefore the DTS
has the rtl8393_ prefix.
realtek: eth: move init_mac() into configuration structure
Avoid family checks where possible. Now that the init_mac()
functions are in perfect shape include them into the
configuration structure. While we are here rename them
to the new driver prefix.
The ethernet driver must initialize the chip for proper operation.
Currently there exist functions for RTL838x, RTL839x and RTL931x.
All of them are called differently. Combine them in a central call
location.
Robert Marko [Sun, 2 Nov 2025 14:15:35 +0000 (15:15 +0100)]
microchipsw: lan969x: add Novarq Tactical 1000
Novarq Tactical 1000 is a LAN9696 based switch.
Specifications:
* CPU: Microchip LAN9696 switch SoC
* DRAM: 2GB DDR4
* Storage:
* 32MB QSPI NOR
* 16GB eMMC
* Networking:
* 24 x 10/100/1000 RJ45 via LAN8804 Quad PHY-s over QSGMII
* 4 x 100/1000/2500/5000/10000 SFP+ ports
* 1 x 10/100/1000 management RJ45 via LAN8840 PHY over RGMII (U-Boot too)
* USB: 1 x USB2.0 Type-A
* Management via USB-C (MCP2200):
* UART @ 115200 baud (Default), 921600 possible
* GPIO-s for bootstrap and reset
* LED-s:
* 2 per networking port (Green and Yellow)
* Green status LED
* Soft reset GPIO
* Power: 12V DC barrel jack
* External PoE:
* Option for PoE add-on
* Temperature Sensors:
* TMP1075 onboard
* CPU temperature
* Microchip MCP79402 RTC with battery back-up
* Microchip ATECC608C secure peripheral
* CPU heatsink with PWM fan
* Onboard header for case fan
Installation instructions:
1. Connect to UART via the USB-C port
2. Connect the management port
3. Boot and interrupt U-Boot
4. TFTP the OpenWrt initramfs image and boot it
5. SCP the OpenWrt eMMC GPT image to a running OpenWrt initramfs to /tmp
openwrt-microchipsw-lan969x-novarq_tactical-1000-squashfs-emmc-gpt.img.gz
And decompress it via:
gzip -d /tmp/openwrt-microchipsw-lan969x-novarq_tactical-1000-squashfs-emmc-gpt.img.gz
Jonas Jelonek [Tue, 6 Jan 2026 19:54:44 +0000 (19:54 +0000)]
realtek: mdio: drop SerDes access functionality
The SerDes access functionality in the mdio-realtek-otto drivers was
meant to be temporary, at least from a certain point on. The user was
all the SerDes configuration that lived in the PHY and DSA drivers.
Now that SerDes configuration has moved completely to the PCS driver,
there is no user of this code anymore. Instead, the PCS driver uses a
separate driver 'mdio-realtek-otto-serdes' to access the SerDes. Thus,
drop all that unused functionality from the "normal" mdio driver.
This commit adds the sysupgrade and factory images for T4240RDB board in
both variants:
- nor: for booting and read whole system from NOR memory
- sdboot: for booting and read whole system from SD card
SD Card images install:
- Burn image to sdcard. E.g:
gunzip -c gunzip -c openwrt-qoriq-generic-fsl_T4240RDB-squashfs-sdcard.img.gz | \
sudo dd of=/dev/mmcblk0 conv=fsync,notrunc status=progress bs=4M && sync
- Download lastest Cortina PHY firmware from NXP github [1], if you accept their
EULA [2].
- Install Cortina PHY on image, E.g:
dd if=cs4315-cs4340-PHY-ucode.txt of=/dev/mmcblk0 bs=1 seek=2M
- Insert SD-Card to SD slot
- Switch SW3.4 to OFF
- Configre mac addresses from sticker in u-boot. E.g:
setenv ethaddr 00:10:f3:3a:a8:66
setenv eth1addr 00:10:f3:3a:a8:67
setenv eth2addr 00:10:f3:3a:a8:68
setenv eth3addr 00:10:f3:3a:a8:69
setenv eth4addr 00:10:f3:3a:a8:6a
setenv eth5addr 00:10:f3:3a:a8:6b
setenv eth6addr 00:10:f3:3a:a8:6c
setenv eth7addr 00:10:f3:3a:a8:6d
setenv eth8addr 00:10:f3:3a:a8:6e
setenv eth9addr 00:10:f3:3a:a8:6f
setenv eth10addr 00:10:f3:3a:a8:70
setenv eth11addr 00:10:f3:3a:a8:71
saveenv
- reset and boot
NOR images install:
- download and extract factory image on tftp server root
- boot device and stop in u-boot (from nor or sd card u-boot)
- configure server and ip address. E.g:
setenv ipaddr 192.168.1.2
setenv serverip 192.168.1.1
- Download image and run flashing:
tftpboot $loadaddr openwrt-qoriq-generic-fsl_T4240RDB-squashfs-factory-nor.bin
protect off all
erase $fwaddr +$filesize
cp.b $loadaddr $fwaddr $filesize
- Switch SW3.4 to ON
- Switch SW3.1-3 to OFF
- reboot
- Do postprocessing (see bellow)
NOR images post processing:
- Configre mac addresses from sticker in u-boot. E.g:
setenv ethaddr 00:10:f3:3a:a8:66
setenv eth1addr 00:10:f3:3a:a8:67
setenv eth2addr 00:10:f3:3a:a8:68
setenv eth3addr 00:10:f3:3a:a8:69
setenv eth4addr 00:10:f3:3a:a8:6a
setenv eth5addr 00:10:f3:3a:a8:6b
setenv eth6addr 00:10:f3:3a:a8:6c
setenv eth7addr 00:10:f3:3a:a8:6d
setenv eth8addr 00:10:f3:3a:a8:6e
setenv eth9addr 00:10:f3:3a:a8:6f
setenv eth10addr 00:10:f3:3a:a8:70
setenv eth11addr 00:10:f3:3a:a8:71
saveenv
- boot
- Download and refresh RCW stored in eeprom:
tr '\0' '\377' < /dev/zero | dd bs=256 of=/sys/bus/i2c/devices/0-0050/eeprom
cat /tmp/openwrt-qoriq-generic-fsl_T4240RDB-squashfs-rcw.bin > /sys/bus/i2c/devices/0-0050/eeprom
- Download lastest Cortina PHY firmware from NXP github [1], if you accept their
EULA [2].
- Install Cortina PHY on image, E.g:
mtd write cs4315-cs4340-PHY-ucode.txt /dev/mtd4
- reset and boot
Pawel Dembicki [Fri, 7 Oct 2022 12:25:20 +0000 (14:25 +0200)]
package: u-boot: initial support for qoriq arch
This package adds initial u-boot support for qoriq target.
U-boot for qoriq devices must be compiled with 32-bit compiler and
linked with 32-bit linker. It's part of mpc 85xx target. But qoriq
target is 64-bit. As workaround, mpc85xx binary toolchain is downloaded
only for this u-boot.
Daniel Golle [Wed, 7 Jan 2026 15:41:17 +0000 (15:41 +0000)]
kernel: net: phy: mxl-gpy: replace downstream SGMII AN hack
Replace downstream hack disabling SGMII in-band AN on the MediaTek platform
with pending upstream patch announcing in-band AN capabilities and implementing
configuring in-band AN in the PHY driver.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
John Audia [Fri, 9 Jan 2026 13:16:09 +0000 (08:16 -0500)]
x86: switch from CONFIG_HZ_PERIODIC to CONFIG_NO_HZ_IDLE
Running with CONFIG_HZ_PERIODIC=y keeps the scheduler tick running
continuously, which produces higher jitter and lower power efficiency.
In contrast, CONFIG_NO_HZ_IDLE=y (the upstream default) stops the tick
only when the CPU is idle, giving lower idle power and normal runtime
jitter.
An Intel N150-based router/firewall was tested using two kernel builds:
one with CONFIG_HZ_PERIODIC=y, and one with CONFIG_NO_HZ_IDLE=y. Power
consumption was measured while the system was essentially idle (no
meaningful traffic). The CONFIG_NO_HZ_IDLE=y build consistently used
less power.
Details: The two power-measurement methods were:
1. PkgWatt from turbostat (software)
2. Wall-power measurement using a Kill-A-Watt (hardware)
The test began by zeroing the Kill-A-Watt and simultaneously running:
turbostat --quiet --Summary --interval 10 --show Busy%,PkgWatt
The test duration was defined by the time required for the Kill-A-Watt
to accumulate 0.005 kWh, after which the average wattage was calculated.
realtek: phy: keep register state during RTL8214FC fibre check
Reading the fibre status of a RTL8214FC needs access to the
page register (31) and the extended page register (30).
The current implementation has two issues.
- The extended page register is not restored after changes
- Instead of register 30 its write-only sibling 29 is used.
This has the following side effect:
During regular polling kernel calls rtl8214fc_read_status
and determines the media status via __rtl8214fc_media_is_fibre.
Writing to register 29 a copy of that value is handed over
to register 30. This makes use of mdio tools for the first
port of the RTL8214FC hard. Register 30 is overwritten with
zero every second.
Change access from register 29 to register 30 and adapt
the sequence to restore register 30 contents at the end.
Chukun Pan [Fri, 5 Dec 2025 12:16:02 +0000 (20:16 +0800)]
mediatek: fix 2.5G PHY LED polarity for MT7987
The patch that adds MT7987 support to the mtk-2p5ge
driver does the following:
case MTK_2P5GPHY_ID_MT7987:
phy_clear_bits_mmd MTK_PHY_LED_ON_POLARITY
case MTK_2P5GPHY_ID_MT7988:
phy_set_bits_mmd.. MTK_PHY_LED_ON_POLARITY
phy_set_bits_mmd... MTK_PHY_LED_ON_POLARITY | xxx
This clearly resulted in the LED polarity of the 2.5G PHY
on the MT7987 being reversed. Remove redundant MMD operations
to fix the 2.5G PHY LED error on Bananapi BPi-R4 Lite.
Fixes: d62fc50f ("mediatek: import patches from SDK to support MT7987 Ethernet") Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Shiji Yang [Thu, 8 Jan 2026 13:10:56 +0000 (21:10 +0800)]
tools/squashfs4: fix rare data corruption issue
There is a chance that the squashfs4 tool may create a broken image
under certain conditions. Backport the fix from upstream to address
this issue.
Report: https://forum.openwrt.org/t/bug-squashfs4-tools-4-7-4-create-corrupted-image/244894 Fixes: 64432358e098 ("tools/squashfs4: update to 4.7.3") Reported-by: Oleg S <remittor@gmail.com> Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Link: https://github.com/openwrt/openwrt/pull/21458 Signed-off-by: Robert Marko <robimarko@gmail.com>
Jonas Jelonek [Sun, 9 Nov 2025 13:29:25 +0000 (13:29 +0000)]
realtek: pcs: rtl839x: setup SerDes in PCS driver
Add the SerDes setup hooks in the PCS driver for RTL839x so that
pcs_config actually triggers configuration. Adjust the DTS of all
devices accordingly by adding pcs-handles and dropping phy-handles.
Add basic SerDes setup functionality which determines and sets the
hardware mode of a SerDes, and does a SerDes reset. This is restricted
to the 10G SerDes only as the 5G SerDes are setup properly by default.
Further initialization will be needed for the modes to function properly
Refactor the previously added SerDes reset sequence. Use the SerDes
MDIO interface instead of plain writes into the switchcore's register
space. Moreover, simplify the sequence because the SDK version is
unnecessarily complex.
qualcommax: ipq50xx: Correct USB DWC3 wrapper interrupts
Interrupts for DWC3 node were completely mixed up - SPI interrupt 62 is
not listed in reference manual at all. It was also causing dtbs_check
warnings:
ipq5018-rdp432-c2.dtb: usb@8af8800 (qcom,ipq5018-dwc3): interrupt-names:0: 'pwr_event' was expected
ipq5018-rdp432-c2.dtb: usb@8af8800 (qcom,ipq5018-dwc3): interrupt-names: ['hs_phy_irq'] is too short
Warning itself was introduced by commit 53c6d854be4e ("dt-bindings: usb:
dwc3: Clean up hs_phy_irq in binding"), but this was trying to bring
sanity to the interrupts overall, although did a mistake for IPQ5018.
IPQ5018 does not have QUSB2 PHY and its interrupts should rather match
ones used in IPQ5332.
Correct it by using interrupts matching the bindings and reference
manual.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/21454 Signed-off-by: Robert Marko <robimarko@gmail.com>
In IPQ5018, the reference clock to the CMN PLL block from the on-board
Wi-Fi has its divider set to 2. This divider wasn't taken into
consideration when calculating the CMN PLL clock rate which meant the
resulting clock rate was doubled.
With the reference clock divider being accounted for in the driver,
correct the assigned clock rate to 4.8GHz.
Add missing dt-bindings/include files needed for compilation of driver.
Enable compilation of the CMN PLL driver by adding the symbols to
Kconfig and Makefile.
Fixes: 468975a985ab ("qualcommax: ipq50xx: backport upstreamed patches for adding ipq5018 CMN PLL support") Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/21453 Signed-off-by: Robert Marko <robimarko@gmail.com>
Robert Senderek [Fri, 10 Oct 2025 12:40:21 +0000 (14:40 +0200)]
qualcommax: ipq50xx: Add support for Zyxel SCR50AXE
This is tri-band WiFi6E capable router. Also Zyxel Nebula managed so no real local GUI. To open device 4 screws must be located uder the label.
Four latches are on front and two on each side. Better start from ethernet port side where 3 small latches are easy to handle.
FCC shows It's identical to WSQ65 sold as Zyxel Multy M6E but that's nowhare to be found yet. WSQ65 is not covered by this PR
Speficiations:
* SoC: Qualcomm IPQ5018
* RAM: 1GB DDR3
* Flash: Winbond W25N02KWZEIR 256MB
* UART: PCB "J3" is located left from front LED strip
(VCC/TX/RX/ /GND) 3.3V 115200n8
* Wi-Fi1: IPQ5018 (2x2 2.4 Ghz 802.11b/g/n/ax)
* Wi-Fi2: QCN6102 (2x2:2 5 Ghz 802.11an/ac/ax)
* Wi-Fi3: QCN6122 (2x2:2 6 Ghz 802.11an/ac/ax)
* Ethernet: QCA8337 4xLAN 1Gbit / 1xWAN 1Gbit
* Buttons: WPS , Reset
* LEDs: 13 in total
RGB power, RGB wan, RGB status (cloud), RGB wifi, Green wps
* FCCID: I8803891
*Flash Instructions starts with getting root:
connect uart to J3 connector next to the front LEDs
go to failsafe when this shows up in log:
"Press the [f] key and hit [enter] to enter failsafe mode"
execute:
mount_root
passwd -d root
reboot
logon as root:
look for 'Please press Enter to activate this console.'
login is root password is empty
execute:
fw_setenv DebugFlag=0x1
fw_setenv bootdelay=0x2
passwd -d root
backup ubi partition "rootfs" into safe space
reboot
Jonas Jelonek [Sun, 4 Jan 2026 17:22:29 +0000 (17:22 +0000)]
realtek: pcs: rtl931x: improve port media handling
The port media handling introduced before was to some extent just taken
over from the SDK. As a second step, improve that code now. Some code
can be deduplicated, a few statements removed and improved in general.
Jonas Jelonek [Sun, 21 Dec 2025 13:45:36 +0000 (13:45 +0000)]
realtek: pcs: rtl931x: add port media handling
SFP modules still do not work that well across different devices. One
missing piece seems to be the bunch of magic values and bits set by the
SDK depending on which media is used on a port.
Take over code from the SDK for port media handling [1]. This applies
different sequences depending on whether it's 10G fiber, 1G fiber or DAC
cables to make it work best for each variant. Place the call to that
code below the configuration of a SerDes mode but before actually
activating that mode and powering on the SerDes. The SDK and our code
for RTL930x do that similarly.
Though we do not have any notion of media in pcs_config right now, do
similar to some SDK versions and set an appropriate media type for fiber
modes and SGMII (otherwise it doesn't work).
Jonas Jelonek [Sun, 21 Dec 2025 13:14:04 +0000 (13:14 +0000)]
realtek: pcs: add enum for port media
The Realtek SDK includes a lot of code around specific port media,
usually having quite some differences between 10G fiber, 1G fiber and
DAC cables. For each type, several magic values are set which in the end
usually make different kinds of links work optimal.
While there is currently no way to get that media information from the
kernel, add some fields as an enum to have a notion of different media
kinds. In additional steps, code for the subtargets can be taken over
from the SDK to handle different media.
Jonas Jelonek [Mon, 5 Jan 2026 14:52:38 +0000 (14:52 +0000)]
realtek: pcs: fix naming of RTL931X sds config data
Those config arrays still do not lineup with common conventions in the
driver in terms of naming. They are missing the driver and variant
prefix. Thus, line that up with how RTL930X code looks like.
- add 'rtpcs_' prefix since it's part of the PCS driver
- add '931x_' prefix because it's for RTL931X
- use 'cfg' instead of 'config' to shorten that a bit
Jonas Jelonek [Mon, 5 Jan 2026 14:44:41 +0000 (14:44 +0000)]
realtek: pcs: use ARRAY_SIZE kernel macro
In the RTL931X configuration code, the array size of configuration
arrays was still calculated with 'sizeof(...) / sizeof(...)'. There's a
dedicated macro in the kernel for exactly that usecase. Use that instead
to avoid possible errors and make the line shorter. The RTL930X code is
already doing it the good way.
Jonas Jelonek [Mon, 5 Jan 2026 14:07:48 +0000 (14:07 +0000)]
realtek: pcs: fix sds_config struct definition
In kernel coding style, it is highly disregarded to hide structures
behind typedefs ([1]). The PCS driver still contains a typedef for the
sds_config which was taken over from the PHY driver.
- drop the typedef, just declaring it as a struct
- give it the common 'rtpcs_' prefix
- adjust all usage locations
Jonas Jelonek [Mon, 5 Jan 2026 13:04:34 +0000 (13:04 +0000)]
realtek: pcs: add myself as module author
I have contributed quite a lot changes recently and should be made
responsible for most of the code that has been added to the PCS driver
after it has been introduced by Markus.
FWIW, add myself as another module author so anything I produced here
doesn't fall back to someone else, i.e. Markus as currently the single
module author.
Daniel Golle [Sat, 3 Jan 2026 21:05:35 +0000 (21:05 +0000)]
kernel: net: phy: c45: check validity of 10GbE LPA
Only use link-partner advertisement bits for 10GbE modes if they are
actually valid. Check LOCALOK and REMOTEOK bits and clear 10GbE modes
unless both of them are set.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Daniel Golle [Sat, 3 Jan 2026 15:41:17 +0000 (15:41 +0000)]
kernel: net: phy: realtek: replace in-band AN hack
Replace downstream hack for RealTek PHYs with a more clean solution
which could make it upstream.
As SGMII in-band AN is broken on some platforms, or simply expected to
be disabled by default in phy/sgmii mode (ie. on-board PHYs with MDIO
for out-of-band configuration and status), a hack for the RealTek PHY
driver was introduced to unconditionally disable SGMII in-band
autonegotiation.
Meanwhile the kernel has gained a proper interface for PHY and PCS to
report in-band AN capabilities and enable/disable in-band, matching
PHY and PCS capabilities.
Thanks to Bevan Weiss' knowledge about how RealTek PHY SerDes registers
are being handled in RealTek's SDK this can now be greatly improved:
- report in-band capabilties
- let phylink set in-band matching PCS and PHY capabilities
- properly abstracted indirect access of SerDes registers
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Daniel Golle [Sat, 3 Jan 2026 18:43:33 +0000 (18:43 +0000)]
kernel: net: phy: realtek: replace hack with proper fix
RealTek's 2.5G PHYs suffer from an up to now inexplicable problem which
results in the SerDes mode not being properly setup and disabling
in-band AN leading to a timeout waiting for a busy-bit to clear. Up to
now there has been a crude work-around: resetting the PHY and trying
another time.
The cause has now been found as a wrong access to register PHYCR1 on
MDIO_MMD_VEND1 instead of MDIO_MMD_VEND2 when setting up ALDPS as well
as disabling the MDIO broadcast address 0.
In order to access MDIO_MMD_VEND2 on Clause-22-only busses a custom
.read_mmd and .write_mmd ops are implemented, mapping MDIO_MMD_VEND2 to
paged access as this is required.
Also, as ALDPS by design disables the SerDes PCS of the PHY in case the
link has been down for a while, move enabling ALDPS to the end of the
config_init function to not face problems when configuring the interface
mode and in-band AN.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Felix Fietkau [Tue, 6 Jan 2026 17:46:46 +0000 (18:46 +0100)]
wifi-scripts: move the "disabled" option to the wifi-iface section
This helps for setups where the wifi interfaces are added dynamically
via procd data by avoiding automatically bringing up interfaces with
the default config. Internally, they are treated pretty much the same
by netifd.
Felix Fietkau [Sun, 4 Jan 2026 10:07:33 +0000 (10:07 +0000)]
unetmsg: add timeout for outgoing auth requests
Add a 10-second timeout for outgoing auth requests to prevent
connections from getting stuck when the remote peer goes silent
after the hello handshake but before responding to auth.
Ziyang Huang [Sun, 19 Oct 2025 09:34:53 +0000 (17:34 +0800)]
airoha: an7581: correct the pinctrl-name of phy leds
address the following issues:
[ 3.542844] mdio_bus mt7530-0: Failed to setup PHY LED pinctrl
[ 3.552550] mdio_bus mt7530-0: Failed to setup PHY LED pinctrl
[ 3.562449] mdio_bus mt7530-0: Failed to setup PHY LED pinctrl
[ 3.574350] mdio_bus mt7530-0: Failed to setup PHY LED pinctrl
There is no need to set the cpu port depending on the
given family. Remove it from the private control structure
and add the fixed value to the configuration structure.
The name of the configuration structure suggests that it
contains a list of registers. As it contains functions too
change the name according to other realtek drivers.
- "Invent" a new driver prefix "rteth"
- Rename the structure and variables to config/cfg
John Audia [Thu, 25 Dec 2025 13:31:13 +0000 (08:31 -0500)]
nat46: fix reproducible-build failure and use latest git
Bump to 2025-11-04 snapshot.
Added 100-gcc15-fix.patch which drops __DATE__/__TIME__ usage and provides
a stable fallback ("unknown"). This fixes build failures with GCC 15 and
-Werror=date-time in kernel builds.
% git log --oneline 04923c5..adb2f72 adb2f72e6fb8 get rid of spurious ubsan complaint for nat46_instance_t pairs field d5f88686a4a8 Add a test harness which boots the kernel under kvm with a custom init which runs the tests b983bab221f0 nat46-core: Fix FIXMEs about ICMPv6 parameter pointers 1aca482d6917 Add support for ignoring traffic class or TOS translation at the same time
Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/21284
[Removed "Replace printk with pr_* macros" patch] Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Valent Turkovic [Sat, 3 Jan 2026 08:50:16 +0000 (09:50 +0100)]
wifi-scripts: wdev.uc: fix mesh mode frequency handling
Mesh mode interface creation fails when the freq parameter is empty or
undefined. Unlike adhoc mode which checks if freq exists before using it,
mesh mode blindly constructs the iw command with freq parameter, resulting
in invalid syntax like:
iw dev mesh0 mesh join ssid freq NOHT
This causes the mesh interface to be created without joining the mesh
network, leaving it in a DOWN state with no channel assigned.
Fix by adding freq validation check similar to adhoc mode.
Tested on two routers in parallel as mesh peers:
- Xiaomi AX3000T (MediaTek MT7981)
- OpenWrt One (MediaTek MT7981)
- OpenWrt 6.6.119, 802.11s mesh on 5GHz (Channel 36, HE80)
This patch was cherry picked from upstream Linux because it references a
patch we backported in the fixes tag.
The function phy_id_compare_vendor() is needed by the fix.
Refresh 782-05-v6.16-net-phy-Add-support-for-Aeonsemi-AS21xxx-PHYs.patch with the upstream code.
Hauke Mehrtens [Thu, 1 Jan 2026 01:34:27 +0000 (02:34 +0100)]
kernel: move patches to backported
These formally pending patches were merged into upstream Linux some time
ago. Move them to the backports folder and add the kernel version they
were added to the file name.
Eric Fahlgren [Sun, 4 Jan 2026 00:04:51 +0000 (16:04 -0800)]
treewide: add explicit default variant part 2
Add 'DEFAULT_VARIANT' to two packages, 'iw' and 'eapol-test',
that were missed in the first pass. Refactor 'iw' and 'ethtool'
package definitions to be consistent with the pattern used in most
other packages.
Fixes: https://github.com/openwrt/openwrt/commit/f4fdb996 Fixes: https://github.com/openwrt/openwrt/commit/7a78dc4a Signed-off-by: Eric Fahlgren <ericfahlgren@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21380 Signed-off-by: Robert Marko <robimarko@gmail.com>
Jonas Jelonek [Fri, 2 Jan 2026 17:49:02 +0000 (17:49 +0000)]
realtek: pcs: rtl931x: soften early exit for USXGMII
Now that the PCS driver keeps track of how many links are registered per
SerDes, we can also decide which real hardware mode to use when USXGMII
is set. While there is still no proper setup for 10G-QXGMII or XSGMII,
the existing USXGMII 10G-SXGMII setup seems to work properly.
Soften the condition when to exit early so that single 10G port USXGMII
can be setup properly.
Jonas Jelonek [Fri, 2 Jan 2026 18:50:10 +0000 (18:50 +0000)]
realtek: pcs: select OFF mode with no links on SerDes
Because the PCS driver keeps track of the number of registered links for
each SerDes now, we now know when there is no link on a SerDes. In this
case, determine to turn off the SerDes in the mode mapper.
Though the phylink subsystem shouldn't attempt to config something
different when no link/port references a Serdes, be on the safe side.
Jonas Jelonek [Fri, 2 Jan 2026 16:30:16 +0000 (16:30 +0000)]
realtek: pcs: cover number of links per SerDes for USXGMII
A SerDes may supply multiple ports and depending on that number,
different hardware modes need to be used. While there are corresponding
modes in the kernel in some cases (e.g. USXGMII with 4 2.5G ports aka
10G-QXGMII), this doesn't always map to Realtek hardware modes. Use the
previously added link number accounting for that.
An obvious example of this is the SerDes on XGS12xx-12 switches which
is connected to an octa-PHY. This runs Realtek proprietary XSGMII mode
(10G-pumped SGMII interface) for which there is no corresponding mode
in the kernel.
projects / thirdparty / openwrt.git / log
