Pietro Monteiro [Fri, 12 Jun 2026 12:09:16 +0000 (08:09 -0400)]
algol68: Use correct library file extension on darwin and windows
Changes from v1:
- Use TARGET_MACHO and TARGET_PECOFF guards instead of __APPLE__ and
_WIN32.
-- >8 -
Darwin uses .dylib as extension for libraries. Windows uses .dll, and
sometimes doesn't prefix the library filename with "lib".
Use those extensions when opening library files to search for imports
on those OSes. Search for file with both the lib prefix and without
on Windows.
gcc/algol68/ChangeLog:
* a68-imports.cc (a68_try_suffixes): Use .dylib suffix on Darwin.
Use .dll suffix and optional lib prefix on Windows.
Signed-off-by: Pietro Monteiro <pietro@sociotechnical.xyz>
Iain Sandoe [Thu, 11 Jun 2026 19:40:51 +0000 (20:40 +0100)]
testsuite, c++: Account for missing stong symbol aliases.
Darwin does not have strong symbol aliases and therefore must emit complete
constructors (which might, or might not call others). Several tests assume
that a base constructor is emitted (which is fine for targets with strong
symbol aliases that emit the complete constructor symbol as an alias to the
base etc.).
Handle the two cases with separate matches.
gcc/testsuite/ChangeLog:
* g++.dg/modules/clone-4_b.C: Account for missing strong symbol
aliases.
* g++.dg/template/explicit-instantiation8.C: Likewise.
Tamar Christina [Fri, 12 Jun 2026 10:56:54 +0000 (11:56 +0100)]
vect: use .VARYING for early break IV [PR125597]
Similar to the mask control variable, this replaces and adds the temporary SSA
var for early break scalar IVs with an IFN_VARYING until the replacement is done
when we start vectorization.
This prevents similar issues as the mask control variable when the IV
expressions are folded.
gcc/ChangeLog:
PR tree-optimization/125597
* tree-vect-loop-manip.cc (vect_do_peeling): Create IFN_VARYING for
early break scalar IV.
* tree-vect-loop.cc (vect_update_ivs_after_vectorizer_for_early_breaks):
Replace the IFN_VARYING with actual value.
Tamar Christina [Fri, 12 Jun 2026 10:56:33 +0000 (11:56 +0100)]
vect: use .VARYING for loop iteraion mask [PR125597]
This replaces the gimple_build_nop () used for making loop control mask variable
with an IFN_VARYING and then actually adding the statement to the IL.
The bug happens because the mask def statement itself is not in the IL but
computations that use it are. As such dataflow analysis fails as it tries to
analyze the use/def chain of these expressions.
When the value if known we replace the IFN_VARYING with the final statement.
gcc/ChangeLog:
PR tree-optimization/125597
(vect_do_peeling): Create IFN_VARYING for masks.
* tree-vect-loop-manip.cc (vect_set_loop_condition): Replace the
IFN_VARYING.
gcc/testsuite/ChangeLog:
PR tree-optimization/125597
* gcc.target/aarch64/pr125597.c: New test.
Tamar Christina [Fri, 12 Jun 2026 10:55:46 +0000 (11:55 +0100)]
middle-end: introduce IFN_VARYING for temporary statements [PR125597]
This defines a new IFN "VARYING" to indicate that the operation has no current
defining statement and so things like range analysis should just not report
anything yet.
In the vectorizer we can create new SSA variables that are only defined after
vectorization is finishing. For instance the actual control statement for
masked loops.
However intermediate values need to be able to perform build expressions using
this SSA name but since GCC 16 ranger now tries to analyze these and we ICE.
This replaces the uses of gimple_nop in the definition with a value with a more
defined semantics.
This in turn means that we hit multiple times the very same insn while
iterating over all uses of r99 which in the end triggers the assert.
This patch relaxes the assert since what we want to ensure here is that
a register is not used by multiple insns since otherwise we cannot
trivially move or delete the definition.
PR rtl-optimization/125173
gcc/ChangeLog:
* ira.cc (combine_and_move_insns): Allow multiple uses within
an insn.
Andrew Pinski [Thu, 4 Jun 2026 23:09:41 +0000 (16:09 -0700)]
phiopt: Allow factoring out of more than just single operand operations
This takes https://gcc.gnu.org/pipermail/gcc-patches/2026-June/719384.html
and merge it into factor_out_conditional_operation. Also expands it to
allow for more than just unary and binary operands.
It handles as similar as what ifcvt does in factor_out_operators
but rejects some cases due to those not being profitable.
The cases which are not profitable:
* pointer plus in early with constant operand 1 (except if equal).
* division/mod with constant operand 1
* Complex expr, it would cause to lose an unitialization warning
(gcc.dg/uninit-17.c)
some cases needed to be rejected for validity (copied from ifcvt):
* BIT_FIELD_REF/BIT_INSERT_EXPR (non first operand)
* VEC_PERM_EXPR with constant operand 2
Notes on the testcase changes:
The recip-*.c testcases need to be disable phiopt since it removes
a division in some cases which causes the recip pass not to run.
slsr-12.c and slsr-34.c need to be xfailed. SLSR pass is mostly
in maintaince mode and is not getting improved.
pr122629-1.c and vect-reduc-cond-2.c are now handled in phiopt
rather than ifcvt.
cinc_common_1.c is xfailed because of missing pattern in the aarch64
backend, PR112304.
fuse_cmp_csel.c needed to be updated since the add is now after the
cmp/csel pair and ira puts the constants formation inbetween the cmp/csel.
fuse_cmp_csel-1.c is new version where there is no constant formation.
changes since v1:
* v2: Fix some comments. Add CEIL_MOD_EXPR and ROUND_MOD_EXPR to
is_divide_or_mod_p. Remove operand_equal from POINTER_PLUS case.
xfail cinc_common_1.c. Fixed up fuse_cmp_csel.c testcase.
* v3: Fix up cost model, was only calling is_factor_profitable on
the different operands when it needs to be on all operands.
* v4: Move is_divide_or_mod_p to tree.h with a rename to int_divide_or_mod_p.
Move find_different_opnum to gimple-match-exports.cc/gimple-match.h.
* tree-if-conv.cc (find_different_opnum): Move to ...
* gimple-match-exports.cc (find_different_opnum): Here.
* gimple-match.h (find_different_opnum): New decl.
* tree-ssa-phiopt.cc (is_factor_profitable): Take
gimple_match_op instead of one operand.
Rearrange the code to check the lifetime of the operands last.
(factor_out_conditional_operation): Handle operands > 1,
including operands communitive operands. Add early_p argument
for costing. Update call of is_factor_profitable.
(pass_phiopt::execute): Pass early_p to
factor_out_conditional_operation.
* tree.h (int_divide_or_mod_p): New function.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/recip-3.c: Disable phiopt since it removes
one division and recip pass needs 3.
* gcc.dg/tree-ssa/recip-5.c: Likewise.
* gcc.dg/tree-ssa/recip-6.c: Likewise.
* gcc.dg/tree-ssa/recip-7.c: Likewise.
* gcc.dg/tree-ssa/slsr-12.c: xfail.
* gcc.dg/tree-ssa/slsr-34.c: Likewise.
* gcc.dg/tree-ssa/pr122629-1.c: Update to scan phiopt1.
* gcc.dg/vect/vect-reduc-cond-2.c: Likewise.
* gcc.dg/tree-ssa/phi-factor-binary-1.c: New test.
* gcc.dg/tree-ssa/phi-factor-binary-2.c: New test.
* gcc.target/aarch64/phi-factor-binary-1.c: New test.
* gcc.target/aarch64/cinc_common_1.c: xfail.
* gcc.target/aarch64/fuse_cmp_csel.c: xfail.
* gcc.target/aarch64/fuse_cmp_csel-1.c: New test.
Co-authored-by: Kyrylo Tkachov <ktkachov@nvidia.com> Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
Align IRA and LRA when it comes to rejecting equivalences
During costing of IRA, pseudos with an equivalence are taken out of the
equation by assigning MEM to those. However, during LRA, some
equivalences are rejected which means those previously spilled pseudos
are then definitely spilled. In some cases, like for PIC, we already
know during IRA that an equivalence will be rejected during LRA.
Therefore, do not assign MEM to those pseudos during IRA which means
there is a fair chance that they get a register assigned in the end.
The attached tests are all derived from glibc. Without this patch some
pseudos are spilled resulting in stack frames just due to those spills.
With this patch, no pseudos are spilled and no unnecessary stack frames
are set up.
Note, the added conjunct in find_costs_and_classes() is basically the
negated form of the disjunct from lra_constraints()
except that IRAs reg_allocno_class() is used instead of LRAs
lra_get_allocno_class().
gcc/ChangeLog:
* ira-costs.cc (find_costs_and_classes): Do not honour equivs if
they get rejected by LRA anyway.
* ira-int.h (CONST_POOL_OK_P): Move CONST_POOL_OK_P here ...
* lra-constraints.cc (CONST_POOL_OK_P): from there.
gcc/testsuite/ChangeLog:
* gcc.target/s390/ira-pic-spill-1.c: New test.
* gcc.target/s390/ira-pic-spill-2.c: New test.
* gcc.target/s390/ira-pic-spill-3.c: New test.
Thomas Koenig [Tue, 9 Jun 2026 05:09:23 +0000 (07:09 +0200)]
Implement warnings based on variable definition and use.
This patch grew from trying to implement PR 30438 into something bigger.
This now warns about variables which were never defined, but are used
via a new option -Wundefined-vars and implements
-Wunused-but-set-variable for Fortran.
It works by keeping tabls of several things in the attributes of a
variable: If and how it has been set (via value_set), used (via
value_used), if it has been allocated (via allocated) and if a
warning has already been emitted for the symbol. This looks at
statements in a namespace only; control flow is *not* considered.
In every corner of the compiler that I could find where values are
set or used, flags are set accodingly. Updates are done if the new
use is considered to be more "important" than the old one. The
location of use or definition is also recorded, as is the place
where a variable may be allocated.
After all the flags have been correctly set (one at least hopes)
gfc_resolve then calls warn_unused_vs_set, which then iterates
over the symbols, calling find_unused_vs_set where all warnings
are emitted. I tried to be conservative here to avoid false
positives, so a whole lot of conditions are excluded (see the top
of the function).
I thought a bit on where to put -Wunused-read and -Wunused-intent-out.
While reading in a value and then not using it, or getting it from an
INTENT(OUT) argument may be dubious, people could use it for skipping
over unneeded data or because an API requires it. Hence, I feld that -Wall
would be too harsh, but I am open to discussion here.
The warn_undefined_vars_* tests are split because the testsuite would
not find warnings in certain lines even though they were issued and
I tried out ! { dg-warning ".+" } . I suspect some strangeness/bug
in gfortran.dg, but did not investigate further.
gcc/fortran/ChangeLog:
PR fortran/30438
PR fortran/28004
* dump-parse-tree.cc (gfc_debug_code_node): New function.
(show_attr): Add select_rank_temporary. Fix typo. Add referenced,
value_set, allocated and value_used.
* gfortran.h (enum value_set): New enum.
(enum value_used): New enum.
(gfc_symbol): Add value_set, value_used, allocated and
warning_emitted attributes. Rename formal_at to other_loc.
Add extra_loc.
(gfc_value_set_at): Add prototype.
(gfc_lvalue_allocated_at): Likewise.
(gfc_mark_lhs_as_used): Likewise.
(gfc_value_used_expr): Likewise.
(gfc_value_set_and_used): Likewise.
(gfc_used_in_allocate_expr): Likewise.
* interface.cc (gfc_compare_actual_formal): Mark actual arguments
according to INTENT and VALUE on formal arguments.
(gfc_procedure_use): Add VALUE_ARG/VALUE_MAYBE_USED for
implicit arguments.
* intrinsic.cc (mark_args_as_used): New function.
(init_arglist): Adjust comment.
(gfc_intrinsic_sub_interface): Use mark_args_as_used.
* invoke.texi: Document -Wundefined-vars, -Wunused-intent-out and
-Wunused-read.
* io.cc (resolve_tag_format): Mark expressions as used.
(resolve_tag): Mark as used or set, depending on tag.
(gfc_resolve_dt): Mark internal unit as set.
(gfc_resolve_inquire): Mark value as set for INQUIRE_RESOLVE_TAG macro.
* lang.opt: Add -Wundefined-vars, -Wunused-intent-out and -Wunused-read.
* lang.opt.urls: Regenerated.
* resolve.cc (resolve_function): Replace formal_at by other_loc.
(resolve_call): Likewise.
(gfc_resolve_iterator): Mark iterator variable as set and used and
other expressions as used.
(resolve_forall_iterators): Likewise.
(resolve_allocate_expr): On success, call gfc_used_in_allocate_expr
and mark value as set if source is present.
(resolve_transfer): Mark set/read according to context.
(gfc_resolve_blocks): Mark expr1 and expr2 as used.
(mark_lhs_assignments_set): Prototype / new function.
(gfc_resolve_code): Mark expr2, expr3 and expr4 as used.
(var_value_is_used): New function.
(var_value_is_set): New function.
(find_unused_vs_set): New function.
(warn_unused_vs_set): New function.
(gfc_resolve): Call warn_unused_vs_set.
* symbol.cc (gfc_value_set_at): New function.
(mark_vars_as_used): New function.
(gfc_value_used_expr): New function.
(gfc_value_set_and_used): New function.
(gfc_used_in_allocate_expr): new function.
(gfc_lvalue_allocated_at): New function.
* trans-decl.cc (gfc_finish_var_decl): If we already emitted a warning,
suppress further middle-end warning o that variable.
libgfortran/ChangeLog:
PR fortran/30438
PR fortran/28004
* mk-kinds-h.sh: Add print statement so test will compile with -Wall -Werror.
* mk-sik-inc.sh: Likewise.
* mk-srk-inc.sh: Likewise.
Iain Sandoe [Fri, 20 Oct 2023 08:57:28 +0000 (09:57 +0100)]
aarch64: Make assembler bug workaround configurable.
Some assmblers have a bug that requires +crc to be emitted even
though the base architecture supports it. However, that also
triggers a different bug in another assembler. So make the fix
configurable.
gcc/ChangeLog:
* common/config/aarch64/aarch64-common.cc: Make the asm
crc bug workaround configurable.
Iain Sandoe [Thu, 11 Jun 2026 15:31:06 +0000 (16:31 +0100)]
testsuite, c++, Darwin: Use scan-weak and scan-not-weak for portability.
In order to get this test to work on Darwin, I would need to edit pretty much
every line. We have portability helpers for weak symbol scans, let's use them.
gcc/testsuite/ChangeLog:
* g++.dg/reflect/visibility1.C: Use scan-weak/scan-not-weak to
improve portability.
Karl Meakin [Thu, 29 May 2025 11:55:34 +0000 (11:55 +0000)]
doc: Replace "fixed-point" with "integral"
In some places the documentation refers to "fixed-point" types or values
when talking about plain integer types (eg `int` or `uint32_t`).
Although this is meant to mean "the opposite of floating-point", it is
misleading and can be confused with the fractional types that are also known as
"fixed-point".
For the avoidance of doubt, refer to plain integer types and values as "integral"
throughout.
Testing done:
`make info` and `make dvi`
gcc/ChangeLog:
* doc/rtl.texi: Replace "fixed-point" with "integral" where
appropriate.
Naveen [Thu, 11 Jun 2026 13:26:23 +0000 (06:26 -0700)]
[AArch64]: Use MOVI for low‑64‑bit integer SIMD constant vectors [PR113926]
Extend AdvSIMD constant materialization to recognize 128‑bit integer vector
constants where the low 64 bits contain a duplicated scalar value and the high
64 bits are zero.
Bootstrapped and tested on aarch64-linux-gnu.
gcc/ChangeLog:
PR target/113926
* config/aarch64/aarch64.cc (struct simd_immediate_info): Add width
field to record AdvSIMD output vector width.
(simd_immediate_info::simd_immediate_info): Initialize width to zero
in all constructors.
(aarch64_simd_valid_imm): Allow 128-bit AdvSIMD MOV immediates with
zero high 64 bits to be materialized using 64-bit MOVI.
(aarch64_output_simd_imm): Use recorded immediate width when outputting
AdvSIMD immediates.
gcc/testsuite/ChangeLog:
PR target/113926
* gcc.target/aarch64/pr113926.c: New test.
* gcc.target/aarch64/pr113926_1.c: New test.
Zhongyao Chen [Wed, 14 Jan 2026 11:38:02 +0000 (11:38 +0000)]
tree-optimization - Require size > 1 for SLP reduction subgroups
The SLP reduction subgroup analysis can succeed for size-1 groups,
but this leads to poor code generation. Size-1 cases should fall
back to single-lane reduction instead.
Handle size-1 groups by returning false from the analysis function,
and add a loop exit check to avoid unnecessary processing.
PR tree-optimization/123343
gcc/ChangeLog:
* tree-vect-slp.cc (vect_analyze_slp_reduction_group): Return
false for group_size <= 1 at entry.
(vect_analyze_slp_reductions): Add loop exit check for
group_size <= 1.
Jerry DeLisle [Tue, 26 May 2026 04:13:19 +0000 (21:13 -0700)]
Fortran: [PR93727] Add EX format READ (read_ex)
Implement read_ex in libgfortran to handle EX edit-descriptor input
per Fortran 2023 13.7.2.3.6. The input field may contain:
* a hexadecimal-significand form (0X<sig>P<exp>) passed directly
to the C strtod/strtold family for exact bit-for-bit conversion;
* any form acceptable for Fw.d input (decimal fallback), including
INF and NAN representations.
For decimal input without a decimal point the d field of the EX.w.d
descriptor adjusts the exponent exactly as for Fw.d. BN/BZ blank
handling and the kP scale factor are also supported via the shared
decimal path.
Assisted by: Claude Sonnet 4.6
PR fortran/93727
libgfortran/ChangeLog:
* io/read.c (read_ex): New function implementing EX format read.
* io/io.h (read_ex): Declare.
* io/transfer.c (formatted_transfer_scalar_read): Add FMT_EX case
dispatching to read_ex.
gcc/testsuite/ChangeLog:
* gfortran.dg/EXformat_4.F90: New test covering EX format read
for kind=4 and 8 (always) and kind=10, 16 (when available):
hex-significand literals, lowercase prefix, negative binary
exponent, decimal fallback, d-field adjustment, INF/NAN, zero
field, and round-trips through write_ex.
Hongyu Wang [Wed, 3 Jun 2026 02:21:11 +0000 (07:51 +0530)]
i386: Add FMV support for avx10.2 and apxf
Add function multiversioning priority for avx10.2 and apxf features,
and add P_PROC_AVX10_2 for processors that support these, like
diamondrapids and novalake.
The priority order is:
P_AVX10_1 < P_PROC_AVX10_1 < P_AVX10_2 < P_APX_F < P_PROC_AVX10_2
gcc/ChangeLog:
* common/config/i386/i386-cpuinfo.h (enum feature_priority):
Add P_AVX10_2, P_APX_F, P_PROC_AVX10_2.
* common/config/i386/i386-isas.h: Set P_AVX10_2 for avx10.2
and P_APX_F for apxf.
* common/config/i386/i386-common.cc (processor_alias_table):
Use P_PROC_AVX10_2 for diamondrapids and novalake.
gcc/testsuite/ChangeLog:
* gcc.target/i386/mvc18.c: New test for target_clones with
avx10.2, apxf, and arch=diamondrapids/novalake.
Zhongyao Chen [Wed, 3 Jun 2026 12:44:59 +0000 (20:44 +0800)]
vect: Avoid external fallback while operand swap retry is possible
When building operand zero of a commutative BB SLP node, a failed child
discovery may build operands from scalars right away. That hides the failure
from the existing retry path, even when retrying with swapped operands could
still fix the current node.
Track the distance from operand-zero subtree discovery to the nearest upthread
swap opportunity. Skip scalar fallback only when that distance is exactly one,
so discovery reaches the retry path first.
My local tests show no regression for vect.exp, only a few for rvv.exp,
but those are reasonable, just need update test expectations.
PR tree-optimization/125567
gcc/
* tree-vect-slp.cc (least_upthread_swappable_op_distance): New.
(vect_build_slp_tree_2): Compute swap checks before building operand
zero. Skip external fallback while swap retry is possible. Reuse the
swap checks in the retry path.
gcc/testsuite/
* gcc.dg/vect/pr125567.c: New test.
Iain Sandoe [Wed, 10 Jun 2026 20:22:21 +0000 (21:22 +0100)]
testsuite, Darwin: Handle undefined symbols in pr97172-2 testcase.
Darwin's linker defaults to complaining about missing symbols, leading
to a spurious fail of this testcase. We can work around this by
allowing undefined symbols to be considered as dynamically looked-up.
gcc/testsuite/ChangeLog:
* gcc.dg/pr97172-2.c: Allow undefined symbols at link-time.
The following invalid testcases ICE in both the C and C++ FEs.
If arg is error_mark_node, TREE_TYPE works on it (and gives error_mark_node)
but TYPE_MAIN_VARIANT on it is already invalid.
The following patch fixes it in both spot by checking for error_operand_p
before that.
2026-06-10 Jakub Jelinek <jakub@redhat.com>
PR c/125694
* c-parser.cc (c_parser_postfix_expression): If arg is
error_operand_p, set error and break.
* typeck.cc (build_x_bswapg_bitreverseg ): If arg is error_operand_p,
return error_mark_node.
* c-c++-common/builtin-bswapg-5.c: New test.
* c-c++-common/builtin-bitreverseg-4.c: New test.
Reviewed-by: Joseph Myers <josmyers@redhat.com> Reviewed-by: Jason Merrill <jason@redhat.com>
Jakub Jelinek [Wed, 10 Jun 2026 20:41:48 +0000 (22:41 +0200)]
c++: Fix up __PRETTY_FUNCTION__ initializer translation [PR91155]
In r16-4399 I've added reencoding of __PRETTY_FUNCTION__ initializer
from the source character set to execution character set.
I've used cpp_translate_string for that, which unfortunately interprets
some escape sequences in the string, and as this testcase shows, those
can appear in __PRETTY_FUNCTION__ and in this case made an old bug reappear.
What didn't help is that the PR91155 testcase had a test for the exact
values but with abort calls commented out and was dg-do compile only by
default, so it actually didn't test anything.
Since then for -freflection purposes cpp_translate_string has been added,
and that doesn't interpret anything, only changes encoding (if needed).
So, the following patch just uses that new function.
2026-06-10 Jakub Jelinek <jakub@redhat.com>
PR c++/91155
* decl.cc (cp_make_fname_decl): Use cpp_translate_string instead of
cpp_interpret_string, don't prefix name strname.text with " and suffix
with " and NUL.
* g++.dg/torture/pr91155.C: Change into dg-do run test, actually test
the strings are the same.
Andrew MacLeod [Thu, 28 May 2026 14:07:02 +0000 (10:07 -0400)]
Make prange_storage::equal_p more efficient.
equal_p created a full prange from storage in order to do a comparison.
This is quite inefficient. It is better to compare just the required
fields directly from storage.
* value-range-storage.cc (prange_storage::equal_p): Compare just
the required fields.
Andrew MacLeod [Mon, 25 May 2026 20:52:31 +0000 (16:52 -0400)]
Replace class format_prange with a function.
The format_prange class is overkill for what it does. It can be replaced
with a simple function call which returns a prange_kind and the number
of words of storage required.
* value-range-storage.cc (prange_storage::alloc): Use new
prange_format function.
(prange_storage::prange_storage): Likewise.
(prange_storage::prange_format): Rename from prange_format
constructor and rework.
(prange_storage::set_prange): Use prange_format function.
(prange_storage::fits_p): Likewise.
* value-range-storage.h (enum prange_kind): Move out of
prange_storage class.
(PRANGE_STORAGE_NINTS): Likewise.
(class prange_format): remove.
(m_trailing_ints): Use PRANGE_STORAGE_NINTS.
Jerry DeLisle [Tue, 9 Jun 2026 16:46:30 +0000 (09:46 -0700)]
fortran: ICE for ASSOCIATE selector that is an overloaded intrinsic operator
Add a fallback branch in match_association_list that, for any remaining
unresolved EXPR_OP selector with BT_UNKNOWN type, calls gfc_extend_expr
to resolve the overloaded operator to its function call early, so the
associate name receives a usable type before the body is parsed. The
INTRINSIC_USER path is unchanged.
Assisted by: Claude Sonnet 4.6
PR fortran/125650
gcc/fortran/ChangeLog:
* match.cc (match_association_list): Handle ASSOCIATE selectors
that are overloaded intrinsic operator expressions by extending
them with gfc_extend_expr at parse time, so the associate name is
typed before the construct body is parsed.
Iain Sandoe [Mon, 4 May 2026 22:24:45 +0000 (23:24 +0100)]
testsuite: Make function body scans more flexible to ABI and asm syntax.
This introduces threee customisation points into the function body scans
code. This allows targets to consume regexes that are written for ABIs and
asm syntax that is reasonably compatibile with that used by the target.
The initial use-case here is to map from regexes specified in terms of
ELF syntax and Linux ABIs, but to be consumed by Darwin ABI and mach-o
binary format.
gcc/testsuite/ChangeLog:
* lib/scanasm.exp (target_regex_skip_line,
target_regex_verbatim_line, target_substitute_func_regex): New.
(check-function-bodies): use the customisation points.
(configure_check-function-bodies): Populate the new customisation
points for Darwin/Mach-O.
* lib/target-supports.exp
(add_options_for_check_function_bodies): Add Darwin criteria.
Pietro Monteiro [Tue, 9 Jun 2026 15:20:09 +0000 (11:20 -0400)]
libiberty, Darwin: Read dylibs too
The Algol 68 frontend adds a section with information on exported
modes and procedures to libraries and object files. Instead of
erroring out when encountering a Mach-O library keep reading it so the
frontend can find the exports section.
libiberty/ChangeLog:
* simple-object-mach-o.c (MACH_O_MH_DYLIB): New definition.
(simple_object_mach_o_match): Accept dylibs as well as object files.
Signed-off-by: Pietro Monteiro <pietro@sociotechnical.xyz>
Jerry DeLisle [Fri, 5 Jun 2026 17:20:36 +0000 (10:20 -0700)]
fortran: ASSOCIATE with contained-function selector rejecting type-bound calls
Two issues prevented ASSOCIATE constructs whose selector is a call to a
contained function from subsequently calling type-bound procedures on the
associate name.
When the selector is a contained function, resolving it
at parse time (before CONTAINS is fully processed) prematurely set the
function's attribute to FL_PROCEDURE/EXTERNAL, conflicting with its later
declaration as an internal procedure and giving a spurious "attribute
conflict" error.
When the first access is a generic type-bound procedure name, no candidate
type was found, and the associate name got no type, giving "no IMPLICIT type".
Now also search type-bound procedure names via gfc_find_typebound_proc; exclude vtable
types to avoid false positives.
Assisted by: Claude Sonnet 4.6
PR fortran/125530
gcc/fortran/ChangeLog:
* match.cc (gfc_match_call): Route ASSOCIATE names followed by '%'
to match_typebound_call without first resolving the selector, to
avoid prematurely marking a contained-function selector as EXTERNAL.
* symbol.cc (find_derived_types): Also search type-bound procedure
names via gfc_find_typebound_proc when inferring the type of an
inferred-type ASSOCIATE name; exclude vtable types.
gcc/testsuite/ChangeLog:
* gfortran.dg/associate_contained_func_typebound.f90: New test.
* gfortran.dg/associate_contained_func_typebound_2.f90: New
run-time test exercising generic resolution and a module-scope
selector.
tobby.li [Mon, 25 May 2026 03:55:33 +0000 (11:55 +0800)]
arm: cortex-m52 is not affected by CVE-2021-35465
The Cortex-M52 processor does not have the VLLDM erratum described
in CVE-2021-35465. Remove the quirk_vlldm feature bit from the
cortex-m52 CPU definition, so that -mfix-cmse-cve-2021-35465 is no
longer enabled by default when compiling for this CPU.
Also correct a typo in the documentation where the CVE number was
incorrectly written as CVE-2021-365465.
gcc/ChangeLog:
* config/arm/arm-cpus.in (cortex-m52): Remove quirk_vlldm.
* doc/invoke.texi: Remove cortex-m52 from the list of CPUs that
enable -mfix-cmse-cve-2021-35465 by default. Fix typo in CVE
number (CVE-2021-365465 -> CVE-2021-35465).
This patch fixes a case where POINTER attribute arrays are deep copied
when not supposed to. Namely, OpenMP states for the "firstprivate Clause":
"If an original list item has the POINTER attribute, the new list
items receive the same association status as the original list
item, as if by pointer assignment."
This creates a new langhook 'omp_array_data_privatize' to differentiate
cases in certain places during omp-low.
PR fortran/122910
gcc/fortran/ChangeLog:
* f95-lang.cc (LANG_HOOKS_OMP_ARRAY_DATA_PRIVATIZE): Define as
gfc_omp_array_data_privatize.
* trans-openmp.cc (gfc_omp_array_data_privatize): New function.
* trans.h (gfc_omp_array_data_privatize): New declaration.
Marek Polacek [Tue, 9 Jun 2026 20:50:14 +0000 (16:50 -0400)]
c++/reflection: ICE with -g on reflection of ctor param [PR125498]
Here we ICE because S::S(int) lost its DECL_ARGUMENTS, and so the
skip_artificial_parms_for in FUNCTION_FIRST_USER_PARM in write_reflection
crashes on a null tree. We've thrown away the body of S::S(int) in
cgraph_node::release_body along with its DECL_ARGUMENTS:
if (!keep_arguments)
DECL_ARGUMENTS (decl) = NULL;
This happens in finalize_compilation_unit -> analyze_functions because
there are no cgraph_node::callers (so referred_to_p() is false I think),
and .force_output is false.
We then call mangle_decl from finalize_compilation_unit ->
dwarf2out_early_finish.
Instead of FUNCTION_FIRST_USER_PARM we can use DECL_PARM_INDEX, thus
avoiding the need to either keep the body around or at least set
keep_arguments.
PR c++/125498
gcc/cp/ChangeLog:
* mangle.cc (write_reflection): Use DECL_PARM_INDEX for
computing the parameter index.
gcc/testsuite/ChangeLog:
* g++.dg/reflect/mangle7.C: New test.
* g++.dg/reflect/parameters_of9.C: New test.
Andrew Pinski [Wed, 10 Jun 2026 01:12:52 +0000 (18:12 -0700)]
ipa: Fix lifetime issue with hash_map::put in prepare_debug_expressions [PR125699]
Here the code was originally:
tree *d = m_dead_ssa_debug_equiv.get (value);
m_dead_ssa_debug_equiv.put (dead_ssa, *d);
but hash_map::put's 2nd argument is a reference.
So if the hashmap decides it needs to resize, the argument
is freed. So the fix is simple change the type of d to tree
and dereference the get. Since tree is a pointer there is not
enough data to care about the extra copy.
Jeff Law [Wed, 10 Jun 2026 13:35:14 +0000 (07:35 -0600)]
[RISC-V] Don't modify existing RTL in combined sCC splitters, generate new nodes instead
I was testing spec2017 late last week on the K3 design and stumbled across a
couple of functional fails.
In this particular case we mis-compiled omnet, thankfully in such a way that it
didn't really run at all, so time to failure was exceedingly short.
A couple months ago I extended our ability to recognize more czero sequences,
particularly in cases where we're combining the output of 2 or more sCC style
insns. I took a bit of a short-cut and adjusted the code on a node I knew
would not be shared in the IL when doing a split. I should have known better.
PUT_MODE and PUT_CODE are generally bad to use and I've called out others for
similar changes.
Consider if we're doing a 3->2 split, but when one of the two split insns do
not match. In that scenario the PUT_CODE trick is going to cause problems
because we change the IL, but the transformation as a whole isn't applied. In
this case we're inverting the mode (EQ->NE and NE->EQ), the net is we flip the
tense of a branch/sCC.
I never narrowed down a testcase. This was found by inspecting codegen and
dump differences after bisecting to a change and bisecting down to a single .o
file.
This fixes the omnet failure. There's a second cluster of failures (502.gcc)
which are unrelated and I'm still debugging those failures.
Bootstrapped and regression tested on riscv64. Of course the original patch
survived that test as well, so perhaps take it with a mountain of salt rather
than the usual grain... Waiting on pre-commit before moving forward.
* config/riscv/zicond.md (combined sCC splitters): Avoid using
PUT_MODE to change existing RTL. Instead just generate a new node.
Robert Dubner [Tue, 9 Jun 2026 20:10:00 +0000 (16:10 -0400)]
cobol: Increase the speed of COMP-3 to COMP-3 moves.
The prior method converted packed-decimal to binary, and then from
binary back to packed-decimal. These changes speed that up by moving
the unconverted bytes of the packed-decimal representations. The moves
are done directly when possible, and do a half-byte shift when
necessary.
The expansion of MOVE algorithms has led me to break out MOVE
functionality from gcc/cobol/genapi.cc to the new gcc/cobol/move.cc
file.
gcc/cobol/ChangeLog:
* Make-lang.in: Incorporate new move.cc file.
* genapi.cc (gg_attribute_bit_get): Removed.
(treeplet_fill_source): Moved.
(file_static_variable): Likewise.
(move_helper): Likewise.
(parser_initialize_programs): Use pointer without converting to
size_t.
(get_binary_value_from_float): Moved.
(gg_attribute_bit_clear): Removed.
(gg_attribute_bit_set): Removed.
(digits_to_bytes): Moved.
(get_bytes_needed): Moved.
(data_decl_type_for): Moved.
(parser_display_internal): Forward reference to move_helper.
(get_literalN_value): Moved.
(is_figconst_t): Moved.
(parser_initialize_table): Moved.
(is_figconst): Moved.
(parser_move): Moved.
(parser_move_multi): Moved.
(parser_division): Use function_address as pointer in call to
__gg__is_canceled.
(conditional_abs): Moved.
(get_reference_to_data): Moved.
(mh_identical): Moved.
(mh_source_is_literalN): Moved.
(float_type_of): Moved.
(mh_dest_is_float): Moved.
(picky_memset): Moved.
(picky_memcpy): Moved.
(mh_numeric_display): Moved.
(mh_little_endian): Moved.
(mh_source_is_group): Moved.
(mh_source_is_literalA): Moved.
(have_common_parent): Moved.
(mh_alpha_to_alpha): Moved.
* genapi.h (move_helper): New declaration.
* gengen.cc (gg_cast): Changes to someday detect aliasing
conditions.
(gg_show_type): Expand types.
(gg_indirect_i): Take a size_t parameter.
(gg_array_value): Use gg_cast() wrapper instead of fold_convert().
(gg_memchr): Likewise.
(gg_strcmp): Likewise.
(gg_strncmp): Likewise.
(gg_strlen): Likewise.
(gg_strdup): Likewise.
(gg_malloc): Likewise.
(gg_realloc): Moved.
* gengen.h (gg_indirect_i): New declaration.
* genutil.cc (get_location): Starting to look for aliasing.
(treeplet_fill_source): Moved.
(data_decl_type_for): Moved.
(attribute_bit_clear): Moved.
(attribute_bit_get): Moved.
(attribute_bit_set): Moved.
* genutil.h (treeplet_fill_source): New declaration.
(data_decl_type_for): Likewise.
(attribute_bit_clear): Likewise.
(attribute_bit_get): Likewise.
(attribute_bit_set): Likewise.
* move.cc: New file.
libgcobol/ChangeLog:
* libgcobol.cc (__gg__to_be_canceled): Use pointer instead of size_t.
(__gg__is_canceled): Likewise.
gcc/testsuite/ChangeLog:
* cobol.dg/group2/COMP-3_to_COMP-3__IN-PHASE__MOVES.cob: New test.
* cobol.dg/group2/COMP-3_to_COMP-3__IN-PHASE__MOVES.out: New test.
* cobol.dg/group2/COMP-3_to_COMP-3__OUT-OF-PHASE__MOVES.cob: New test.
* cobol.dg/group2/COMP-3_to_COMP-3__OUT-OF-PHASE__MOVES.out: New test.
Eric Botcazou [Tue, 9 Jun 2026 18:51:09 +0000 (20:51 +0200)]
Ada: Fix couple of oversights in Big_Integer package
Having too many special cases can be counter-productive as shown here.
gcc/ada/
PR ada/125695
* libgnat/s-genbig.adb ("**"): Do not drop the sign on the floor.
(Big_Exp): Take into account the parity of the exponent for -2.
Marek Polacek [Tue, 19 May 2026 23:03:33 +0000 (19:03 -0400)]
c++: recognize more aliases with lambda targs [PR125212]
This patch introduces a new TYPE_DECL flag so that dependent_opaque_alias_p
doesn't have to peruse the tree every time it's called to see if there is
a LAMBDA_EXPR, in which case the alias should be opaque. Using walk_tree
in dependent_opaque_alias_p was too expensive, and the special cases we
had there were fooled by more deeply nested lambdas.
Compiling range-v3's zip.cpp, perf stat shows:
this patch: 28.826446158 seconds time elapsed
trunk: 29.425441889 seconds time elapsed
so this patch makes the situation marginally better.
* cp-tree.h (TYPE_DECL_OPAQUE_ALIAS_P): Define.
(any_lambdas_p): Declare.
* decl.cc (grokdeclarator): Set TYPE_DECL_OPAQUE_ALIAS_P.
* pt.cc (dependent_opaque_alias_p): Refine to check
TYPE_DECL_OPAQUE_ALIAS_P.
(tsubst_decl) <case TYPE_DECL>: Set TYPE_DECL_OPAQUE_ALIAS_P.
(any_lambdas_p): New, factored out of...
(regenerate_decl_from_template): ...this. Call it.
gcc/testsuite/ChangeLog:
* g++.dg/cpp26/lambda-targ1.C: New test.
* g++.dg/cpp2a/lambda-targ26.C: New test.
* g++.dg/cpp2a/lambda-targ27.C: New test.
* g++.dg/cpp2a/lambda-targ28.C: New test.
* g++.dg/cpp2a/lambda-targ29.C: New test.
* g++.dg/cpp2a/lambda-targ30.C: New test.
* g++.dg/cpp2a/lambda-targ31.C: New test.
* g++.dg/cpp2a/lambda-targ32.C: New test.
Uros Bizjak [Tue, 9 Jun 2026 14:48:56 +0000 (16:48 +0200)]
i386: Always emit MOVSBL instead of MOVSBW [PR125636]
Use MOVSBL instead of MOVSBW for QImode-to-HImode sign extension to avoid
a 16-bit partial register write and to eliminate 0x66 operand size prefix.
PR target/125636
gcc/ChangeLog:
* config/i386/i386.md (extendqihi2): Use movsbl instead of movsbw.
Adjust the destination operand to use %k0 and update the mode
attribute accordingly.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr89954.c: Update assembler scan
directives to expect movsbl instead of movsbw.
Ciprian Arbone [Tue, 9 Jun 2026 15:31:11 +0000 (16:31 +0100)]
ARM: Fix broken Thumb1 CBZ cc tracking [PR124077]
thumb1_cbz uses operands[2], both when checking if it can reuse the
previously set condition code, and when recording the operands that set
the current condition code. operands[2] for this pattern is the target
label of the jump though, and not the intended second operand of the
comparison operator.
As the label is unlikely to end up as operands[2], the condition code
reuse logic doesn't kick in and causes the redundant CMP instruction
described in PR124077. In addition, thumb1_final_prescan_insn also
doesn't treat thumb1_cbz as a cbranch and ends up resetting condition
code tracking state.
Fix by replacing operands[2] with the actual second operand of the
pattern i.e const0_rtx. Also treat thumb1_cbz the same as
cbranchsi4_insn in thumb1_final_prescan_insn and let it track condition
code state itself.
gcc/ChangeLog:
PR target/124077
* config/arm/arm.cc (thumb1_final_prescan_insn): Also skip
condition code update for thumb1_cbz instructions.
* config/arm/thumb1.md (thumb1_cbz): Use const0_rtx as the
recorded cc_op1 instead of operands[2].
gcc/testsuite/ChangeLog:
PR target/124077
* gcc.target/arm/pr124077.c: New test.
[PATCH v3 2/9] RISC-V: Track altfmt in RVV vtype state
Zvfofp8min instructions use the VTYPE altfmt field to select the
alternate FP8 format. Track altfmt in vsetvl_info so the vsetvl pass
does not merge or remove configurations that require different altfmt
values.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (enum altfmt_type): New.
* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl): Pass
ALTFMT_NONE to gen_vsetvl.
(gen_no_side_effects_vsetvl_rtx): Pass ALTFMT_NONE to
gen_vsetvl_no_side_effects.
* config/riscv/riscv-vector-builtins-bases.cc: Include insn-attr.h.
(vsetvl::expand): Pass ALTFMT_NONE to gen_vsetvl_no_side_effects.
* config/riscv/riscv-vsetvl.cc (altfmt_to_str): New function.
(get_altfmt): New function.
(demand_flags): Add DEMAND_ALTFMT_P.
(altfmt_demand_type): New enum.
(vsetvl_info): Track altfmt.
(demand_system): Add altfmt compatibility, availability, and merge handling.
* config/riscv/riscv-vsetvl.def: Add altfmt rules.
* config/riscv/vector.md (altfmt): New attribute, numeric with
INVALID_ATTRIBUTE default.
(@vsetvl<mode>, vsetvl_vtype_change_only,
@vsetvl_discard_result<mode>, @vsetvl<mode>_no_side_effects,
*vsetvldi_no_side_effects_si_extend): Add altfmt operand.
Wilco Dijkstra [Thu, 4 Jun 2026 14:47:23 +0000 (14:47 +0000)]
AArch64: Avoid zeroing movprfx on MOV/FMOV
A zeroing movprfx with merging MOV/FMOV should be avoided since they result in a
read of the destination register - this introduces extra dependencies eventhough
the read has no useful effect. Remove such patterns so that the zero value is
created via MOV d0, 0. Update various tests.
gcc:
* config/aarch64/aarch64-sve.md: Remove zeroing movprfx of merging MOV
causing the duplication of a 2-element vector ((float16) x0, 0) into z0.
This is a copy-paste error from the original combine_internal patterns,
where UZP1 always operates on vectors of 2 elements, in which circumstance
it is equivalent to ZIP1. For smaller element sizes (and thus higher
element counts) only ZIP1 is correct.
The fix is to emit ZIP1 when concatenating values on vector registers.
For consistency, I've changed the original combine_internal patterns as
well as the ones added in r17-898-g920eeb67a3537b. Since this latter
change has nothing to do with the PR, it could have been better to split
the patch in two; I'd be happy to do that if necessary.
Both aforementioned changes required adjusting existing AdvSIMD/SVE
vec_init-related testcases; I've added pr125550.c from the PR on top of
that as well.
Bootstrapped and regtested on aarch64-linux-gnu.
PR target/125550
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
(*aarch64_combine_internal<mode>): Use zip1 instead of uzp1
to concatenate values residing in SIMD registers.
(*aarch64_combine_internal_be<mode>): Likewise.
JRobinNTA [Tue, 9 Jun 2026 12:58:14 +0000 (06:58 -0600)]
[PATCH] RISC-V: Fix static rounding mode splicing for xtheadvector [PR125395]
When generating assembly for T-Head vector float conversions,
the backend used hardcoded pointer math that failed to account
for static rounding mode suffixes (e.g., .rtz). Additionally,
intercept blocks for VFCVT and VFWCVT were entirely missing,
allowing illegal static rounding modes to leak into the assembler.
This patch adds the missing conversion blocks and introduces
an offset calculation to safely bypass the mnemonic regardless
of standard RVV rounding suffixes.
PR target/125395
gcc/ChangeLog:
* config/riscv/thead.cc (th_asm_output_opcode): Add VFCVT
and VFWCVT blocks. Add offset logic for static rounding suffixes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/pr125395.c: New test.
Alex Coplan [Fri, 5 Jun 2026 15:51:47 +0000 (16:51 +0100)]
expmed: Fix up CONST_POLY_INT case of make_tree [PR125621]
The PR showed us ICEing in build_poly_int_cst because we have type set
to a non-type tree node (a var_decl). A closer look shows this is
because we pass the wrong variable to wide_int_to_tree in
expmed.cc:make_tree: we pass t instead of type, where t is
uninitialized at the point of the call. Fixed thusly.
I also took the opportunity to move the CONST_POLY_INT case out of the
default: section into its own case of the switch.
gcc/ChangeLog:
PR middle-end/125621
* expmed.cc (make_tree): Fix CONST_POLY_INT case to pass type
instead of t, move it to its own switch case.
gcc/testsuite/ChangeLog:
PR middle-end/125621
* gcc.target/aarch64/torture/pr125621.c: New test.
Monk Chiang [Tue, 9 Jun 2026 12:51:43 +0000 (06:51 -0600)]
[PATCH v2] RISC-V: Add load-to-address bypass for SiFive-7 series
The SiFive-7 series processors have a dual-pipeline architecture with
load latency of 3 cycles. However, when a load instruction produces
an address register that is used immediately by a subsequent load or
store with zero offset, the address can be forwarded after 2 cycles
instead of 3. This reduces pipeline stalls for common address
calculation patterns like:
ld a0, 0(a1) # Load pointer, 3-cycle latency
ld a2, 0(a0) # Use as address with zero offset, bypass to 2 cycles
Changes in v2:
- Fix sifive-7-load-address-bypass test for rv32 targets.
gcc/
* config/riscv/riscv-protos.h (riscv_zero_offset_address_bypass_p):
New function.
* config/riscv/riscv.cc (riscv_zero_offset_address_bypass_p): New
function.
* config/riscv/sifive-7.md: Add bypass definition.
gcc/testsuite/
* gcc.target/riscv/sifive-7-load-address-bypass.c: New test.
The optimization removes the redundant LUI instruction, uses only two
registers (t2, t3), and adds a nop for proper 8-byte alignment to avoid
-Wpadded warnings.
Changes in v2:
- Fix zicfilp-trampoline test for Linux targets.
- Fix line length exceeding 80 characters.
gcc/
* config/riscv/riscv.cc (riscv_trampoline_init): Remove redundant
LUI instruction.
gcc/testsuite/
* gcc.target/riscv/zicfilp-trampoline.c: New test.
Change the diagnostic for the ambiguity check for 'omp declare reduction'
to actually output the reduction operator/idenfier and the type to which
this reduction applies to.
Xi Ruoyao [Fri, 5 Jun 2026 08:29:20 +0000 (16:29 +0800)]
hard-reg-set: make temporary SET for EXECUTE_IF_SET_IN_HARD_REG_SET a build-time error
So we don't make the same error again.
gcc/
PR rtl-optimization/125609
PR middle-end/122992
* hard-reg-set.h
(build_error_on_rvalue): New function.
(EXECUTE_IF_SET_IN_HARD_REG_SET): Call the function above.
Currently, USM is only supported if all AMD GPUs support USM; hence,
on a mixed system (e.g. CPU with GPU of type APU plus separate, discrete
GPU not supporting USM/SVM), host fallback always happens.
Workaround is to use ROCR_VISIBLE_DEVICES. Additionally, the
"not-supported" wording should refer here to USM/SVM support not
to XNACK, which has been clarified here.
Paul Thomas [Mon, 8 Jun 2026 11:20:40 +0000 (12:20 +0100)]
Fortran: [PDT] Prevent unnecessary mallocs and frees. [PR125669]
2026-06-07 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran
PR fortran/125669
* decl.cc (gfc_get_pdt_instance): If the bound expressions for
and array component, of the length expression for a character
component, gave simplified to a constant, do not set attributes
pdt_array and pdt_string respectively.
gcc/testsuite/
PR fortran/125669
* gfortran.dg/pdt_92.f03: New test.
Jeevitha [Tue, 9 Jun 2026 02:39:54 +0000 (21:39 -0500)]
rs6000: Add Future ISA compare and swap equal AMO operations [RFC02689]
This patch adds support for compare-and-swap-equal atomic memory
operations that may be added to a future PowerPC processor. Note that
the names of these functions may change in the future.
Add _AMO_LD_CS_EQ to the _AMO_LD enum and define four new
compare-and-swap equal helper functions, all guarded by _ARCH_FUTURE.
For non-Future targets, provide error-attribute stubs to emit a
compile-time diagnostic.
a68: fix diagnostic strings in a68_attr_format_token
The a68_attr_format_token class is incorrectly using
a68_find_keyword_from_attribute to get the diagnostic message, rather
than the intended descriptive text for the attribute.
This patch fixes this and adds a little testcase.
Signed-off-by: Jose E. Marchesi <jemarch@gnu.org>
gcc/algol68/ChangeLog
* a68-pretty-print.h (a68_attr_format_token): Get diagnostic
string from a68_attribute_name.
gcc/testsuite/ChangeLog
* algol68/compile/error-attr-format-token-1.a68: New test.
* doc/tm.texi.in: Ditto. And standardize on "option" over
"flag".
(strategy): Ditto. And standardize on "option" over "switch"
and fix grammar.
* target.def: Ditto.
* doc/tm.texi: Regenerate.
Jakub Jelinek [Mon, 8 Jun 2026 19:38:17 +0000 (21:38 +0200)]
c++: Add various missing auto_diagnostic_group sentinels
I've grepped for inform with larger grep context and looked for missing
auto_diagnostic_group if the inform was preceded by some related diagnostic
function (or call which emits that).
Jakub Jelinek [Mon, 8 Jun 2026 19:36:24 +0000 (21:36 +0200)]
c: Fix up ICE with __builtin_{bswap,bitreverse}g [PR125629]
The following testcase ICEs, because we never call c_fully_fold on the
argument.
Fixed by calling it before calling fold_build_builtin_bswapg_bitreverseg
which creates the builtin or IFN calls.
2026-06-08 Jakub Jelinek <jakub@redhat.com>
PR c/125629
* c-parser.cc (c_parser_postfix_expression) <case RID_BUILTIN_BSWAPG>:
Call c_fully_fold on the argument before calling
fold_build_builtin_bswapg_bitreverseg.
* c-c++-common/builtin-bswapg-4.c: New test.
* c-c++-common/builtin-bitreverseg-3.c: New test.
Alfie Richards [Fri, 6 Feb 2026 12:40:29 +0000 (12:40 +0000)]
aarch64: Add support for range prefetch intrinsic.
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.cc (enum aarch64_builtins):
Add AARCH64_PREFETCH_PLD_RANGE and AARCH64_PREFETCH_PLDX_RANGE.
(aarch64_init_prefetch_builtins): Add initialization of
__pld_range and __pldx_range.
(require_const_argument): Update to return the minval if value
is out of range.
(aarch64_expand_prefetch_range_builtin): New function.
(aarch64_general_expand_builtin): Add support for
AARCH64_PREFETCH_PLD_RANGE and AARCH64_PREFETCH_PLDX_RANGE.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Add
__ARM_PREFETCH_RANGE macro.
* config/aarch64/aarch64.md (unspec): Add UNSPEC_PLDX_RANGE and
UNSPEC_PLD_RANGE
(aarch64_rprfm): New instruction.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/acle/rprfm.c: New test.
* gcc.target/aarch64/acle/rprfm_error.c: New test.
* gcc.target/aarch64/acle/fprcvt.c: New test.
* gcc.target/aarch64/fprcvt.c: New test.
* gcc.target/aarch64/fprcvt.x: New test.
* gcc.target/aarch64/fprcvt_float32_int32.c: New test.
* gcc.target/aarch64/fprcvt_float32_int64.c: New test.
* gcc.target/aarch64/fprcvt_float32_uint32.c: New test.
* gcc.target/aarch64/fprcvt_float32_uint64.c: New test.
* gcc.target/aarch64/fprcvt_float64_int32.c: New test.
* gcc.target/aarch64/fprcvt_float64_int64.c: New test.
* gcc.target/aarch64/fprcvt_float64_uint32.c: New test.
* gcc.target/aarch64/fprcvt_float64_uint64.c: New test.
Richard Biener [Mon, 8 Jun 2026 12:02:38 +0000 (14:02 +0200)]
tree-optimization/125668 - missed alignment updating from forwprop
With the PR125296 fix I forgot to handle the LHS propagation case.
PR tree-optimization/125668
* tree-ssa-forwprop.cc (forward_propagate_addr_expr_1):
Preserve alignment of the original access also for propagating
into the LHS.
Richard Biener [Mon, 8 Jun 2026 08:50:35 +0000 (10:50 +0200)]
tree-optimization/125652 - wrong code with SCEV
The following fixes a latent issue in chrec_fold_plus_poly_poly
which suffers from being prone to signed overflow UB in the way
it associates additions when accumulating two polynomical CHRECs.
Similar to r16-2781-gafafae097232e7 the following catches the
obvious cases when constants are involved without trying to address
the actual underlying issue.
Richard Biener [Mon, 8 Jun 2026 07:41:25 +0000 (09:41 +0200)]
tree-optimization/125646 - fixup vector types for const mult pattern
When we pattern recognize integer multiplication with a constant
and need a conversion to unsigned we fail to set the appropriate
unsigned vector type on the pattern stmt so it gets the vector
type of the signed result. This confuses code dealing with UB
for reduction vectorization but will also result in wrong-code
in the non-reduction case.
PR tree-optimization/125646
* tree-vect-patterns.cc (vect_synth_mult_by_constant): Assign
vector type to the pattern def sequence stmts.
PR rtl-optimization/122992
* config/m68k/m68k.cc (m68k_conditional_register_usage): Fix
signedness of register number var.
(m68k_zero_call_used_regs): Fix missing declaration.
Optab instruction conditions are cached and so won't adapt to the
current phase of compilation.
The old code to FAIL for !create_pseudo_p was redundant since
general-purpose arithmetic optabs like bswap can only be used
while can_create_pseudo_p is true.
Xi Ruoyao [Sun, 7 Jun 2026 06:34:26 +0000 (14:34 +0800)]
mips: fix unintialized operand use in sync_{old,new}_<optab>_12
In GCC, if the RTL template of define_insn has multiple elements, it's
treated as a parallel expression. And, "in parallel" means that first
all the values used in the invidiviual side-effects are computed, and
second all the actual side-effects are performed. So when the value of
operand 1 (the output reg) is used, it's not set yet.
When optimization is enabled, the uninitialized value is replaced with 0
and then for e.g. if atomic_hiqi_op is plus, (plus (0) (val)) is folded
to simply (val). Now the RTL template happens to be matched by
sync_old_nand_12 (of which the RTL is written in a really inconsistent
way), causing "0 + 1 = -1".
So fix the uninitialized operand use, i.e. (match_dup 0) should be
(match_dup 1). Also slightly alter the source of the set for the memory
in sync_new_<optab>_12 to make it clear the value in the reg and in the
memory should be same after the operation.
gcc/
* config/mips/sync.md (sync_old_<optab><mode>): Fix
uninitialized operand use.
(sync_new_<optab><mode>): Fix uninitialized operand use, use the
same expression for the set source of operand 0 and 1.
projects / thirdparty / gcc.git / log
