Kewen Lin [Fri, 1 May 2026 13:50:57 +0000 (13:50 +0000)]
i386: Adjust some c86-4g*.md modeling to reduce build time
Commit r17-203 caused significant increase in GCC build time
on several environments as folks reported, mainly due to
excessively long execution time of genautomata.
As Alexander pointed out, the current division modeling in
c86-4g*.md can cause a combinatorial explosion in the
automaton, that further leads to significant build time
increase.
Following Alexander's suggestion, this patch introduces the
dedicated automatons and cpu_units for idiv and fdiv, uses
them to updates the integer, floating point division and
square root modeling for now. Some evaluated statistics
are listed below.
With r17-202:
*Tested stage-1 i686 build -j 32: 255 seconds*
$ nm -CS -t d --defined-only gcc/insn-automata.o \
| sed 's/^[0-9]* 0*//' \
| sort -n | tail -20
13896 r slm_transitions
15360 r znver4_fp_store_transitions
16760 r znver4_ieu_transitions
17776 r bdver1_ieu_transitions
20068 r bdver1_fp_check
20068 r bdver1_fp_transitions
20983 t internal_state_transition(int, DFA_chip*)
22270 t internal_min_issue_delay(int, DFA_chip*)
26208 r slm_min_issue_delay
27244 r bdver1_fp_min_issue_delay
28518 r glm_check
28518 r glm_transitions
33690 r geode_min_issue_delay
45436 r znver4_fpu_min_issue_delay
46980 r bdver3_fp_min_issue_delay
49428 r glm_min_issue_delay
53730 r btver2_fp_min_issue_delay
53760 r znver1_fp_transitions
93960 r bdver3_fp_transitions
181744 r znver4_fpu_transitions
With culprit commit r17-203:
*Tested stage-1 i686 build -j 32: 949 seconds*
$ nm -CS -t d --defined-only gcc/insn-automata.o \
| sed 's/^[0-9]* 0*//' \
| sort -n | tail -20
28518 r glm_check
28518 r glm_transitions
33690 r geode_min_issue_delay
45436 r znver4_fpu_min_issue_delay
46980 r bdver3_fp_min_issue_delay
49428 r glm_min_issue_delay
53730 r btver2_fp_min_issue_delay
53760 r znver1_fp_transitions
68160 r c86_4g_ieu_min_issue_delay
93960 r bdver3_fp_transitions
110080 r c86_4g_fp_min_issue_delay
136320 r c86_4g_ieu_transitions
181744 r znver4_fpu_transitions
220160 r c86_4g_fp_transitions
262988 r c86_4g_m7_fpu_base
475225 r c86_4g_m7_ieu_min_issue_delay
950450 r c86_4g_m7_ieu_transitions 4010567 r c86_4g_m7_fpu_min_issue_delay 5496908 r c86_4g_m7_fpu_check 5496908 r c86_4g_m7_fpu_transitions
With this patch:
*Tested stage-1 i686 build -j 32: 257 seconds*
$ nm -CS -t d --defined-only gcc/insn-automata.o \
| sed 's/^[0-9]* 0*//' \
| sort -n | tail -20
20068 r bdver1_fp_transitions
22354 r c86_4g_m7_ieu_min_issue_delay
25705 t internal_state_transition(int, DFA_chip*)
26208 r slm_min_issue_delay
27164 t internal_min_issue_delay(int, DFA_chip*)
27244 r bdver1_fp_min_issue_delay
28518 r glm_check
28518 r glm_transitions
33690 r geode_min_issue_delay
33728 r c86_4g_fp_transitions
45436 r znver4_fpu_min_issue_delay
46980 r bdver3_fp_min_issue_delay
49428 r glm_min_issue_delay
53730 r btver2_fp_min_issue_delay
53760 r znver1_fp_transitions
89414 r c86_4g_m7_ieu_transitions
93960 r bdver3_fp_transitions
181744 r znver4_fpu_transitions
326322 r c86_4g_m7_fpu_min_issue_delay 1305288 r c86_4g_m7_fpu_transitions
I noticed the number of c86_4g_m7_fpu_transitions is still
large, but this patch can address the build time issue.
To avoid impacting folks' daily builds and regular testings,
I'd like to land this patch first if possible. We can then further
refine the c86-4g modeling and investigate large transition
count as part of the follow-up work, even potentially part
of PR 87832.
Michiel Derhaeg [Fri, 1 May 2026 13:41:54 +0000 (07:41 -0600)]
[PATCH v2] RISC-V: Add Synopsys RMX-100 series pipeline description.
This patch introduces the pipeline description for the Synopsys RMX-100 series
processor to the RISC-V GCC backend. The RMX-100 has a short, three-stage,
in-order execution pipeline with configurable multiply unit options.
The option -mmpy-option was added to control which version of the MPY unit the
core has and what the latency of multiply instructions should be similar to
ARCv2 cores (see gcc/config/arc/arc.opt:60).
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add arc-v-rmx-100-series.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
Add arcv_rmx100.
(enum arcv_mpy_option_enum): New enum for ARC-V multiply options.
* config/riscv/riscv-protos.h (arcv_mpy_1c_bypass_p): New declaration.
(arcv_mpy_2c_bypass_p): New declaration.
(arcv_mpy_10c_bypass_p): New declaration.
* config/riscv/riscv.cc (arcv_mpy_1c_bypass_p): New function.
(arcv_mpy_2c_bypass_p): New function.
(arcv_mpy_10c_bypass_p): New function.
* config/riscv/riscv.md: Add arcv_rmx100.
* config/riscv/riscv.opt: New option for RMX-100 multiply unit
configuration.
* doc/riscv-mtune.texi: Document arc-v-rmx-100-series.
* config/riscv/arcv-rmx100.md: New file.
Michiel Derhaeg [Fri, 1 May 2026 13:35:43 +0000 (07:35 -0600)]
[PATCH v2] RISC-V: Add Synopsys RHX-100 series pipeline description
This patch introduces the pipeline description for the Synopsys RHX-100 series
processor to the RISC-V GCC backend. The RHX-100 features a 10-stage,
dual-issue, in-order execution pipeline architecture.
It has support for instruction fusion, which will be addressed by subsequent
patches. Due to fusion, up to four instructions can be issued in a single
cycle. It is modeled as four separate pipelines and the issue_rate is set to
four.
Philipp Tomsich [Fri, 1 May 2026 13:32:17 +0000 (07:32 -0600)]
[PATCH GCC17-stage1] riscv: Optimize power-of-2 boundary comparisons in conditional moves
In riscv_expand_conditional_move, detect unsigned comparisons against
power-of-2 boundaries and convert them to shift-based equality tests.
This avoids materializing large constants (e.g. 2^56 - 1) that may
require multiple instructions (bseti + sltu), replacing them with a
single srli that feeds directly into czero.eqz/czero.nez.
The transformation handles four cases:
GTU x, (2^N-1) -> NE (x >> N), 0
LEU x, (2^N-1) -> EQ (x >> N), 0
GEU x, 2^N -> NE (x >> N), 0
LTU x, 2^N -> EQ (x >> N), 0
For example, `(a & (0xff << 56)) ? b : 0` previously generated:
bseti a5, zero, 56
sltu a0, a0, a5
czero.nez a0, a1, a0
Now generates:
srli a0, a0, 56
czero.eqz a0, a1, a0
Existing define_split patterns in riscv.md (lines 3727-3748) handle
the same optimization for standalone SCC operations, but they don't
fire in the conditional move expansion path which goes through
riscv_expand_int_scc directly.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_conditional_move):
Convert unsigned comparisons against power-of-2 boundaries
to shift-based equality tests.
Marek Polacek [Wed, 29 Apr 2026 21:24:19 +0000 (17:24 -0400)]
c++/reflection: propagate cv-quals for SPLICE_SCOPE [PR125096]
tsubst_splice_scope isn't propagating cv-quals from the template tree
to the result, which means wrongly failed asserts in the new test due to
a missing 'const'. So let's add the cv-quals like we do in so many
other places in tsubst.
PR c++/125096
gcc/cp/ChangeLog:
* pt.cc (tsubst_splice_scope): Don't return early for
dependent_splice_p. Propagate cv-qualifiers from the
SPLICE_SCOPE to the result.
* reflect.cc (valid_splice_scope_p): Accept SPLICE_SCOPE.
gcc/testsuite/ChangeLog:
* g++.dg/reflect/mangle4.C: Move dg-error.
* g++.dg/reflect/dep16.C: New test.
Rainer Orth [Fri, 1 May 2026 13:18:04 +0000 (15:18 +0200)]
build: Check solaris_{as,ld} where appropriate
Several of the gas and gnu_ld checks in gcc/configure actually need to
determine if Solaris as and ld are in use. Since solaris_as and
solaris_ld are determined reliably now, it's clearer to check them
directly instead of !gas and !gnu_ld.
This patch does just that. Since solaris_as/solaris_ld imply target
*-*-solaris2*, the tests can be simplified and sometimes converted from
case/esac to if/else.
Bootstrapped on amd64-pc-solaris2.11, sparcv9-sun-solaris2.11,
x86_64-pc-linux-gnu, amd64-pc-freebsd15.0, and
x86_64-apple-darwin21.6.0.
When there are different flavours of as and/or ld depending on PATH
(/usr/bin/as vs. /usr/gnu/bin/as resp. ld on Solaris, /usr/bin/ld, LLD,
and /usr/local/bin/ld, GNU ld on FreeBSD), the builds were configured
with --with-as/--with-ld.
The Solaris tests were run for as/ld, gas/ld, and gas/gld
configurations, the FreeBSD tests with gas/gld.
In all cases, gcc/auto-host.h and gcc/Makefile were unchanged.
Jin Ma [Fri, 1 May 2026 13:06:01 +0000 (07:06 -0600)]
[PATCH] RISC-V: Fix missing braces in riscv_rtx_costs for slli.uw pattern [PR???]
The AND case in riscv_rtx_costs for the slli.uw pattern (zba extension) has a
multi-statement if body without braces. This causes the 'return true' to
execute unconditionally whenever the left operand of AND is an ASHIFT,
regardless of whether the inner condition (checking register_operand,
CONST_INT_P, and the 0xffffffff mask) is satisfied.
This effectively short-circuits the entire AND cost calculation for any
AND+ASHIFT combination when TARGET_ZBA && TARGET_64BIT && DImode,
skipping subsequent pattern checks (bclri, bclr, etc.) and the
fallthrough to PLUS/MINUS.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs): Add missing braces
around the if body for the slli.uw pattern in the AND case.
Jakub Jelinek [Fri, 1 May 2026 12:54:35 +0000 (14:54 +0200)]
strlen: Adjust objsz arg in __strcat_chk -> __stpcpy_chk transformation [PR125079]
As the following testcase shows, we have two different transformations
of __strcat_chk. One done in strlen_pass::handle_builtin_strcat,
which transforms __strcat_chk (x, y, z) if we know beforehand strlen (x),
so something like:
l = strlen (x);
__strcat_chk (x, y, z);
and since PR87672 we change that to
l = strlen (x);
__strcpy_chk (x + l, y, z - l);
i.e. decrease the objsz in
if (objsz)
{
objsz = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (objsz), objsz,
fold_convert_loc (loc, TREE_TYPE (objsz),
unshare_expr (dstlen)));
objsz = force_gimple_operand_gsi (&m_gsi, objsz, true, NULL_TREE, true,
GSI_SAME_STMT);
}
And another transformation is when we have earlier __strcat_chk (x, y, z)
call and want to compute strlen (x) after that. In that case
get_string_length transforms
__strcat_chk (x, y, z);
to
t = strlen (x);
l = __stpcpy_chk (x + t, y, z) - x;
where l is the len we are looking for. This patch changes it similarly to
the PR87672 to
t = strlen (x);
l = __stpcpy_chk (x + t, y, z - t) - x;
instead.
2026-05-01 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/125079
* tree-ssa-strlen.cc (get_string_length): Transform
__strcat_chk (x, y, z) when we need strlen (x) afterwards into
l1 = strlen (x); l = __stpcpy_chk (x + l1, y, z - l1) - x;
where l is the strlen (x), instead of using z as last __stpcpy_chk
argument.
Jeff Law [Fri, 1 May 2026 12:47:07 +0000 (06:47 -0600)]
[PR target/124559][RISC-V] Improve RISC-V constant synthesis for some HImode constants
So this is a trivial little bug we found doing some comparisons against LLVM.
For the function sub2 in load-immediate.c we get this code:
li a5,-32768
sh a5,0(a0)
xori a5,a5,-1
sh a5,0(a1)
Note carefully that li+xori. There's a slightly better sequence here from an
encoding standpoint. Instead of using xori we can adjust the synthesis
sequence to target an "addi" for that statement and in doing so we can save two
code bytes of space.
The xori sequence was used because we can't do this in gcc:
(set (dest:HI) (const_int 0x8000))
We're in HI mode so the constant must be sign extended from bit 15 to a
HOST_WIDE_INT.
Fixing this isn't hard. The key is realizing the vast majority of the time we
really don't want/need to load in HImode and in fact we're typically going to
be generating objects in word_mode. So instead of passing in the pre-promoted
mode, pass in the post-promoted mode.
That's fine and good with one caveat. CSE fails to use NEG/NOT to derive a
new constant from an older constant, even if the cost is smaller, which caused
a code quality regression elsewhere on the RISC-V port. So this patch adjusts
CSE ever-so-slightly to allow it to derive constants from a previous constant
using NOT/NEG in a fairly obvious way.
This has been in my tester for a while, so it's been through the usual
bootstrap & regression test on the Pioneer, BPI, x86 and aarch64 and others as
well as testing across the various embedded targets.
Waiting on pre-commit testing to do its thing.
PR target/124559
gcc/
* config/riscv/riscv-protos.h (riscv_move_integer): Drop mode argument.
* config/riscv/riscv.cc (riscv_move_integer): Pass mode after promotions
to riscv_build_integer. All callers changed.
* config/riscv/riscv.md: Corresponding changes.
* cse.cc (cse_insn): Try to derive one constant from another using NOT/NEG.
Jonathan Wakely [Fri, 1 May 2026 09:58:57 +0000 (10:58 +0100)]
libstdc++: Tweak Doxygen comments for experimental simd
I noticed that Doxygen was not documenting the contents of
<experimental/simd> as part of namespace std, because it didn't know
about the _GLIBCXX_SIMD_BEGIN_NAMESPACE and _GLIBCXX_SIMD_END_NAMESPACE
macros which open and close namespace std::experimental::parallelism_v2.
After defining those macros in the Doxygen config, the Doxygen comments
in experimental/bits/simd.h were causing namespace std to be documented
as part of the Parallelism TS v2. That's because the preprocessed code
looks like:
This causes Doxygen to apply the @ingroup command to all three of
namespace std, namespace std::experimental, and namespace
std::experimental::parallelism_v2. I don't know if this is the intended
behaviour, but it doesn't seem useful so I've opened an issue about it:
https://github.com/doxygen/doxygen/issues/12114
To workaround this, we can move the _GLIBCXX_SIMD_BEGIN_NAMESPACE macro
before the @{ group and document it separately with a @namespace
comment. That makes the @ingroup only apply to the namespace named by
the @namespace command, not to its enclosing namespaces as well. Moving
the position of the BEGIN macro also fixes the nesting, as previously we
had @{ then BEGIN then @} then END. Now we have BEGIN @{ @} END which
seems preferable.
libstdc++-v3/ChangeLog:
* doc/doxygen/user.cfg.in (PREDEFINED): Add BEGIN/END macros for
the <experimental/simd> namespace.
* include/experimental/bits/simd.h: Move BEGIN macro before
Doxygen @{ group.
Jonathan Wakely [Fri, 1 May 2026 11:15:17 +0000 (12:15 +0100)]
libstdc++: Improve Doxygen comments for <iterator> contents
Use markdown and suppress unwanted docs for internal helpers.
libstdc++-v3/ChangeLog:
* include/bits/stl_iterator.h: Prevent Doxygen from documenting
namespace __detail as part of the Iterators topic.
* include/bits/stl_iterator_base_funcs.h: Likewise. Also mark
internal helpers as undocumented.
(distance, advance): Improve Doxygen comments.
* include/bits/stl_iterator_base_types.h (iterator): Use
markdown in Doxygen comment. Add @deprecated.
(iterator_traits): Improve wording of Doxygen comment.
Jonathan Wakely [Thu, 30 Apr 2026 12:27:48 +0000 (13:27 +0100)]
libstdc++: Do not assume URBG::result_type exists [PR121919]
The ranges::sample and ranges::shuffle algorithms are supposed to work
with types which model std::uniform_random_bit_generator, which means
they should not assume that G::result_type is present. That isn't needed
to satisfy the concept. Change the algorithms to use decltype(__g())
instead of using result_type.
This isn't sufficient to fix the bug though, because those algorithms
use std::uniform_int_distribution and that class template's operator()
overloads depend on the more restrictive uniform random bit generator
requirements, which do include the presence of a nested result_type
member.
We need to change std::uniform_int_distribution to also use decltype
instead of the nested result_type, even though the standard says that
std::uniform_int_distribution is allowed to assume that result_type
exists.
There's yet another problem, which is that a type that returns random
bool values can model the concept, but doesn't meet the named
requirements and can't be used with std::uniform_int_distribution. That
isn't addressed by this change.
libstdc++-v3/ChangeLog:
PR libstdc++/121919
* include/bits/ranges_algo.h (__sample_fn, __shuffle_fn): Use
decltype(__g()) instead of remove_reference_t<_G>::result_type.
* include/bits/uniform_int_dist.h
(uniform_int_distribution::operator()): Use decltype(__urng())
instead of _UniformRandomBitGenerator::result_type
(uniform_int_distribution::__generate_impl): Likewise.
* testsuite/25_algorithms/sample/121919.cc: New test.
* testsuite/25_algorithms/shuffle/121919.cc: New test.
Eric Botcazou [Fri, 1 May 2026 10:54:38 +0000 (12:54 +0200)]
Ada: Link with PIC static Ada runtime when -pie is specified
This changes gnatlink to append _pic to the name of the static Ada runtime
when -pie is passed on the command line.
gcc/ada/
PR ada/87936
* gnatlink.adb (Gnatlink): Rename local variable and add Output_PIE
local variable; when it is set, compile the binder file with -fPIE.
(Process_Args): Set Output_PIE upon seeing -pie.
(Process_Binder_File): Append "_pic" to the name of the static Ada
runtime if Output_PIE is set.
s390: Fix dealing with HF vector modes in s390_secondary_reload
Initial HF mode support was added in commit r16-6682-g5d6d56d837c which
is missing HF vector mode support when dealing with secondary reloads
for instructions which do not accept relative operands.
gcc/ChangeLog:
* config/s390/s390.cc (s390_secondary_reload): Add cases for HF
vector modes.
* config/s390/s390.md: Add modes V{1,2,4,8}HF to mode iterator
ALL.
Jeff Law [Fri, 1 May 2026 03:37:34 +0000 (21:37 -0600)]
[V3][RISC-V][PR rtl-optimization/96692] Improve xor+xor+ior sequence when possible
Consider this code:
int f(int a, int b, int c)
{
return (a ^ b) ^ (a | c);
}
For RISC-V we generate something like this:
xor a1,a0,a1
or a0,a0,a2
xor a0,a1,a0
But this would be better:
andn a0,a2,a0
xor a0,a0,a1
It looks like Roger tackled this earlier with splitters for x86. I'd have
leaned more towards simplify-rtx, but there may be secondary concerns at play.
So I'll attack in the RISC-V target files in a similar manner.
The patch, but not the testcase, have been in my tester for a while, so it's
been bootstrapped and regression tested on the Pioneer and BPI-F3 board and
regression tested on riscv32-elf and riscv64-elf. Obviously I'll wait for
pre-commit CI before moving forward.
PR rtl-optimization/96692
gcc/
* config/riscv/bitmanip.md (xor+xor+ior splitters): New splitters
that ultimately generate andn+xor when possible.
H.J. Lu [Wed, 15 Apr 2026 05:43:08 +0000 (13:43 +0800)]
x86: Remove DI_REG/SI_REG from x86_64_int_return_registers
Since only AX/DX register pair and XMM0/XMM1 register pair are used for
function return values in 64-bit mode, remove DI_REG and SI_REG registers
from x86_64_int_return_registers and limit the number of registers used
in return values to 2 in 64-bit mode.
Tested on Linux/x86-64 and Linux/i686.
PR target/124878
* config/i386/i386.cc (x86_64_int_return_registers): Remove
DI_REG and SI_REG.
(ix86_function_value_regno_p): Remove DI_REG and SI_REG cases.
(function_value_64): Replace X86_64_REGPARM_MAX and
X86_64_SSE_REGPARM_MAX with X86_64_MAX_RETURN_NREGS and
X86_64_MAX_SSE_RETURN_NREGS for the number of registers used
in return values.
* config/i386/i386.h (X86_64_MAX_RETURN_NREGS): New. Defined
to 2.
(X86_64_MAX_SSE_RETURN_NREGS): Likewise.
H.J. Lu [Thu, 30 Apr 2026 07:37:13 +0000 (15:37 +0800)]
x86: Disable 16-bit imm store for TARGET_LCP_STALL
When TARGET_LCP_STALL is enabled, 16-bit immediate integer store should
be avoided. Update V_16_32_64:*mov<mode>_imm to disable 16-bit immediate
integer store when TARGET_LCP_STALL is enabled.
Tested on Linux/x86-64 and Linux/i686.
PR target/125102
* config/i386/mmx.md (V_16_32_64:*mov<mode>_imm): Disable
16-bit immediate integer store if TARGET_LCP_STALL is true.
Felix Morgner [Thu, 30 Apr 2026 16:24:07 +0000 (17:24 +0100)]
libstdc++: Add <bits/binders.h> to freestanding headers [PR125112]
The <ranges> header was added to the freestanding headers in r16-3575-g1a41e52d7ecb58 but bits/binders.h that it depends on was not
moved, making <ranges> unusable with --disable-libstdcxx-hosted.
libstdc++-v3/ChangeLog:
PR libstdc++/125112
* include/Makefile.am: Move bits/binders.h from bits_headers to
bits_freestanding.
* include/Makefile.in:
[IRA]: Process operand NO_REGS class for reg cost calculation
In record_reg_classes there is no special processing of case op_class ==
NO_REGS. It can result in very high cost of the insn alternative cost.
The patch fixes this and can change generated code.
gcc/ChangeLog:
* ira-costs.cc (record_reg_classes): Process correctly case
op_class == NO_REGS.
[IRA]: Fix soft conflict and hard reg cost calculation
When finding soft conflict in IRA, we wrongly use conflict allocno mode.
This can result in more shuffling on the region borders and worse code
generation. The patch fixes this.
gcc/ChangeLog:
* ira-color.cc (assign_hard_reg): Use the right allocno mode to
call note_conflict.
- ICE verify_vssa exceeds stack space for big functions [PR124805]
The source from PR124561 led to an ICE with --enable-checking, caused by a stack overflow.
The recursive verification code verify_vssa in tree-ssa.cc could not handle the extreme
number of basic blocks within the typical limits of stack space.
As for PR124561 the recursive code was transformed into an iterative version, which
avoided the recursive calls.
A worklist is used, which has as entries a pair of a basic_block and a tree (vdef).
The logic of verification steps for each basic_block is unchanged, although the order
of basic_blocks is changed.
This fixes PR124805.
Reg tested OK.
2026-04-07 Heiko Eißfeldt <heiko@hexco.de>
PR middle-end/124805
* tree-ssa.cc (verify_vssa):
replace recursive calls with iteration for lower stack usage
Andrew Pinski [Wed, 29 Apr 2026 21:34:32 +0000 (14:34 -0700)]
match: Simplify patterns for `a != b` implies a or b is non-zero
This simplified the patterns by using a for loop. Also noticed
that the `:c` on the inner ne/eq is not needed as it will match
the same canonicalization as the inner bit_ior too so removes that too.
This removes a little more 300 lines from the generated gimple-match*.cc files too.
Bootstrapped and tested on x86_64-linux-gnu.
gcc/ChangeLog:
* match.pd (`(a !=/== b) &\| ((a|b) ==/!= 0)`):
Simplify patterns using for loop and remove the `:c`
on the inner ne/eq.
Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
aarch64: Handle opts_set parameter properly in aarch64_option_restore
Previously, the AArch64 implementation of TARGET_OPTION_RESTORE ignored
the opts_set parameter and its callee, aarch64_override_options_internal,
invoked SET_OPTION_IF_UNSET with &global_options_set instead of with
opts_set.
That was bad for maintainability, because it was based on an assumption
that cl_target_option_restore would only be called with &global_options_set.
Otherwise, if an option were set in *opts_set but not in global_options_set,
the corresponding value would have been wrongly overridden; conversely, if
an option were set in global_options_set but not in *opts_set then its
value would not have been overridden as expected.
It looks as though cl_target_option_restore is not currently called with
an argument expression other than &global_options_set except by the arm,
i386 and s390 backends. However, ascertaining that and ensuring it will
always be true wastes more time than simply doing the right thing.
gcc/ChangeLog:
* config/aarch64/aarch64-c.cc (aarch64_pragma_target_parse):
Pass &global_options_set as an argument to
aarch64_override_options_internal.
* config/aarch64/aarch64-protos.h (aarch64_override_options_internal):
Add a parameter declaration for opts_set.
* config/aarch64/aarch64.cc (aarch64_override_options_internal):
Add a parameter declaration for opts_set and use the argument
when invoking SET_OPTION_IF_UNSET.
(aarch64_override_options): Pass &global_options_set as an argument to
aarch64_override_options_internal.
(aarch64_option_restore): As above.
(aarch64_set_current_function): As above.
(aarch64_option_valid_attribute_p): As above.
(aarch64_option_valid_version_attribute_p): As above.
Richard Biener [Thu, 30 Apr 2026 06:39:52 +0000 (08:39 +0200)]
tree-optimization/125088 - some TLC to the new vect_bb_slp_scalar_cost
This realizes that orig_stmt_info == stmt and refactors control flow
around cost recording to avoid the do { } while (false); loop which
had continue stmts confusing coverity.
PR tree-optimization/125088
* tree-vect-slp.cc (vect_bb_slp_scalar_cost): Refactor and
simplify.
* tree-vect-stmts.cc (vect_nop_conversion_p): Exclude
copies with memory accesses.
Richard Biener [Fri, 24 Apr 2026 12:35:49 +0000 (14:35 +0200)]
flip --param ix86-vect-compare-costs default
The following flips the default of ix86-vect-compare-costs as discussed
during stage3/4. It adds the testcase from PR120398 and ensures the
existing one works without specifying the --param.
Testcases have been adjusted with simple dump scan adjustments.
gcc.target/i386/vect-epilogues-10.c shows that we compute the
masked epilog to be more expensive than the not masked one. That's
probably correct as we're facing an in-order reduction. I have
added -fno-vect-cost-model given this is a testcase for a missing
feature.
PR tree-optimization/120398
PR tree-optimization/123603
* config/i386/i386.opt (ix86-vect-compare-costs): Default to 1.
Richard Biener [Wed, 29 Apr 2026 13:26:35 +0000 (15:26 +0200)]
[x86] Avoid gcc.target/i386/shift-gf2p8affine-?.c fails with compare costs
The following disables epilogue vectorization for the
gcc.target/i386/shift-gf2p8affine-?.c tests so they pass with both
--param ix86-vect-compare-costs=1 and =0.
Richard Biener [Wed, 29 Apr 2026 09:07:06 +0000 (11:07 +0200)]
[x86] Adjust gcc.target/i386/vect-epilogues-2.c and vect-pr113078.c
The following adjusts two very similar testcases that when
vector cost comparison is enabled and with generic tuning,
chose to use SSE vector size for the vector epilogue as that
reduces the possible iterations through the scalar epilogue
following that and thus speeds up the overall epilogue processing
for a majority of cases. I have chosen to duplicate the
testcases for --param ix86-vect-compare-costs=0 and =1.
Richard Biener [Tue, 28 Apr 2026 13:44:41 +0000 (15:44 +0200)]
[x86] Adjust gcc.target/i386/vect-strided-?.c for cost compare
With cost comparison and MMX-with-SSE vector width available we
prefer to use V2SImode over V4SImode with shuffles, rightfully
so I think. The following adds variants with explicit cost
compare enabled and disabled and adjusts the cost comparison
variant accordingly.
The following resolves the gcc.target/i386/vect-epilogues-3.c failure
when --param ix86-vect-compare-costs=1 is specified. When the target
requests multiple epilogues to be used and the new candidate is the
epilogue of choice of the currently prevailing epilogue keep that.
But avoid doing so if the new candidate uses a vectorization factor
of one which should be an optimal vector epilog. This avoids
regressing gcc.dg/vect/costmodel/x86_64/costmodel-pr122573.c
* config/i386/i386.cc (ix86_vector_costs::better_epilogue_loop_than_p):
New. If the other loop suggests this as epilog prefer other.
This overrides vector_costs::better_main_loop_than_p to avoid
regressing gcc.target/i386/vect-partial-vectors-2.c with
--param ix86-vect-compare-costs=1. As the user (or a tuning model)
asks for masked epilogs the vectorizer considers to mask the
main loop in case it effectively works as a standalone vector epilog
due to known small number of iterations of the loop. While the
generic cost compare rightfully figures masking of AVX is more expensive
than not masking with SSE it does not consider the cost of the epilog.
This compensates with a x86 specific heuristic that prefers the
masked loop if the loop cannot be vectorized with a non-masked
main loop and at most a single vector epilog plus a single scalar
epilog iteration. This is a reasonable heuristic for x86 and
a small number of iterations as icache footprint matters here,
so considering the possibility of 3 vector epilogs and 1 scalar
iteration does not look profitable. Unless testcases will prove
to us otherwise.
I'm not sure if it makes sense to preserve --param ix86-vect-compare-costs=0
in the end, if people think so I'll duplicate the testcase with
both modes explicitly specified.
* tree-vectorizer.h (vector_costs::vinfo): New accessor.
* config/i386/i386.cc (ix86_vector_costs::better_main_loop_than_p):
Prefer a masked main loop if we can elide enough of (vector)
epilog loop iterations.
This expands on the changes from test fix r16-6710-gda5a5c55284969:
* test name now reflect the size of the generator range,
* extracted code repeated between tests was exctracted to run_generator,
* expanded non-power of two ranges types to cover all IEC559 floating point,
* select values to test based on the size of mantisa instead of type,
handling different long double representations.
The test now cover the cases, where mutliple value greater than one are
produced (and skipped) in the row. To avoid test running infinite loop,
the number of skips per element is limited by max_skips_per_elem template
parameter of run_generator.
The values checked in test_2p31m1<double> differs from their old test03<double>
counterpart, as we now request mantissa - 5 bits for each type (48bits for
ieee64) instead of previously hardoced 30bits.
Andrew Pinski [Wed, 29 Apr 2026 19:49:49 +0000 (12:49 -0700)]
testsuite: Fix cond-add-vec-2.C and make cond-add-vec-1.C test some more
With -march=cascadelake/-mavx512f, the VEC_COND_EXPR is turned into a COND_ADD.
This breaks cond-add-vec-2.C check to make sure the conditional add is still there.
So we need to check for COND_ADD or VEC_COND_EXPR in forwprop1.
Even though cond-add-vec-1.C works right now, it is best to make sure COND_ADD is
not there.
Pushed as obvious after testing with and without -march=cascadelake on x86_64.
gcc/testsuite/ChangeLog:
* g++.dg/tree-ssa/cond-add-vec-1.C: Add a check to make sure COND_ADD
is not there either.
* g++.dg/tree-ssa/cond-add-vec-2.C: Change the check for VEC_COND_EXPR
to allow for COND_ADD.
Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
Wilco Dijkstra [Tue, 3 Feb 2026 18:31:51 +0000 (18:31 +0000)]
AArch64: Deprecate -mpc-relative-literal-loads
Deprecate -mpc-relative-literal-loads. Emitting special symbols in
the text section causes issues (see PR123791). Since the option is
relatively obscure and GCC now uses anchors for literals, there is
no need to keep it.
Cleanup code models - remove the confusing AARCH64_CMODEL_TINY_PIC,
AARCH64_CMODEL_SMALL_PIC and AARCH64_CMODEL_SMALL_SPIC. This simplifies
a lot of code. No change to generated code.
[LRA]: Fix a bug in updating live info in rematerialization
LRA rematerialization ignores that a pseudo can require more one hard reg
when updating live hard reg info. This can result in wrong
rematerialization. The patch fixes this.
gcc/ChangeLog:
* lra-remat.cc (do_remat): Use the right nregs for pseudo hard reg
when updating live hard regs.
[IRA]: Use correct allocno when building conflicts
When conflicts are built in IRA a wrong conflict allocno is taken. The
allocno is used only in assertion which becomes always true and checks
nothing. The patch fixes this.
gcc/ChangeLog:
* ira-conflicts.cc (build_object_conflicts): Use the right
conflicting allocno.
Richard Biener [Wed, 29 Apr 2026 12:28:49 +0000 (14:28 +0200)]
tree-optimization/125080 - fix SLP scalar stmt coverage for instance roots
Even instance roots can be mentioned in externs of other instances
and thus have to be kept scalar. Consider that.
PR tree-optimization/125080
* tree-vect-slp.cc (vect_bb_slp_mark_stmts_vectorized): Only
add instance root stmts to scalar coverage if they do not
appear in externs.
Patrick Palka [Wed, 29 Apr 2026 12:48:50 +0000 (08:48 -0400)]
c++/modules: memfn merging wrt to obj-ness [PR125035]
Here we ICE during declaration merging for the streamed-in static A::f
because we incorrectly match with the in-TU iobj A::f instead of the
in-TU static A::f.
The problem is the merge key doesn't have enough information to discern
between two overloads that essentially only differ by whether they have
an object parameter (and whether it's implicit or explicit). To that end
this patch adds iobj_p and xobj_p bits to merge_key.
PR c++/125035
gcc/cp/ChangeLog:
* module.cc (merge_key): Add iobj_p and xobj_p bits.
(trees_out::key_mergeable) <case MK_named>: Set and stream
merge_key's iobj_p and xobj_p bits.
(check_mergeable_decl) <case FUNCTION_DECL>: Compare merge_key's
iobj_p and xobj_p bits with that of the given function.
(trees_in::key_mergeable): Stream merge_key's iobj_p and xobj_p
bits.
gcc/testsuite/ChangeLog:
* g++.dg/modules/merge-22.h: New test.
* g++.dg/modules/merge-22_a.H: New test.
* g++.dg/modules/merge-22_b.C: New test.
Patrick Palka [Wed, 29 Apr 2026 12:48:31 +0000 (08:48 -0400)]
c++/modules+reflection: fix merging typedef struct { } A [PR124582]
r16-7903 changed the representation of typedefs to an unnamed type, such
as typedef struct { } A, so that we preserve both the unnamed and typedef
TYPE_DECL rather than replacing the unnamed decl. This patch teaches
modules declaration merging to handle the new representation when streaming
in the unnamed decl, working around the fact that the unnamed decl isn't
visible to name lookup but still has the same DECL_NAME as the typedef decl.
PR c++/124582
PR c++/123810
gcc/cp/ChangeLog:
* module.cc (check_mergeable_decl) <case TYPE_DECL>: Handle
merging a typedef to an unnamed type with the -freflection
representation.
gcc/testsuite/ChangeLog:
* g++.dg/modules/anon-4.h: New test.
* g++.dg/modules/anon-4_a.H: New test.
* g++.dg/modules/anon-4_b.C: New test.
Xin Liu [Wed, 29 Apr 2026 10:56:50 +0000 (10:56 +0000)]
i386: Support HYGON c86-4g series processors
This patch enables new x86 CPU vendor HYGON ID detection
and adds c86-4g series c86-4g-m{4,6,7} processor supports.
Without such support, if users use -march=native option on
HYGON machines, they can get some old arch like core2, it
would be suboptimal. It also enables -m{arch,tune}=c86-4g
-m{4,6,7} supports. Based on the hardware characteristics,
appropriate cost models and tuning parameters are provided.
New machine description files are introduced: c86-4g.md is
used to describe the pipeline for c86-4g-m4 and c86-4g-m6,
while c86-4g-m7.md describes the pipeline for c86-4g-m7.
To better model some pipeline information, it introduces
new attrs c86_attr and c86_decode by following existing
practice.
Bootstrapped and regtested on hygon c86-4g-m4 and c86-4g-m7
machine, as well as a cfarm x86-64 machine.
Co-authored-by: Zhaoling Bao <baozhaoling@hygon.cn> Signed-off-by: Xin Liu <liulxx@hygon.cn> Signed-off-by: Zhaoling Bao <baozhaoling@hygon.cn>
gcc/ChangeLog:
* gcc.target/i386/builtin_target.c: Add handling for HYGON CPUs by
validating the vendor and invoking HYGON-specific CPU detection.
* gcc.target/i386/funcspec-56.inc: Test function target attribute on
{arch,tune}=c86-4g-m{4,6,7}.
* g++.target/i386/mv33.C: New test.
Julian Brown [Wed, 29 Apr 2026 10:12:13 +0000 (12:12 +0200)]
OpenMP: Expand "declare mapper" mappers for target {enter,exit,} data directives
This patch allows 'declare mapper' mappers to be used on 'omp target
data', 'omp target enter data' and 'omp target exit data' directives.
For each of these, only explicit mappings are supported, unlike for
'omp target' directives where implicit uses of variables inside an
offload region might trigger mappers also.
Add support for C and C++.
The patch also adjusts 'map kind decay' to match OpenMP 5.2 semantics,
which is particularly important with regard to 'exit data' operations.
gcc/c-family/
* c-common.h (c_omp_region_type): Add C_ORT_EXIT_DATA,
C_ORT_OMP_EXIT_DATA.
(c_omp_instantiate_mappers): Add region type parameter.
* c-omp.cc (omp_split_map_kind, omp_join_map_kind,
omp_map_decayed_kind): New functions.
(omp_instantiate_mapper): Add ORT parameter. Implement map kind decay
for instantiated mapper clauses.
(c_omp_instantiate_mappers): Add ORT parameter, pass to
omp_instantiate_mapper.
gcc/c/
* c-parser.cc (c_parser_omp_target_data): Instantiate mappers for
'omp target data'.
(c_parser_omp_target_enter_data): Instantiate mappers for 'omp target
enter data'.
(c_parser_omp_target_exit_data): Instantiate mappers for 'omp target
exit data'.
(c_parser_omp_target): Add c_omp_region_type argument to
c_omp_instantiate_mappers call.
* c-tree.h (c_omp_instantiate_mappers): Remove spurious prototype.
gcc/cp/
* parser.cc (cp_parser_omp_target_data): Instantiate mappers for 'omp
target data'.
(cp_parser_omp_target_enter_data): Instantiate mappers for 'omp target
enter data'.
(cp_parser_omp_target_exit_data): Instantiate mappers for 'omp target
exit data'.
(cp_parser_omp_target): Add c_omp_region_type argument to
c_omp_instantiate_mappers call.
* pt.cc (tsubst_omp_clauses): Instantiate mappers for OMP regions other
than just C_ORT_OMP_TARGET.
(tsubst_expr): Update call to tsubst_omp_clauses for OMP_TARGET_UPDATE,
OMP_TARGET_ENTER_DATA, OMP_TARGET_EXIT_DATA stanza.
* semantics.cc (cxx_omp_map_array_section): Avoid calling
build_array_ref for non-array/non-pointer bases (error reported
already).
gcc/testsuite/
* c-c++-common/gomp/declare-mapper-15.c: New test.
* c-c++-common/gomp/declare-mapper-16.c: New test.
* g++.dg/gomp/declare-mapper-1.C: Adjust expected scan output.
Pan Li [Mon, 27 Apr 2026 02:01:52 +0000 (10:01 +0800)]
RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost
This patch would like to combine the vec_duplicate + vmsgtu.vv to the
vmsgtu.vx. From example as below code. The related pattern will depend
on the cost of vec_duplicate from GR2VR. Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.
Assume we have asm code like below, GR2VR cost is 0.
Jakub Jelinek [Wed, 29 Apr 2026 09:12:47 +0000 (11:12 +0200)]
bitintlower: Padding bit fixes, part 6 [PR123635]
I've missed torture/bitint-{93,94}.c FAILs on s390x-linux (i.e. big endian).
For __builtin_mul_overflow, the code to extend the partial most significant
limb is done before memmoving it down, so that limb actually isn't on big
endian at offset 0 but is nelts - obj_nelts. The following patch computes
obj_nelts first, uses it on big-endian and so that the offset checking
asserts don't trigger, on big-endian also uses NULL_TREE first argument to
limb_access.
2026-04-29 Jakub Jelinek <jakub@redhat.com>
PR middle-end/123635
* gimple-lower-bitint.cc (bitint_large_huge::finish_arith_overflow):
Move obj_nelts/atype computation before bitint_extended handling. For
bitint_big_endian in the bitint_extended handling use size_zero_node
only for limb_access_type calls, otherwise use
size_int (nelts - obj_nelts) and pass NULL_TREE as first argument to
limb_access calls.
BB SLP: Enabling reduction root finding for sum-of-diff kind of patterns
Add an optional parameter allow_alt_code to vect_slp_linearize_chain
(default true). When false, do not follow into MINUS_EXPR when
building a PLUS reduction chain; treat MINUS results as leaves.
This will allow "sum of diffs" (d_i = a[i]-b[i], sum = d0+...+dN)
kind of pattern to be recognized and vectorized. Pure PLUS chains
will still work; other callers of vect_slp_linearize_chain keep the
default. Once support for MINUS_EXPR in the chain is added, this
call site can be switched to allow_alt_code true.
gcc/ChangeLog:
* tree-vect-slp.cc (vect_slp_linearize_chain): Optional parameter
allow_alt_code added (default true), check added not to follow
MINUS_EXPR, when false.
(vect_slp_check_for_roots): Calls vect_slp_linearize_chain with
parameter allow_alt_code set to false.
Jakub Jelinek [Wed, 29 Apr 2026 06:01:02 +0000 (08:01 +0200)]
c++: Fix up REFLECT_BASE comparison
While writing testcase for PR125007 I found an ICE in cp_tree_equal.
The r16-7260 change to compare_reflections broke REFLECT_BASE comparisons.
It now calls cp_tree_equal on their REFLECT_EXPR_HANDLE which is TREE_BINFO.
It works if lhs == rhs, returns true, or if TREE_CODE is different (returns
false), but otherwise the function isn't prepared to handle TREE_BINFO
and because TREE_BINFO is tcc_exceptional, ends with
default:
gcc_unreachable ();
(for --disable-checking it actually works by doing return false; after
this). This patch fixes that in the third hunk by doing lhs == rhs
comparison only.
2026-04-29 Jakub Jelinek <jakub@redhat.com>
* reflect.cc (compare_reflection): For REFLECT_BASE use lhs == rhs rather
than cp_tree_equal.
Jakub Jelinek [Wed, 29 Apr 2026 05:58:46 +0000 (07:58 +0200)]
testsuite: Diagnose non-uglified names even in requires exprs
I was worried we don't handle lambda parameters/captures,
but apparently we do (so I have just added tests to verify that),
and noticed we don't handle params of requires expressions, so
added test coverage for that and handled those in the plugins.
2026-04-29 Jakub Jelinek <jakub@redhat.com>
* g++.dg/plugin/uglification_plugin.cc (plugin_check_tree): Walk
REQUIRES_EXPR_PARMS of REQUIRES_EXPR.
(plugin_walk_decl): Walk TEMPLATE_PARMS_CONSTRAINTS using
plugin_check_tree. Walk DECL_INITIAL of CONCEPT_DECL as well.
* g++.dg/plugin/uglification.C: Add tests for non-uglified names
in lambda parameters, lambda captures and requires expressions.
Reviewed-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
Jakub Jelinek [Wed, 29 Apr 2026 05:55:02 +0000 (07:55 +0200)]
testsuite: Add plugin to verify bits/std.cc exports
The following patch adds another g++.dg/plugin/ testsuite plugin,
this time to verify whether some std.cc exports aren't mistakenly
omitted.
The patch is a reworked version of the
https://gcc.gnu.org/pipermail/libstdc++/2025-August/thread.html#62859
proof of concept. That version just dumped out everything it saw
in the std namespace and its child namespaces (excluding non-inline
subnamespaces with identifiers starting with underscore) and then I've
used sed&grep to form a list of omissions.
This patch keeps the previous walk of std namespace and namespaces children
of it, but it only reports (in this version using error_at instead of inform
previously) what it finds if it isn't exported from the module and is not
deprecated (deprecated attribute is used usually for zombie.names in the
standard).
I've been strugling with the detection of what is and what isn't exported,
had to try several different methods.
What is DECL_MODULE_EXPORT_P is ignored, but that is not set on everything
actually exported. In other cases there is OVL_EXPORT_P flag on OVERLOAD
(but OVL_HIDDEN_P at the start doesn't have it). Another case are inline
namespaces, e.g. for std::filesystem::__cxx11::begin or
std::filesystem::__cxx11::directory_iterator. In the latter case, there
is no sign of the above flags in __cxx11 binding entry, but there is a
USING_DECL with the same name directly in std::filesystem. And for begin
there is OVERLOAD with OVL_EXPORT_P in std::filesystem but not in
std::filesystem::__cxx11.
2026-04-29 Jakub Jelinek <jakub@redhat.com>
* g++.dg/plugin/plugin.exp: Set PLUGIN_DEFAULT_REPO. Add
set*module*exports* to plugin_test_list. Remove *.gcm files
at the start and end.
* g++.dg/plugin/std_module_exports_plugin.cc: New file.
* g++.dg/plugin/std-module-exports-c++20.C: New test.
* g++.dg/plugin/std-module-exports-c++23.C: New test.
* g++.dg/plugin/std-module-exports-c++26.C: New test.
Reviewed-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
Jakub Jelinek [Wed, 29 Apr 2026 05:49:32 +0000 (07:49 +0200)]
testsuite: Add C++ plugin to check for libstdc++ header uglification
The following patch adds a plugin (sorry, to check-g++ testsuite rather
than libstdc++ testsuite because in plugin.exp we have all the needed
infrastructure.
The plugin diagnoses non-obfuscated function parameter names, automatic
variable names, template arguments, requires arguments etc., but as an
exception allows non-obfuscated names which appear as function/template
etc. names in std namespace. The uglification.C test verifies the plugin
diagnoses what it should be.
2026-04-29 Jakub Jelinek <jakub@redhat.com>
* g++.dg/plugin/plugin.exp (plugin_test_list): Add uglification tests.
* g++.dg/plugin/uglification_plugin.cc: New file.
* g++.dg/plugin/uglification.C: New test.
* g++.dg/plugin/uglification-c++98.C: New test.
* g++.dg/plugin/uglification-c++11.C: New test.
* g++.dg/plugin/uglification-c++14.C: New test.
* g++.dg/plugin/uglification-c++17.C: New test.
* g++.dg/plugin/uglification-c++20.C: New test.
* g++.dg/plugin/uglification-c++23.C: New test.
* g++.dg/plugin/uglification-c++26.C: New test.
Reviewed-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
libstdc++: simd: x86: accept 64-bit long double as double [PR124657]
Various simd_x86 functions that handle double need to be adjusted to
match 64-bit long double as well.
Introduce __is_x86_ps<_Tp>() and __is_x86_pd<_Tp>() and use them
instead of is_same_v<_Tp, float> and is_same_v<_Tp, double>,
respectively.
for libstdc++-v3/ChangeLog
PR libstdc++/124657
* include/experimental/bits/simd_x86.h
(__is_x86_ps<_Tp>): New. Replace is_same_v<_Tp, float> with it.
(__is_x86_pd<_Tp>): New. Replace is_same_v<_Tp, double> with it.
libstdc++: follow std in numeric_limits<bool>::traps and integral traps
There's a comment from 2002 suggesting that
numeric_limits<bool>::traps was in a DR, but C++ standards including
11, 17 and 23 explicitly set it to false, presumably in response to
issue 184.
Issue 554 clarifies that traps is about values that may trap, rather
than operations that may trap, so we were wrong in the interpretation
about divide-by-zero operations' trapping on integral types that led
to __glibcxx_integral_traps's defaulting to true, and some of its
overrides.
Align numeric_limits<bool>::traps with the standard, default
__glibcxx_integral_traps to false, drop the overriders based on the
incorrect interpretation, but keep __glibcxx_integral_traps to allow
command-line restoring of this ABI fix, and for the admittedly
unlikely case of trapping integral values' coming to exist on some
architecture.
for libstdc++-v3/ChangeLog
* include/std/limits (__glibcxx_integral_traps): Set to
false. Update comments.
(numeric_limits<bool>::traps): Drop comments.
* config/cpu/arm/cpu_defines.h: Remove.
* config/cpu/powerpc/cpu_defines.h: Likewise.
* configure.host (cpu_defines_dir): Adjust.
David Malcolm [Tue, 24 Feb 2026 23:47:35 +0000 (18:47 -0500)]
analyzer: new warning: -Wanalyzer-div-by-zero (PR analyzer/124217)
gcc/analyzer/ChangeLog:
PR analyzer/124217
* analyzer.opt (Wanalyzer-div-by-zero): New.
* analyzer.opt.urls: Regenerate.
* region-model.cc (class div_by_zero_diagnostic): New.
(region_model::get_gassign_result): Add warning for division by
zero if ctxt is non-null. Bail out on such cases even if ctxt
is null.
* svalue.cc (type_can_have_value_range_p): Also handle frange.
David Malcolm [Mon, 23 Mar 2026 18:29:27 +0000 (14:29 -0400)]
analyzer: split out various pending_diagnostic subclasses from region-model.cc
Split up region-model.cc somewhat. No functional change intended.
gcc/ChangeLog:
* Makefile.in (ANALYZER_OBJS): Add
analyzer/poisoned-value-diagnostic.o,
analyzer/shift-diagnostics.o, and
analyzer/write-to-const-diagnostics.o.
gcc/analyzer/ChangeLog:
* poisoned-value-diagnostic.cc: New file, taken from material in
region-model.cc.
* region-model.cc (class poisoned_value_diagnostic): Move to
poisoned-value-diagnostic.cc.
(class shift_count_negative_diagnostic): Move to
shift-diagnostics.cc.
(class shift_count_overflow_diagnostic): Likewise.
(region_model::get_gassign_result): Use factory functions when
creating diagnostics so that the subclasses can be moved to their
own source files.
(region_model::check_for_poison): Likewise.
(region_model::deref_rvalue): Likewise.
(class write_to_const_diagnostic): Move to
write-to-const-diagnostics.cc.
(class write_to_string_literal_diagnostic): Likewise.
(region_model::check_for_writable_region): Use factory functions
when creating diagnostics so that the subclasses can be moved to
their own source files.
* region-model.h (make_poisoned_value_diagnostic): New decl.
(make_shift_count_negative_diagnostic): New decl.
(make_shift_count_overflow_diagnostic): New decl.
(make_write_to_const_diagnostic): New decl.
(make_write_to_string_literal_diagnostic): New decl.
* shift-diagnostics.cc: New file, taken from material in
region-model.cc.
* write-to-const-diagnostics.cc: Likewise.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Thu, 15 Jan 2026 19:17:08 +0000 (14:17 -0500)]
analyzer: use concrete_binding_map for compound_svalue (PR analyzer/123145)
A compound_svalue can only have concrete bindings. Capture this in the
type system by splitting out the concrete parts of class binding_map
into a new class concrete_binding_map, and use the latter for
compound_svalue. This also allows some simplifications and
optimizations, where we can use bit_range rather than binding keys.
No functional change intended.
gcc/analyzer/ChangeLog:
PR analyzer/123145
* access-diagram.cc
(compound_svalue_spatial_item::compound_svalue_spatial_item):
Update for compound_svalue using concrete_binding_map rather than
binding_map.
* bounds-checking.cc (strip_types): Likewise.
* call-summary.cc
(call_summary_replay::convert_svalue_from_summary_1): Update for
reimplementation of class binding_map.
(call_summary_replay::convert_svalue_from_summary_1): Likewise.
* infinite-recursion.cc (contains_unknown_p): Update for
compound_svalue using concrete_binding_map rather than
binding_map.
* program-state.cc (sm_state_map::impl_set_state): Likewise.
* region-model-manager.cc (maybe_undo_optimize_bit_field_compare):
Likewise.
(maybe_undo_optimize_bit_field_compare): Avoid building a
concrete_binding key by using get_any_exact_binding.
(region_model_manager::get_or_create_compound_svalue): New
overload, consuming a concrete_binding_map &&.
* region-model-manager.h
(region_model_manager::get_or_create_compound_svalue): New decl
for the above.
* region-model-reachability.cc (reachable_regions::handle_sval):
Update for compound_svalue using concrete_binding_map rather than
binding_map.
(reachable_regions::handle_parm): Likewise.
* region-model.cc (region_model::scan_for_null_terminator_1): Port
from binding_map to concrete_binding_map.
(exposure_through_uninit_copy::calc_num_uninit_bits): Update for
compound_svalue using concrete_binding_map rather than
binding_map.
(contains_uninit_p): Likewise.
* region.cc (decl_region::calc_svalue_for_constructor): Port from
binding_map to concrete_binding_map.
(decl_region::get_svalue_for_initializer): Update call to
get_or_create_compound_svalue.
* store.cc (concrete_binding_map::dump_to_pp): New.
(concrete_binding_map::dump): New.
(concrete_binding_map::add_to_tree_widget): New.
(concrete_binding_map::validate): New.
(binding_map::cmp): Convert to...
(concrete_binding_map::cmp): ...this.
(concrete_binding_map::get_any_exact_binding): New.
(concrete_binding_map::calc_complexity): New.
(concrete_binding_map::remove_overlapping_binding): New.
(concrete_binding_map::remove_overlapping_bindings): New.
(concrete_binding_map::get_overlapping_bindings): New.
(binding_map::put): Update for change to m_concrete.
(binding_map::validate): Likewise.
(binding_map::apply_ctor_to_region): Convert to...
(concrete_binding_map::apply_ctor_to_region): ...this.
(binding_map::apply_ctor_val_to_range): Convert to...
(concrete_binding_map::apply_ctor_val_to_range): ...this.
(binding_map::apply_ctor_pair_to_child_region): Convert to...
(concrete_binding_map::apply_ctor_pair_to_child_region): ...this.
(binding_map::remove_overlapping_bindings): Move part of
implementation to
concrete_binding_map::remove_overlapping_binding.
(binding_cluster::bind_compound_sval): Simplify using
concrete_binding_map.
(binding_cluster::maybe_get_compound_binding): Likewise.
(store::replay_call_summary_cluster): Update for change
to compound_svalue.
* store.h: Include "analyzer/complexity.h".
(class concrete_binding_map): New, based on
binding_map::concrete_bindings_t.
(binding_map::concrete_bindings_t): Use concrete_binding_map.
(binding_map::empty_p): Update for above.
(binding_map::apply_ctor_to_region): Drop decl.
(binding_map::cmp): Likewise.
(binding_map::apply_ctor_val_to_range): Likewise.
(binding_map::apply_ctor_pair_to_child_region): Likewise.
* svalue.cc (svalue::cmp_ptr): Update for change to
compound_svalue.
(compound_svalue::compound_svalue): Port from binding_map to
concrete_binding_map.
(compound_svalue::accept): Likewise.
(compound_svalue::calc_complexity): Drop.
(compound_svalue::maybe_fold_bits_within): Port from binding_map
to concrete_binding_map.
* svalue.h (class compound_svalue): Update leading comment. Port
from binding_map to concrete_binding_map.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Virginia Kodsy [Wed, 25 Mar 2026 15:39:39 +0000 (17:39 +0200)]
analyzer: add known_function handler for strcasecmp
This patch adds a known_function handler for strcasecmp to the
static analyzer. It ensures the analyzer checks for null-terminated
string arguments and, when a return value is expected (LHS),
it conjures a symbolic value for the result.
analyzer: model mktemp-family success/failure outcomes [PR105890]
The known_function handlers for the mktemp family all use
set_any_lhs_with_defaults, leaving the return value unconstrained.
This means the analyzer cannot distinguish the success path from the
failure path and cannot, for example, detect use of an invalid file
descriptor returned by mkstemp.
This patch makes the analyzer aware of each function's return
convention. A nested enum kf_mktemp_family::outcome describes the
three conventions used by the family:
fd -- returns a non-negative fd on success, -1 on failure
(mkstemp, mkostemp, mkstemps, mkostemps).
null_ptr -- returns a pointer on success, NULL on failure
(mkdtemp).
modif_tmpl -- returns the template pointer; sets template[0] to
'\0' on failure (mktemp).
Each call is bifurcated into success and failure paths, modeling
the return value and errno according to the outcome. This enables
fd leak and double-close detection for the fd-returning variants.
A new helper region_model::update_for_null_return is added for the
null_ptr failure path.
The template placeholder check is now in impl_call_post and influences
bifurcation: when the placeholder is definitely invalid, only the
failure path is explored.
The patch "analyzer: new warnings -Wanalyzer-mkstemp-missing-suffix
and -Wanalyzer-mkstemp-of-string-literal [PR105890]" added those two
warnings for mkstemp only. This patch generalizes them to the whole
mktemp family (including GNU extensions): mktemp, mkstemp, mkostemp,
mkstemps, mkostemps, and mkdtemp.
The two warnings are renamed to reflect their broader scope:
-Wanalyzer-mkstemp-missing-suffix becomes
-Wanalyzer-mktemp-missing-placeholder. For the suffixed variants
(mkstemps, mkostemps), the diagnostic accounts for the suffix length
when locating the "XXXXXX" placeholder.
-Wanalyzer-mkostemp-redundant-flags warns when mkostemp or
mkostemps is called with flags that include O_RDWR, O_CREAT, or
O_EXCL, which are already implied by these functions and produce
errors on some systems.
All three warnings are enabled by default under -fanalyzer.
Bootstrapped and tested on x86_64-pc-linux-gnu.
gcc/analyzer/ChangeLog:
PR analyzer/105890
* analyzer-language.cc (stash_named_constants): Stash O_CREAT,
O_EXCL, and O_RDWR for use by kf.cc.
* analyzer.opt: Rename -Wanalyzer-mkstemp-missing-suffix to
-Wanalyzer-mktemp-missing-placeholder and
-Wanalyzer-mkstemp-of-string-literal to
-Wanalyzer-mktemp-of-string-literal. Add
-Wanalyzer-mkostemp-redundant-flags. Fix alphabetical ordering.
* analyzer.opt.urls: Regenerate.
* kf.cc (class mkstemp_of_string_literal): Rename to...
(class mktemp_of_string_literal): ...this.
(class mkstemp_missing_suffix): Rename to...
(class mktemp_missing_placeholder): ...this. Add trailing_len
parameter for suffixed variants.
(class mkostemp_redundant_flags): New diagnostic class.
(class kf_mktemp_family): New base class with shared template
and flags checking logic.
(kf_mktemp_family::check_template_with_suffixlen_arg): New.
(kf_mktemp_family::check_template): New.
(kf_mktemp_family::check_flags): New.
(kf_mktemp_family::check_placeholder): New.
(class kf_mkstemp): Rename to...
(class kf_mktemp_simple): ...this. Generalize to handle mktemp,
mkstemp, and mkdtemp.
(class kf_mkostemp): New known_function handler.
(class kf_mkostemps): New known_function handler.
(class kf_mkstemps): New known_function handler.
(register_known_functions): Register all mktemp family handlers.
gcc/ChangeLog:
PR analyzer/105890
* doc/invoke.texi: Rename -Wanalyzer-mkstemp-missing-suffix to
-Wanalyzer-mktemp-missing-placeholder and
-Wanalyzer-mkstemp-of-string-literal to
-Wanalyzer-mktemp-of-string-literal. Add
-Wanalyzer-mkostemp-redundant-flags. Fix alphabetical ordering
of detailed descriptions.
gcc/testsuite/ChangeLog:
PR analyzer/105890
* gcc.dg/analyzer/mkstemp-1.c: Update terminology from "suffix"
to "placeholder".
* gcc.dg/analyzer/mkdtemp-1.c: New test.
* gcc.dg/analyzer/mkostemp-1.c: New test.
* gcc.dg/analyzer/mkostemps-1.c: New test.
* gcc.dg/analyzer/mkstemps-1.c: New test.
* gcc.dg/analyzer/mktemp-1.c: New test.
Signed-off-by: Tomas Ortin Fernandez (quanrong) <quanrong@mailbox.org>
analyzer: new warnings -Wanalyzer-mkstemp-missing-suffix and -Wanalyzer-mkstemp-of-string-literal [PR105890]
This patch adds two new analyzer warnings for misuse of mkstemp(3):
-Wanalyzer-mkstemp-of-string-literal warns when a string literal is
passed to mkstemp. Since mkstemp modifies its argument in place,
passing a string literal is undefined behavior (SEI CERT C rule
STR30-C). The diagnostic suggests using a writable character array
instead.
-Wanalyzer-mkstemp-missing-suffix warns when the template argument
does not end with the required "XXXXXX" suffix. This addresses PR
analyzer/105890.
Both warnings are enabled by default under -fanalyzer.
The checks are in the analyzer rather than -Wformat because mkstemp
does not use a format attribute. Placing the checks in the analyzer
could also allow interprocedural analysis in the future, once the
analyzer can fully track string contents across function calls.
Bootstrapped and tested on x86_64-pc-linux-gnu.
gcc/analyzer/ChangeLog:
PR analyzer/105890
* analyzer.opt: Add -Wanalyzer-mkstemp-missing-suffix and
-Wanalyzer-mkstemp-of-string-literal.
* analyzer.opt.urls: Add URL entries for the new warnings.
* kf.cc (class mkstemp_of_string_literal): New diagnostic class
for mkstemp called on a string literal.
(class mkstemp_missing_suffix): New diagnostic class for mkstemp
called with a template missing the "XXXXXX" suffix.
(class kf_mkstemp): New known_function handler for mkstemp.
(register_known_functions): Register kf_mkstemp.
gcc/ChangeLog:
PR analyzer/105890
* doc/invoke.texi: Add -Wanalyzer-mkstemp-missing-suffix and
-Wanalyzer-mkstemp-of-string-literal.
gcc/testsuite/ChangeLog:
PR analyzer/105890
* gcc.dg/analyzer/mkstemp-1.c: New test.
Signed-off-by: Tomas Ortin Fernandez (quanrong) <quanrong@mailbox.org>
Saksham Gupta [Mon, 9 Mar 2026 06:20:36 +0000 (11:50 +0530)]
analyzer: add known function handling for atoi, atol, and atoll
This patch adds kf_atoi_family to handle atoi, atol, and atoll functions in the
analyzer, ensuring that the argument is checked for a valid,
null-terminated string.
gcc/analyzer/ChangeLog:
* kf.cc (class kf_atoi_family): New class.
(register_known_functions): Register atoi, atol, and atoll.
gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/atoi-1.c: Update test coverage.
David Malcolm [Tue, 24 Feb 2026 22:54:39 +0000 (17:54 -0500)]
sarif-replay: decode event IDs [PR123056]
Attempt to round-trip event IDs through in execution paths
through SARIF.
gcc/ChangeLog:
PR sarif-replay/123056
* libsarifreplay.cc: Include "json-pointer-parsing.h".
(sarif_replayer::sarif_replayer): Initialize m_root_val.
(sarif_replayer::m_root_val): New field.
(sarif_replayer::replay_file): Store m_root_val.
(sarif_replayer::append_embeddded_link): Add message_obj param.
Attempt to decode intra-sarif links, turning them into event IDs.
(sarif_replayer::decode_link_within_sarif): New.
(sarif_replayer::make_plain_text_within_result_message): Pass
message_obj to append_embeddded_link.
gcc/testsuite/ChangeLog:
PR sarif-replay/123056
* sarif-replay.dg/2.1.0-invalid/3.10.3-bad-json-pointer.sarif: New
test.
* sarif-replay.dg/2.1.0-valid/embedded-links-pr123056-check-sarif-roundtrip.py
(test_roundtrip_of_url_in_generated_sarif): Update expected
result, to expect the URL for the event.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Tue, 24 Feb 2026 22:44:31 +0000 (17:44 -0500)]
Introduce pretty-print-token-buffer.{cc,h}
Move the implementation of diagnostic_message_buffer from libdiagnostics
to a new pretty-print-token-buffer.{cc,h}, for capturing the tokens from
a pretty-print.
Implement a new class pp_token_buffer_element for replaying the tokens
in a pretty_print_token_buffer into another pretty-print, using "%e".
Add selftests.
gcc/ChangeLog:
* Makefile.in (OBJS-libcommon): Add pretty-print-token-buffer.o.
* libgdiagnostics.cc: Drop include of "auto-obstack.h".
Include "pretty-print-token-buffer.h".
(class copying_token_printer): Move to
pretty-print-token-buffer.cc.
(struct diagnostic_message_buffer): Reimplement as a subclass of
pretty_print_token_buffer.
(diagnostic_message_buffer::to_string): Rename to
pretty_print_token_buffer::to_string and move to
pretty-print-token-buffer.cc.
* pretty-print-token-buffer.cc: New file, based on material from
libgdiagnostics.cc.
* pretty-print-token-buffer.h: New file, based on material from
libgdiagnostics.h.
* selftest-run-tests.cc (selftest::run_tests): Call
selftest::pretty_print_token_buffer_cc_tests.
* selftest.h (selftest::pretty_print_token_buffer_cc_tests): New
decl.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Mon, 19 Jan 2026 17:25:55 +0000 (12:25 -0500)]
analyzer: avoid naked "new"
Modernization; no functional change intended.
gcc/analyzer/ChangeLog:
* access-diagram.cc
(access_diagram_impl::add_aligned_child_table): Use
std::make_unique rather than "new".
(access_diagram_impl::add_valid_vs_invalid_ruler): Likewise.
* checker-path.h (checker_path::replace_event): Use
std::unique_ptr.
* diagnostic-manager.cc
(diagnostic_manager::consolidate_conditions): Use std::make_unique
rather than "new".
* feasible-graph.cc (feasible_graph::make_epath): Likewise.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Jeff Law [Tue, 28 Apr 2026 22:55:13 +0000 (16:55 -0600)]
[V3][RISC-V][PR target/124760] Promote SI to DI in some cases to encourage shNadd insns
So for this testcase:
int foo (int t)
{
return 3 * t - 1;
}
We currently generate:
slliw a5,a0,1
addw a0,a5,a0
addiw a0,a0,-1
ret
Intuitively we can see we're doing a 32->64 sign extension at each step and we
could drop the intermediate sign extensions. In fact, not only can we drop the
intermediate sign extensions, we can safely "promote" the intermediate
operations from SI to DI with a final sign extending add. Conceptually that
unlocks combining the first shift+add into a shNadd insn resulting in this
code:
sh1add a0, a0, a0
addiw a0, a0, -1
ret
The patch, but not the testcase, has been in my tree for a while, so it's been
through bootstrap & regression testing on the BPI and Pioneer as well as
testing on riscv32-elf and riscv64-elf. Obviously I'll wait for pre-commit CI
to do its thing before pushing.
PR target/124760
gcc/
* config/riscv/bitmanip.md (SI->DI promoting shadd pattern): Promote
intermediate SI ops to DI ops when there's a final extending op.
Andrew Pinski [Tue, 28 Apr 2026 19:46:31 +0000 (12:46 -0700)]
phiprop: Fix typo [PR125067]
When I factored out the code in can_handle_load, I had a small typo
which seemed to work for most cases but I had noticed later on was
broken. Basically the bb where the vop definition has to be dominated
by the current bb (and can't be the current bb).
Pushed as obvious afte a quick bootstrapped.
PR tree-optimization/125067
gcc/ChangeLog:
* tree-ssa-phiprop.cc (can_handle_load): Fix copy and pasto
on dominated_by_p.
Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
The proposed resolution of CWG 3065 suggests that reflection on a block-scope
extern declaration be ill-formed. This patch makes it so, and it also
happens to fix a crash.
PR c++/124756
gcc/cp/ChangeLog:
* reflect.cc (get_reflection): Give an error when taking the
reflection of a block-scope extern.
Marek Polacek [Mon, 20 Apr 2026 17:00:52 +0000 (13:00 -0400)]
c++/reflection: improve diagnostic for dependent splices
In the parser we've changed the "not usable in a splice" error messages
to the more helpful "expected a reflection of ...", but tsubst_splice_scope
still uses the former. This patch updates the diagnostic there as well.
Let's also teach inform_tree_category about concepts and alias templates
now that a testcase exercises them.
gcc/cp/ChangeLog:
* error.cc (inform_tree_category): Also print concept and alias
template.
* pt.cc (tsubst_splice_scope): Reword the diagnostic messages.
Call inform_tree_category.
[LRA]: Fix elimination recognition for INC/DEC RTL
There is a typo when we processing {PRE,POST}_{INC,DEC} and
{PRE,POST}_MODIFY to prevent elimination of hard reg operand. The
condition actually makes to consider pseudos instead of hard reg. The
patch fixes this.
gcc/ChangeLog:
* lra-eliminations.cc (mark_not_eliminable): Fix condition to
consider hard regs instead of pseudos for INC/DEC/MODIFY operands.
When searching prefered hard regs from too strict constraints we can ignore
some alternatives for subsequent operands. This can result in worse code
generation. The patch fixes this.
gcc/ChangeLog:
* ira-lives.cc (ira_implicitly_set_insn_hard_regs): Use the same
start prefered for all operand.
projects / thirdparty / gcc.git / log
