Roger Sayle [Fri, 24 Jul 2026 06:21:48 +0000 (07:21 +0100)]
x86 SSE: Use insertps to zero V4SI/V4SF elements in a single instruction.
This patch teaches the x86 backend that the SSE4.1 insertps instruction
can be used/abused to clear one or more elements of a V4SI or V4SF vector
in a single instruction (i.e. without requiring pxor to clear a second
register).
foo: xorl %eax, %eax
vpinsrd $2, %eax, %xmm0, %xmm0
ret
with this patch we now generate:
foo: vinsertps $4, %xmm0, %xmm0, %xmm0
ret
For the more complicated example:
v4si bar(v4si x) { x[1]=0; x[3]=0; return x; }
previously, we'd generate:
bar: xorl %eax, %eax
vpinsrd $1, %eax, %xmm0, %xmm0
vpinsrd $3, %eax, %xmm0, %xmm0
ret
with this patch we now generate:
bar: vinsertps $10, %xmm0, %xmm0, %xmm0
ret
One improvement that I'll leave to an i386/SSE expert, is that setting
elements 1, 2 and 3 [i.e. zero extending element 0] still falls back
to the existing patterns (and tests for this are commented out in the
new test cases). Tweaking sse_movss_v4si to consider using insertps
requires expertise in register preferencing and instruction attributes
that I'm happy to leave to someone else.
2026-07-24 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
gcc/ChangeLog
* config/i386/i386-expand.cc (ix86_expand_vec_set_builtin): Don't
force op1 to a register when it is CONST0_RTX (mode1).
(ix86_expand_vector_set_var): For now, force VAL to a register.
(ix86_expand_vector_set): If val is CONST0_RTX, expand using
the new sse4_1_insertps_v4s[if]_zero patterns on TARGET_SSE4_1.
Otherwise, force val to a register (restoring previous behaviour).
* config/i386/sse.md (sse4_1_insertps_<mode>_zero): New insn
using vec_merge to select which elements to clear/preserve.
(vec_set<mode>): Tweak operand 1 to allow both REGs and CONST0_RTX.
gcc/testsuite/ChangeLog
* gcc.target/i386/sse4_1-insertps-6.c: New test case.
* gcc.target/i386/sse4_1-insertps-7.c: Likewise.
Philipp Tomsich [Thu, 23 Jul 2026 17:09:21 +0000 (19:09 +0200)]
ifcvt: drop redundant reversibility pre-checks in store-flag callers
The PR126347 fix (commit dcb8c8d3e733) made noce_emit_store_flag return
NULL_RTX whenever the requested (reversed) comparison code is UNKNOWN, so
every caller already copes with an unreversible condition through the
existing NULL_RTX return.
Remove the redundant guards and document the invariant on
noce_emit_store_flag, matching noce_try_store_flag_logical, which already
relies on the NULL_RTX return with no pre-check. The noce_reversed_cond_code
guards in noce_try_addcc and noce_try_cmove_arith protect a different
consumer and are left in place.
Bootstrapped and regression tested on x86_64-pc-linux-gnu with no
regressions.
gcc/
* ifcvt.cc (noce_emit_store_flag): Document that a NULL_RTX
return signals an unreversible condition.
(noce_try_store_flag): Drop redundant noce_reversed_cond_code
pre-check.
(noce_try_shifted_store_flag): Likewise.
(noce_try_store_flag_constants): Drop redundant can_reverse
guards on the reversed 2^n and -1 cases.
(noce_try_store_flag_mask): Set reversep unconditionally; the
store-flag emission now handles an unreversible condition.
libgfortran: Add additional long double math support for hppa64-hpux*
On hppa-hpux, we lack support for C99 math routines but the long
double type conforms to the standard 16-byte IEEE (IEC 60559)
specification. This allows us to use the quad routines from
libquadmath.
2026-07-22 John David Anglin <danglin@gcc.gnu.org>
testsuite: use arm_neon as xfail condition [PR118407]
Before r17-2558-g383854a7016ad2, the test predcom-8.c test was only
failing for -march=armv7ve+neon and -march=armv7ve+simd. After, there
are xpass for Cortex-M targets. Correct xfail condition to arm_neon to
rectify my mistake.
gcc/testsuite/ChangeLog:
PR testsuite/118407
* gcc.dg/tree-ssa/predcom-8.c: Use arm_neon as xfail condition.
rs6000: Builtins for MMA+ float16 outer product instructions
This patch adds builtins for the Matrix Multiply Assist Plus (MMA+)
float16 GER instructions. These instructions may or may not be
supported in a future Power processor. Specifically, builtins have been
added for the following instructions:
Float16 GER operations:
- dmxvf16gerx2 and its variants (pp, pn, np, nn)
- pmdmxvf16gerx2 and its variants (pp, pn, np, nn)
Note, the names of the builtins may change in the future.
Philipp Tomsich [Tue, 21 Jul 2026 19:19:53 +0000 (21:19 +0200)]
ifcvt: do not emit a store flag for an irreversible condition [PR126347]
noce_emit_store_flag feeds the possibly-reversed comparison code to a
store-flag insn, and to emit_store_flag, without checking that the
reversal succeeded. reversed_comparison_code returns UNKNOWN for
UNLT/UNLE/UNGT/UNGE, and for a MODE_CC comparison it cannot trace back
to its COMPARE -- common for a floating-point condition on targets that
compare into a condition-code register. emit_store_flag then reaches
its floating-point path and calls swap_condition (UNKNOWN), which aborts.
This was latent until r17-2519-ga33f26607eb4f3 made
noce_try_shifted_store_flag the first caller to reach
noce_emit_store_flag with REVERSEP set for such a condition.
Bail out early when the reversal failed.
Bootstrapped and regression tested on aarch64-unknown-linux-gnu with no
regressions.
PR rtl-optimization/126347
gcc/
* ifcvt.cc (noce_emit_store_flag): Return NULL_RTX when the
comparison code is UNKNOWN.
rs6000: Builtins for MMA+ bfloat16 and int8 instructions [RFC02658]
This patch adds builtins for the Matrix Multiply Assist Plus (MMA+)
instructions defined in RFC02658. These instructions may or may not be
supported in a future Power processor. Specifically, builtins have been
added for the following instructions:
1. Bfloat16 GER operations:
- dmxvbf16gerx2 and its variants (pp, pn, np, nn)
- pmdmxvbf16gerx2 and its variants (pp, pn, np, nn)
2. Signed accumulate variant for 8-bit integer GER operations:
- dmxvi8gerx4spp
- pmdmxvi8gerx4spp
Note, the names of the builtins may change in the future.
rs6000: Add DMR extract builtins for Dense Math support
Add two new builtins for extracting data from 1024-bit Dense Math
Registers (DMRs):
- __builtin_dmr_extract512 (void *, dmr1024 *, const int<2>):
extracts one 512-bit half of a DMR into four 128-bit vectors.
- __builtin_disassemble_dmr (void *, dmr1024 *):
extracts both 512-bit halves of a DMR into eight 128-bit vectors.
gcc:
* config/rs6000/rs6000-builtins.def (__builtin_dmr_extract512): New
built-in.
(__builtin_disassemble_dmr): Likewise.
(__builtin_dmr_extract512_internal): New internal built-in.
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin):
Exempt RS6000_BIF_DISASSEMBLE_DMR from the early-return guard.
Generate appropriate gimple code for the extract builtins.
gcc/testsuite:
* gcc.target/powerpc/dmf-extract512.c: New test.
* gcc.target/powerpc/dmf-disassemble-dmr.c: New test.
This is an attempt to implement <https://cplusplus.github.io/LWG/issue3819>.
My understanding of this issue is that previously, ref_xes_from_temporary
was defined by using is_constructible, which is implemented by seeing
if
T t(declval<Args>()...);
is well-formed. But declval always yields an xvalue, never a prvalue.
In practice this means that for
struct U {
U();
U(U&&) = delete;
};
struct T {
T(U);
};
reference_constructs_from_temporary_v<const T&, U> is false due
to the deleted move ctor. But if we have a prvalue, then the
call to the move ctor should be elided and so it doesn't matter
that it's deleted. So the result should be 'true'.
Our ref_xes_from_temporary already doesn't check is_constructible<T, U>
as the comment says, but we always use build_trait_object which
gives us an xvalue. What we need is to implement [meta.unary.prop]/5.2:
Otherwise [not a reference or function type], VAL<T> is a prvalue that
initially has type T. For this I've added build_prvalue_trait_object.
The finish_trait_expr change is so that get_target_expr doesn't crash
on an incomplete type. This change should be correct since
https://cplusplus.github.io/LWG/issue2939 didn't adjust
reference_xes_from_temporary the same way as is_convertible/constructible.
PR c++/112908
gcc/cp/ChangeLog:
* method.cc (build_prvalue_trait_object): New.
(ref_xes_from_temporary): Use build_prvalue_trait_object.
Use deferring_access_check_sentinel and cp_unevaluated. Don't
call force_rvalue or rvalue.
* semantics.cc (finish_trait_expr)
<case CPTK_REF_CONSTRUCTS_FROM_TEMPORARY>: Actually check
completeness.
gcc/testsuite/ChangeLog:
* g++.dg/ext/is_constructible8.C: Move
__reference_*_from_temporary testing to a new test.
* g++.dg/ext/reference_xes_from_temporary2.C: New test.
* g++.dg/ext/reference_xes_from_temporary3.C: New test.
Jakub Jelinek [Thu, 23 Jul 2026 13:42:10 +0000 (15:42 +0200)]
c++: Diagnose return from [[noreturn]] function during constant evaluation [PR126354]
This PR complains about g++ not diagnosing return from [[noreturn]]
function (which is UB) during constant evaluation.
This patch diagnoses that.
I haven't included the [[noreturn]] function name in the diagnostics
as it is printed in the context:
/home/jakub/src/gcc/gcc/testsuite/g++.dg/cpp1y/pr126354.C:18:24: in 'constexpr' expansion of 'bar()'
/home/jakub/src/gcc/gcc/testsuite/g++.dg/cpp1y/pr126354.C:15:7: in 'constexpr' expansion of 'foo(false)'
/home/jakub/src/gcc/gcc/testsuite/g++.dg/cpp1y/pr126354.C:15:7: error: '[[noreturn]]' call returns
But if you think it is better to emit
error ("%<[[noreturn]]%> %qD call returns", fun);
instead, I can certainly do that.
2026-07-23 Jakub Jelinek <jakub@redhat.com>
PR c++/126354
* constexpr.cc (cxx_eval_call_expression): Diagnose return from
[[noreturn]] function.
* g++.dg/cpp1y/pr126354.C: New test.
* g++.dg/cpp26/pr126354.C: New test.
and we replace '<retval>' with 'names', but we only call
recompute_tree_invariant_expr for the first ADDR_EXPR, not the latter.
For the second ADDR_EXPR d->changed will be false: the first replacement
changed the shared tree <retval>.D.3013. In replace_placeholders_r we
unshare_expr when replacing a PLACEHOLDER_EXPR, but we also replace
PLACEHOLDER_EXPRs in lookup_placeholder which didn't have this
unsharing.
PR c++/126215
gcc/cp/ChangeLog:
* constexpr.cc (lookup_placeholder): Do unshare_expr.
Anlai Lu [Tue, 30 Jun 2026 12:49:03 +0000 (12:49 +0000)]
libstdc++: Use __chrono_write via _S_empty_fs for chrono ostream insertion
Add __detail::__chrono_write which formats a chrono object into a
stack buffer via std::format_to_n with _S_empty_fs(), then writes
through __ostream_insert. A non-type template parameter _BufSize
allows per-type buffer tuning. Each _BufSize is the smallest power
of two that accommodates the longest possible formatted output for
that type, including error cases. All chrono operator<< overloads
that previously used std::format, std::vformat, or basic_stringstream
now use this helper.
libstdc++-v3/ChangeLog:
* include/bits/chrono_io.h (__formatter_chrono::_S_empty_fs):
Make public.
(__detail::__chrono_write): New function template.
(operator<<): Use __chrono_write consistently for all chrono
types.
Reviewed-by: Jonathan Wakely <jwakely@redhat.com> Reviewed-by: Tomasz Kamiński <tkaminsk@redhat.com> Signed-off-by: Anlai Lu <agicy@qq.com>
libstdc++: Remove noexcept from basic_string instantiations [PR126327]
The explicit instantiations of basic_string's default constructor used
an unconditional noexcept specification. For the fully-dynamic COW
string, those default constructors are noexcept(false).
Remove noexcept from both the char and wchar_t instantiations.
Yan Churkin [Fri, 26 Jun 2026 19:45:31 +0000 (22:45 +0300)]
libstdc++: Don't dereference past-the-end iterator with overloaded operator&& [PR125981]
std::__find_if, std::__mismatch and std::__push_heap drove their loops
with a condition of the form
while (__first != __last && PREDICATE_CALL(...))
If the predicate/comparator result type has an ADL-reachable
operator&&(bool, T), overload resolution selects that user-defined
operator&& for the loop condition. It does not short-circuit, so the
operand that dereferences *__first is evaluated even when
__first == __last, dereferencing the past-the-end iterator.
Such a result type does not model boolean-testable, so this is undefined
behaviour and not a conformance issue. Handle it anyway as a QoI
extension, consistent with std::equal, std::binary_search and
std::__partition, by forcing the predicate result to bool so the
built-in && is used. This has no effect on well-behaved predicates; the
ranges:: versions are unaffected because their wrappers already return
bool.
PR libstdc++/125981
libstdc++-v3/ChangeLog:
* include/bits/stl_algobase.h (__find_if): Force the predicate
result to bool so that non-boolean_testable predicates cannot
cause a past-the-end iterator to be dereferenced.
(__mismatch): Likewise for both overloads.
* include/bits/stl_heap.h (__push_heap): Likewise for the
comparator result.
* testsuite/25_algorithms/find_if/overloaded_logical_ops.cc: New
test.
* testsuite/25_algorithms/mismatch/overloaded_logical_ops.cc:
New test.
Automake normally builds subdirectories sequentially, which makes the
libsanitizer builds effectively sequential as there is little parallelism per
subdirectory. This patch replaces the all-recursive loop with an explicit
dependency graph: asan and hwasan depend on lsan, while others just need
sanitizer_common.
Exposing this DAG to make raises the CPU load from 2.3 to 3.7, yielding a
roughly 30% reduction in build time on multi-core machines.
libsanitizer/ChangeLog:
* Makefile.am: Override all-recursive and define explicit
DAG dependencies for all-* targets to enable parallel builds.
* Makefile.in: Regenerate.
Signed-off-by: Harmen Stoppels <me@harmenstoppels.nl> Reviewed-by: Jakub Jelinek <jakub@redhat.com>
Jakub Jelinek [Thu, 23 Jul 2026 09:14:21 +0000 (11:14 +0200)]
c++: Diagnose declaration of objects with anonymous union or struct types [CWG3130]
https://wg21.link/CWG3130 added
"All objects of such an unnamed type shall be such an unnamed object."
sentence which should prevent reusing anonymous union types (and by
extension anonymous struct types too) as types of some other declarations,
which in some cases ICEs, in other cases is just really weird and could
misbehave when trying to look things up etc.
That wording is IMHO bad, because creation of objects is what happens
at runtime, so it is something that really can't be diagnosed by the compiler
because it doesn't know if a variable, function parameter, temporary etc.
will be actually encountered during runtime or not.
This patch assumes this sentence is changed to something reasonable that
would disallow anything that can create such objects at compile time,
so, declaration of variables, function parameters, class members,
constructs that need temporaries of this type, or all of those with
a type (perhaps multidimensional) array of anonmous union/struct.
In addition to that, I've added an error trying to make derived types from
anonymous struct types (one can't make derived types from union types, so
that case isn't a problem).
2026-07-23 Jakub Jelinek <jakub@redhat.com>
gcc/cp/
* typeck2.cc: Implement part of CWG3130 - Naming function members of
anonymous unions.
(abstract_virtuals_error): Diagnose trying to create
an object with anonymous union or struct type.
* semantics.cc (finish_compound_literal): Call abstract_virtuals_error.
(finish_member_declaration): Diagnose named members with anonymous
union or struct type.
* decl.cc (xref_basetypes): Diagnose anonymous structs as bases.
gcc/testsuite/
* g++.dg/cpp0x/anon-union4.C: New test.
* g++.dg/reflect/anon6.C: New test.
* g++.dg/reflect/anon7.C: New test.
* g++.dg/reflect/anon8.C: New test.
* g++.dg/reflect/anon9.C: New test.
* g++.dg/template/anonunion3.C: Expect an error.
testsuite: Provide shf_link_order effective target
Like R_flag_in_section, the o_flag_in_section effective target is a
misnomer. It actually signifies support for the SHF_LINK_ORDER section
flag. Therefore this patch uses the et-static framework to determine it
from HAVE_GAS_SECTION_LINK_ORDER in auto-host.h, adapting the existing
uses.
Bootstrapped without regressions on i386-pc-solaris2.11 and
x86_64-pc-linux-gnu.
Richard Biener [Wed, 15 Jul 2026 08:37:57 +0000 (10:37 +0200)]
Support two-lane vector BB reductions without target support
The following implements BB reduction epilog handling for two-lane
vectors with lane extracts. This allows targets to omit defining
reduc_*_scal optabs for two lane vector modes and enables trivial
handling of in-order reductions with two lanes. The former is
one issue we run into with PR126028 on x86_64.
This causes some no-op vectorization since we now accept vector
costs equal to scalar costs.
For gcc.target/i386/pr54400.c this shows that after SLP vectorizing
a two lane reduction we are no longer able to match up the x86 haddpd
instruction I have sent a partial x86 backend fix.
For g++.target/i386/pr114187.C it shows the usual
argument/return costing difficulties but also a too broad testcase
and inadverted coverage of -m32 - I have adjusted the testcase.
PR tree-optimization/126028
* tree-vect-slp.cc (vect_slp_check_for_roots): Move
fold-left reduction check ...
(vectorizable_bb_reduc_epilogue): ... here and allow
two reduction lanes to be unaffected. Handle the two
vector lane without target support for the reduction.
(vectorize_slp_instance_root_stmt): Implement manual two-lane
reduction.
* gcc.dg/vect/bb-slp-reduc-1.c: New testcase for a two-lane
in-order reduction.
* c-c++-common/vector-subscript-4.c: Use -fno-vectorize.
* g++.target/i386/pr114187.C: Narrow pattern to better
only catch the reported issue.
The existing R_flag_in_section effective target is badly named: the name
carries no mnemonic value and is actually an implementation detail of a
specific assembler section flag syntax.
This patch uses the et-static framework to replace it by a new
gnu_retain keyword. Given that the existing R_flag_in_section
implementation checks for both HAVE_GAS_SHF_GNU_RETAIN and
HAVE_INITFINI_ARRAY_SUPPORT, this patch starts with matching
shf_gnu_retain and sht_init_array keywords and combines them into
gnu_retain proper.
The existing tests are adaptated accordingly.
Bootstrapped without regressions on i386-pc-solaris2.11 and
x86_64-pc-linux-gnu.
gcc/testsuite:
* lib/et-static.def (shf_gnu_retain, sht_init_array): New
effective targets.
* lib/target-supports.exp
(check_effective_target_R_flag_in_section): Remove.
(check_effective_target_gnu_retain): New proc.
testsuite: Don't use auto-host.h in target-supports.exp
Several effective targets use a complicated dance to determine their
values from auto-host.h. This prompted the et-static framework, which
is now used to replace their implementations.
Bootstrapped without regressions on i386-pc-solaris2.11 and
x86_64-pc-linux-gnu.
Like the gas/solaris_as case, a testcase actually checks if Solaris ld
is in use. This patch uses the et-static framework to introduce a
solaris_ld effective target for this.
Other uses of the existing gld effective target are about GNU ld
features and remain untouched.
Bootstrapped without regressions on i386-pc-solaris2.11,
sparc-sun-solaris2.11 (as/ld and gas/gld), and x86_64-pc-linux-gnu.
Several uses of the gas effective target in the testsuite are actually
about if Solaris as is in use. This patch uses the new framework to
generate effective targets from auto-host.h to introduce a solaris_as
effective target and adjusts affected tests accordingly.
The existing gas effective target remains, however, because other uses
are about using gas features in particular.
Bootstrapped without regressions on i386-pc-solaris2.11,
sparc-sun-solaris2.11, x86_64-pc-linux-gnu, and
sparc64-unknown-linux-gnu.
i386: Update Suffix for AVX10.2 SAT CVT scalar Intrinsics
The previous _ep[i|u]{32,64} suffix for scalar SAT CVT intrinsics does
not match the intrinsic naming convention: scalar convert intrinsics
have used _[i|u]{32,64} (with _si{32,64} aliases for signed variants)
since AVX-512F, so the AVX10.2 scalar SAT CVT names need to follow the
same convention.
This patch renames the scalar SAT CVT intrinsics to use _[i|u]{32,64}
suffix and provides _si{32,64} aliases for the signed intrinsics.
gcc/ChangeLog:
* config/i386/avx10_2satcvtintrin.h
(_mm_cvtts_sd_i32): Renamed from _mm_cvtts_sd_epi32.
(_mm_cvtts_sd_si32): New alias of _mm_cvtts_sd_i32.
(_mm_cvtts_sd_u32): Renamed from _mm_cvtts_sd_epu32.
(_mm_cvtts_ss_i32): Renamed from _mm_cvtts_ss_epi32.
(_mm_cvtts_ss_si32): New alias of _mm_cvtts_ss_i32.
(_mm_cvtts_ss_u32): Renamed from _mm_cvtts_ss_epu32.
(_mm_cvtts_roundsd_i32): Renamed from _mm_cvtts_roundsd_epi32.
(_mm_cvtts_roundsd_si32): New alias of _mm_cvtts_roundsd_i32.
(_mm_cvtts_roundsd_u32): Renamed from _mm_cvtts_roundsd_epu32.
(_mm_cvtts_roundss_i32): Renamed from _mm_cvtts_roundss_epi32.
(_mm_cvtts_roundss_si32): New alias of _mm_cvtts_roundss_i32.
(_mm_cvtts_roundss_u32): Renamed from _mm_cvtts_roundss_epu32.
(_mm_cvtts_sd_i64): Renamed from _mm_cvtts_sd_epi64.
(_mm_cvtts_sd_si64): New alias of _mm_cvtts_sd_i64.
(_mm_cvtts_sd_u64): Renamed from _mm_cvtts_sd_epu64.
(_mm_cvtts_ss_i64): Renamed from _mm_cvtts_ss_epi64.
(_mm_cvtts_ss_si64): New alias of _mm_cvtts_ss_i64.
(_mm_cvtts_ss_u64): Renamed from _mm_cvtts_ss_epu64.
(_mm_cvtts_roundsd_i64): Renamed from _mm_cvtts_roundsd_epi64.
(_mm_cvtts_roundsd_si64): New alias of _mm_cvtts_roundsd_i64.
(_mm_cvtts_roundsd_u64): Renamed from _mm_cvtts_roundsd_epu64.
(_mm_cvtts_roundss_i64): Renamed from _mm_cvtts_roundss_epi64.
(_mm_cvtts_roundss_si64): New alias of _mm_cvtts_roundss_i64.
(_mm_cvtts_roundss_u64): Renamed from _mm_cvtts_roundss_epu64.
Expose existing vector conversion instructions through lrint optabs so
the vectorizer can use vcvtps2qq and vcvtpd2dq instead of scalar
conversion sequences.
gcc/ChangeLog:
PR target/126160
* config/i386/sse.md (lrint<ssePSmode2lower><mode>2): New expander.
(lrintv2sfv2di2): Likewise.
(ssedfsimode): New mode attribute.
(ssedfsimodelower): Likewise.
(lrint<mode><ssedfsimodelower>2): New expander.
gcc/testsuite/ChangeLog:
PR target/126160
* gcc.target/i386/pr126160.c: New test.
* gcc.target/i386/pr126160-2.c: New test.
rs6000: Update existing mma insns to use wD constraint and update %A printer
This patch replaces the 'd' constraint that was used for accumulators
previously since they overlapped with the FPRs, to use 'wD' constraint
and the new accumulator_operand in the existing mma define_insns. The
behaviour without dense-math option will be same as before, only if
dense-math option is used will the DMR registers be used.
It also updates the %A operand printer to print the DMR register numbers
instead of FPR if dense-math option is enabled
frange: Add a comparison function for range endpoints
IEEE calls -0.0 and +0.0 equal, but in frange they are distinct:
[+0.0, x] excludes -0.0 and [-0.0, x] includes it. We have been
fixing things on the fly at each modification site, either manually or
by calling combine_zeros to fix up the signs. This was hacky at best.
This patch removes the signed zero special casing by providing
frange_cmp(), a comparison function that orders -0.0 strictly below +0.0.
The ranges themselves are unchanged. The only difference is that we
are now more exact about whether we actually modified a range
containing a zero. Previously combine_zeros flagged a change whenever
the two ranges disagreed on the sign of a zero endpoint, even when the
canonical result was the sign we already had. This made union_ and
intersect return a changed range pessimistically. We are now more
accurate, so in theory the ranger cache should be happier.
With these cleanups we can start implementing multi-ranges for frange
without any special casing for signed zeros.
Tested on x86-64 and ppc64le Linux. No changes to assembly for a
corpus of preprocessed files from LAPACK. Also, LAPACK and GCC tests
pass as usual.
gcc/ChangeLog:
* value-range.cc (frange_cmp): New.
(frange::combine_zeros): Remove.
(frange::union_): Use frange_cmp to merge endpoints.
(frange::intersect): Likewise.
(frange::contains_p): Use frange_cmp.
(frange::verify_range): Use frange_cmp.
* value-range.h (class frange): Remove combine_zeros.
rs6000: Add Dense Math (DMF/MMA+) built-in/instruction support
Add support for the DMF (Dense Math Facility) and MMA+
(Matrix-Multiply Assist Plus) builtins and instructions which may be
available on a future Power processor.
This patch extends the existing MMA infrastructure to support Dense
Math Registers (DMRs).
Key changes:
1. Extended MMA operand support from 7 to 9 operands (MAX_MMA_OPERANDS)
2. Added new DMF-specific unspecs:
* UNSPEC_DMF_DMXOR for DMR XOR operations
* UNSPEC_DMF_DMXVI8GERX4* for DMR GER (outer product) operations
* UNSPEC_DMF_PMDMXVI8GERX4* for prefixed DMR GER operations
* UNSPEC_DMF_DMSETDMRZ for zeroing a DMR register
3. Implemented new instruction patterns in mma.md:
* dmf_build_dmr: Build a DMR from eight vector operands
* dmf_dmsetdmrz: Zero a DMR register
* dmf_dmxor: XOR operation on DMR registers
* dmf_dmxvi8gerx4/dmxvi8gerx4pp: DMR outer product operations
* dmf_pmdmxvi8gerx4/pmdmxvi8gerx4pp: Prefixed DMR outer product
operations
4. Added new DMF builtins and updated GIMPLE folding:
* Added DMF and MMA+ builtins
* Updated GIMPLE folding to handle DMR pass-by-reference semantics
* Extended builtin expansion to support up to 9 operand instructions
5. Added documentation for the new DMF and MMA+ builtins.
The implementation follows the existing MMA pattern where user-facing
builtins use pass-by-reference for DMR arguments, while internal
builtins use pass-by-value for optimization.
testsuite: prevent packing enum in vect-early-break_65.c [PR124112]
GCC might be compiled with -fshort-enum enabled by default.
For those targets, it is important that the enum type is not packed into
something smaller than int, or vectorization will not match.
gcc/testsuite/ChangeLog:
PR testsuite/124112
* gcc.dg/vect/vect-early-break_65.c: Prevent packing enum to a
smaller object.
The changes have been bootstrapped and regression tested on
powerpc64le-linux.
Register __dmr1024 as a new 1024-bit opaque built-in type, following
the same pattern as the existing __vector_pair (OOmode) and
__vector_quad (XOmode) opaque types. __dmr1024 uses TDOmode, which
was already added in a previous commit ("rs6000: Add TDOmode
support"), and is intended to hold the contents of a Dense Math
Register (DMR) when the Dense Math Facility (-mdense-math) is
enabled.
2026-07-22 Manjunath Matti <mmatti@linux.ibm.com>
gcc/
* config/rs6000/rs6000.h (RS6000_BTI_dmr1024): New enumerator.
(RS6000_BTI_ptr_dmr1024): New enumerator.
(dmr1024_type_node): New macro.
(ptr_dmr1024_type_node): New macro.
* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Handle
dmr1024_type_node.
(rs6000_init_builtins): Register the __dmr1024 opaque type and
its pointer-to-const variant, with 512-bit alignment.
* config/rs6000/rs6000.cc (rs6000_mangle_type): Handle
dmr1024_type_node.
(rs6000_invalid_conversion): Reject conversions to/from TDOmode.
(rs6000_opaque_type_invalid_use_p): Gate __vector_quad and
__vector_pair on TARGET_MMA and __dmr1024 on TARGET_DMF
independently, and require -mdense-math for __dmr1024.
gcc/testsuite/
* gcc.target/powerpc/dmr1024-alignment.c: New test case.
* gcc.target/powerpc/dmr1024-compile.c: Likewise.
* gcc.target/powerpc/dmr1024-invalid-use-1.c: Likewise.
* gcc.target/powerpc/dmr1024-invalid-use-2.c: Likewise.
* gcc.target/powerpc/dmf-no-mma.c: Likewise.
Pan Li [Wed, 22 Jul 2026 01:33:45 +0000 (09:33 +0800)]
RISC-V: Add test cases for vfwcvt.rtz.xu.f.v reg overlap
Add test cases for register group overlap, please
note it is not overlap as much as possible.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_xu-f16-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_xu-f16-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_xu-f16-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_xu-f16-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_xu-f16-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_xu-f32-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_xu-f32-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_xu-f32-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_xu-f32-mf2.c: New test.
Pan Li [Wed, 22 Jul 2026 01:32:21 +0000 (09:32 +0800)]
RISC-V: Add test cases for vfwcvt.rtz.x.f.v reg overlap
Add test cases for register group overlap, please
note it is not overlap as much as possible.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f16-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_rtz_x-f32-mf2.c: New test.
Andrew Pinski [Mon, 22 Jun 2026 23:54:27 +0000 (16:54 -0700)]
phiopt: for non-diamond case, invoke a limited conditional store elimination
After adding a limited store elimination function which is always valid even
without non-trapping code, we can call this from phiopt to optimize earlier
some ifconversion. This should allow for earlier optimizations of say perlbmk.
Also since the _limited version does not depend on store sinking, to happen,
some cases in loops might be better optimized.
Changes since v1:
* v2: Add false argument to cond_store_replacement_limited. And add/fixup
testcases.
Andrew Pinski [Sun, 21 Jun 2026 06:01:07 +0000 (23:01 -0700)]
cselim: reduced cs-elim without non-trapping
This adds a reduced cs-elim functionality which will be used
from phiopt. The design is similar to cond_store_replacement except
we are looking for a similar store right beore the condition or a
non-trapping (no data races or local variable) load right before
the conditional. This allows for 2 things, the reuse of the same
aliasing set and second is allows for use in phiopt in a secondary patch.
It supports the inserting on the edge for the case where there is
no load/stores before the condition if the store is a non-trapping memory
with no data races; this is a similar to what is done in cond_store_replacement
already. Thia part is not going to be used with phiopt though as it is too
complex to support there and it adds a conditional load for no benifit for
phiopt.
Note pr99473-1.c of a case where can be optimized even without
-fallow-store-data-races now. The store happens before the conditional
and inside the conditional, so afterwards there is only one store rather
than 2. The code was also handling it in sink in GCC 12 the same way too
but now handling it in cselim before sink1.
Changes since v1:
* v2: Add support for loads before the conditional and support
for doing the load on the edge. Fix formating and comments.
* v3: Move and rename can_trap_as_a_store to tree-eh.cc (lhs_could_trap_p).
Rename may_alias_mem to copy_mem_with_alias_set_zero.
Bootstrapped and tested on x86_64-linux-gnu.
gcc/ChangeLog:
* tree-eh.cc (lhs_could_trap_p): New function.
* tree-eh.h (lhs_could_trap_p): New decl.
* tree-ssa-phiopt.cc (copy_mem_with_alias_set_zero): New function.
(cond_store_replacement_limited): New function.
(pass_cselim::execute): Call cond_store_replacement_limited before
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr99473-1.c: Remove -fallow-store-data-races as it is not
needed with cond_store_replacement_limited.
Signed-off-by: Andrea Pinski <andrew.pinski@oss.qualcomm.com>
James K. Lowden [Wed, 22 Jul 2026 22:16:43 +0000 (18:16 -0400)]
cobol: Restrict CDF reserved words to CDF parsing.
Among others PARAMETER was captured as a reserved word during normal
parsing, which it is not. Move that and some other obvious CDF tokens
to the cdf_state start condition.
gcc/cobol/ChangeLog:
* scan.l: Make PARAMETER and friends unspecial outside CDF.
James K. Lowden [Wed, 22 Jul 2026 21:50:47 +0000 (17:50 -0400)]
cobol: Improve "sameness" test when deciding whether a CDF token was used.
In establishing whether or not the CDF parser discarded a lookahead
token, compare not just the last scanned token's type, but also its
location.
gcc/cobol/ChangeLog:
* cdf.y (cdf::location): New function.
* scan_post.h (same_end): New function to match token ending
locations.
(same_token): New function to match two tokens.
[frange] Consolidate signed-zero canonicalization of endpoints
The methods frange::set() and frange::flush_denormals_to_zero() canonicalize
ranges containing floating point zero endpoints differently. Whereas set()
includes both +0.0 and -0.0 in the range, so contains_p([+-]0.0) works, even
under -ffast-math, flush_denormals_to_zero() always sets the lower bound of a
positive denormal as +0.0, regardless of HONOR_SIGNED_ZEROS. This means that
contains_p(-0.0) would theoretically fail under -ffast-math.
In reality this last scenario doesn't happen because all users of zero endpoints
in the code are special casing signed zeros. Also, building a range with -0.0
would cause the set() canonicalization to kick in, and set the range to
[-0.0, +0.0] anyhow. Not only is this fragile at best, but in follow-up patches
I'd like to do some cleanup in this area, and one representation across the
board is in the spirit of what we've always tried to do with irange: a given
range should be representable in only one way (ok, not exactly cause we have
irange_bitmask's which complicate things, but we try ;-)).
Ultimately I'd like to implement sub-ranges for frange so we can represent
inequality with a constant, and tackle a couple of the signed zero PRs in this
area. But initially I just want to provide an frange_cmp() comparison
function that respects signed zeros, and lets users not have to worry about
special casing anything when dealing with endpoints.
For example, frange_cmp() will order -0.0 strictly below +0.0, so a membership
test becomes just two endpoint comparisons: -0.0 lands outside [+0.0, x] but
inside [-0.0, x], and nobody has to first ask "is this a zero, and if so which
one?". But that only works if a range always spells its zero endpoints the same
way. Today set() spells the lower zero of [0.0, 5.0] as -0.0 under -ffast-math,
while flush_denormals_to_zero() spells it +0.0, so one range ends up with two
bit patterns, and frange_cmp() would tell you [+0.0, 5.0] is a strict subset of
[-0.0, 5.0] even though they are the same range. Once both producers run
through canonicalize_zeros() the order is well defined, and when frange_cmp()
gets implemented, contains_p(), and the eventual sub-range union/intersect code
can just call it and drop their signed-zero special cases entirely.
This patch moves the canonicalization into one function that both set() and
flush_denormals_to_zero() can share. With it flush_denormals_to_zero() moves
the denormal endpoint to the zero on its side and lets canonicalize_zeros()
settle the sign, exactly as set() does.
I've included a selftest to test this: under -ffast-math, flushing
[+DENORM, 5.0] used to yield [+0.0, 5.0], while set() on the same range yields
[-0.0, 5.0]. With this patch, flushing also yields [-0.0, 5.0], matching set().
There's no observable change with this patch-- every consumer that reads the
sign of a zero endpoint already special-cases !HONOR_SIGNED_ZEROS, so nothing
today can tell the two representations apart.
Tested on x86-64 Linux with a full bootstrap and regtests. I also tested the
LAPACK suite for regressions, and I ran f951 over all the preprocessed Fortran
files in LAPACK and made sure there are no changes in the assembly with and
without this patch. Also, tested on ppc64le Linux, including LAPACK,
and making sure there are no changes in assembly with the preprocessed Fortran
files.
This is an internal-consistency fix and a prerequisite for upcoming patches
which will make the sign of a zero endpoint load-bearing.
gcc/ChangeLog:
* value-range.cc (frange::flush_denormals_to_zero): Collapse a
denormal endpoint to the zero of the same sign and defer the sign
to canonicalize_zeros.
(frange::canonicalize_zeros): New.
(frange::set): Use it.
(range_tests_flush_denormals): New.
(range_tests_floats): Call it.
* value-range.h (class frange): Declare canonicalize_zeros.
James K. Lowden [Wed, 22 Jul 2026 20:19:14 +0000 (16:19 -0400)]
cobol: Enable suppression of unimplemented exception conditions.
For each warning, provide both Wx and Wno-x in the specs string, so
that the driver passes both forms to the driver. This enables, in
addition to being able to defeat a default, to override the warning
status implied by a dialect.
gcc/cobol/ChangeLog:
* cobol1.cc (enable_exceptions): Remove redundant message.
* lang-specs.h: Provide both forms of every warning.
* parse.y: Remove deleterious comment.
Jerry DeLisle [Sat, 11 Jul 2026 04:47:59 +0000 (21:47 -0700)]
fortran: [PR78718] ICE in gfc_get_symbol_decl, at fortran/trans-decl.c
PR fortran/78718
gcc/fortran/ChangeLog:
* resolve.cc (was_declared): Recognize the RESULT attribute so a
function's result variable is not mistaken for a host-associated
symbol of the same name.
I noticed that as of commit 7cb252f60c1f600066300ede2781a2c9e3808adb
"libgomp: Add by-device capabilities for OpenMP 'omp requires' handling",
'libgomp.fortran/reverse-offload-5.f90' no longer XFAILs NVIDIA GPU offloading
execution, no matter whether non-USM or USM single-GPU system. That was
suspicious, given that this commit shouldn't cause any such difference in
behavior, per my understanding. Well, turns out, this commit indeed didn't
magically fix the failure, but it's just another case of non-existing static
type checking of flag values...
James K. Lowden [Wed, 22 Jul 2026 17:43:46 +0000 (13:43 -0400)]
cobol: Accept ASSIGN TO DEVICE.
For SELECT fd-name ASSIGN TO dev, "dev" may name either a runtime
environment variable (as previously) or, as now, an
implementation-defined device. New warnings govern dialect
variations. Fixes RT 3617.
gcc/cobol/ChangeLog:
* cbldiag.h (enum cbl_diag_id_t): New warnings.
* cobol1.cc (cobol_langhook_handle_option): Process warnings.
* gcobol.1: Document warnings and devices.
* lang-specs.h: Accept warngings.
* lang.opt: Define warnings.
* messages.cc: Associate warnings with dialects.
* parse.y: Parse new syntax.
Jerry DeLisle [Tue, 21 Jul 2026 16:15:50 +0000 (09:15 -0700)]
fortran: [PR53296] Fix character array-ctor function called twice
Avoid the redundant generated call to the pre chain when
no_function_call is set.
Also fix a related stack-buffer-overflow: gfc_conv_array_parameter
wrote over the array constructor's. The specified length was to short.
Use the explicit character type-spec length instead.
PR fortran/53296
gcc/fortran/ChangeLog:
* trans-expr.cc (gfc_conv_procedure_call): Skip the redundant
function call added to the pre chain when no_function_call is
set and the character result length was already determined
without running the callee.
* trans-array.cc (gfc_conv_array_parameter): Convert an array
constructor's explicit character type-spec length directly
instead of using the first elements length.
Andrea Pinski [Tue, 21 Jul 2026 18:25:34 +0000 (11:25 -0700)]
Fix maintainer_utils.py for older jsonscheme [PR126162]
Some semi-older distros don't have a new enough jsonscheme
installed. So this moves the scheme to the older json scheme
rather than using the 2020 one.
PR testsuite/126162
contrib/ChangeLog:
* maintainer_utils.py: Move to the older scheme which
is valid for MAINTAINERS.yml.
Signed-off-by: Andrea Pinski <andrew.pinski@oss.qualcomm.com> Co-authored-by: Arsen Arsenović <aarsenovic@baylibre.com>
Split the movxo pattern into DMF and non-DMF variants.
Use DMF move instructions (dmxxinstdmr512, dmmr, and dmxxextfdmr512)
for accumulator/DMR moves while retaining the existing split for
non-DMR operands.
2026-07-15 Vijay Shankar <vijay@linux.ibm.com>
gcc/ChangeLog:
* config/rs6000/mma.md (*movxo): renamed to movxo_nodmf
(*movxo_nodmf): updated contraint to use wD and add !TARGET_DMF
(*movxo_dmf): New pattern to handle dmf insert/extract from vsx
rs6000: Add TDOmode reload patterns for DMR registers
Add define_insn_and_split patterns for reloading TDOmode values between
Dense Math Registers (DMRs) and memory when TARGET_DMF is enabled.
2026-07-15 Surya Kumari Jangala <jskumari@linux.ibm.com>
Peter Bergner <bergner@linux.ibm.com>
gcc:
* config/rs6000/mma.md (UNSPEC_DMR_RELOAD_FROM_MEMORY): New unspec.
(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
(reload_tdo_load): New define_insn_and_split.
(reload_tdo_store): Likewise.
* config/rs6000/rs6000.cc (rs6000_init_hard_regno_mode_ok): Set
reload_load and reload_store for TDOmode when TARGET_DMF.
This patch
- Tweaks the signed overflow handling in __mulQ64_work.
- Rename misnomed fx24-mul.c to fx64-mul-1.c.
- Adds more test cases in fx64-mul-2.c.
libgcc/
* config/avr/lib1funcs-fixed.S (__mulQ64_work): Tweak
overflow handling. Use __negsi2 (non-saturating negation)
to negate.
gcc/testsuite/
* gcc.target/avr/fx24-mul.c: Renamed to...
* gcc.target/avr/fx64-mul-1.c: ...this.
* gcc.target/avr/fx64-mul-2.c: New test.
* gcc.target/avr/fx64-mul.h: New file.
testsuite: require cortex-a53 in reg_equal_test.c test
The original purpose of the test is to verify that, when the backend
emits a mov-pair sequence, the sequence carries a REG_EQUAL note for the
final constant value. Make that precondition explicit instead of
depending on target-specific tuning behavior, by forcing the test to
a CPU with the required properties.
gcc/testsuite/ChangeLog:
* gcc.target/arm/reg_equal_test.c: Add require effective target
cortex-a53 for test.
Jakub Jelinek [Wed, 22 Jul 2026 09:56:48 +0000 (11:56 +0200)]
libstdc++: Update Linux baselines for GCC 17.0
The following patch applies the powerpc64le-linux-gnu/baseline_symbols.txt
and x86_64-linux-gnu/baseline_symbols.txt r17-2579 changes to all
other linux arches which have recently updated baseline_symbols.txt
(i.e. those which have GLIBCXX_3.4.35 symbol version in it).
Those 3 symbols are architecture independent, they don't have any
size_t etc. argument that depends on the architecture, j (unsigned int) for
the last one is unsigned int on all arches.
On most the patch applied cleanly, on some (powerpc*/s390x*) I had to
manually resolve fuzz, as
FUNC:_ZNKSt16bad_array_length4whatEv@@CXXABI_1.3.8
there wasn't followed by
FUNC:_ZNKSt17bad_function_call4whatEv@@GLIBCXX_3.4.18
but some @@GLIBCXX_LDBL_3.4 symbols (which are _ZNKSt17* though, so the
two new comes alphabetically sorted before those).
libgomp: Add by-device capabilities for OpenMP 'omp requires' handling
Before the capabilities of a device were statically set to a generic
by-device-type value. This has been modified to additionally set them
to a value for a specific device.
On the plugin side, this permits to set the unified-shared memory
capability for only a subset of devices and to mark devices that are
integrated GPUs (APU) and support USM, which in turn permitted to move
the handling of OpenMP requirements from the plugin back to target.c
and permits in future to automatically enable unified-shared memory
for integrated GPUs/APUs.
The check for whether host memory can be accessed is for Nvidia GPUs
whether pageableMemoryAccess is supported (unchanged) and for AMD GPUs
whether SVM_ACCESSIBLE_BY_DEFAULT is supported (unchanged, global
property) and, if not, now also whether the device is an APU and
either XNACK is enabled or not supported by the hardware. For systems
with a single GPU, the result should be identical.
Note: The resulting capability is currently only used with
omp requires unified_shared_memory / self_maps
such that this flag is only set if the user code has this requirement
and all devices not supporting the host-memory access are filtered out.
Co-authored-by: Andrew Stubbs <ams@baylibre.com> Co-authored-by: supers1ngular <supers1ngular@baylibre.com>
include/ChangeLog:
Add move support for the new TDOmode opaque type used to represent
1024-bit Dense Math Registers that may be supported by future Power
processors.
Implement the movtdo pattern to support moves between memory, VSX
registers, and Dense Math Registers. Memory moves and VSX
register-to-register moves are handled by the generic multi-register
splitter. Dense Math Register-to-Register moves use dmmr, while moves
between VSX and Dense Math Registers are expanded using dm_insert1024
and dm_extract512.
gcc/
* config/rs6000/mma.md (UNSPEC_DMF_EXTRACT512): New unspec.
(dm_extract512): New insn.
(movtdo): New expander.
(*movtdo): New insn_and_split to support TDOmode moves between
memory, VSX registers, and Dense Math Registers.
* config/rs6000/rs6000.cc (rs6000_emit_move): Diagnose constant
assignments to TDOmode objects.
(rs6000_split_multireg_move): Handle TDOmode when splitting
multi-register moves.
rs6000: Build DMF accumulators using DMR insert operations
A future PowerPC processor may provide the Dense Math Facility (DMF),
where accumulators are backed by dedicated Dense Math Registers (DMRs).
Update accumulator assembly to build accumulators in DMRs using the new
DMR insert operations rather than xxmtacc/xxmfacc.
Add DMR register predicate support, enable the required OOmode VSX pair
patterns under TARGET_DMF, use accumulator operands for MMA accumulator
assembly and disassembly, and avoid emitting xxmtacc/xxmfacc during
internal accumulator moves and GIMPLE folding when DMF is enabled.
Add DMF instruction type and ISA attributes for instruction scheduling
and enablement.
2026-07-22 Kishan Parmar <kishan@linux.ibm.com>
gcc/
* config/rs6000/mma.md (UNSPEC_DMF_INSERT512): New unspec.
(UNSPEC_DMF_INSERT1024): Likewise.
(movoo): Enable for TARGET_DMF.
(*movoo): Likewise.
(vsx_assemble_pair): Likewise.
(*vsx_assemble_pair): Likewise.
(vsx_disassemble_pair): Likewise.
(*vsx_disassemble_pair): Likewise.
(dm_insert512): New insn.
(dm_insert1024): Likewise.
(mma_assemble_acc): Use accumulator_operand.
Build accumulators via DMR insert operations when TARGET_DMF.
(*mma_assemble_acc): Use accumulator_operand.
(mma_<acc>): New define_expand treating xxmtacc/xxmfacc as no-ops
for TARGET_DMF.
(*mma_<acc>): Restrict to !TARGET_DMF and use accumulator_operand.
(mma_disassemble_acc): Use accumulator_operand.
* config/rs6000/predicates.md (dmr_register_operand): New predicate.
(gpc_reg_operand): Accept DMR registers.
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Do
not emit xxmfacc for DISASSEMBLE_ACC when TARGET_DMF.
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Allow
OOmode in VSX register pairs for TARGET_DMF.
(rs6000_split_multireg_move): Avoid emitting xxmtacc/xxmfacc when
TARGET_DMF.
* config/rs6000/rs6000.md (type): Add dmf type.
(isa): Add mma and dmf ISA attributes.
(enabled): Add mma and dmf enable conditions.
gcc/testsuite/
* gcc.target/powerpc/dmf-xxacc.c: New test.
* gcc.target/powerpc/nodmf-xxacc.c: New test.
Juergen Christ [Tue, 10 Feb 2026 13:13:03 +0000 (14:13 +0100)]
s390x: Implement vec_cbranch_{all,any}
This enables early-exit vectorization on s390x.
Adjust the test suite since s390x does not support variable length
vectors and only supports basic vector load schemes.
gcc/ChangeLog:
* config/s390/s390-protos.h (s390_expand_vec_compare_gen_cc):
New function.
* config/s390/s390.cc (s390_expand_vec_compare_cc): Extract
part of this function into a ...
(s390_expand_vec_compare_gen_cc): ... new function.
* config/s390/vector.md (vec_cbranch_any<mode>): Implement.
(vec_cbranch_all<mode>): Implement.
rs6000: Add %wD constraint and predicate for accumulators
The future processor may introduce new set of registers for
accumulators. This patch adds a constraint and predicate for the
accumulator registers which can be used by the dense math and mma
patterns.
rs6000: Add support for Dense Math Facility (DMF) registers
The Dense Math Facility, which may be present in a future processor,
extends the Power architecture's computational capabilities by providing
eight dedicated registers (dmr0-dmr7) that can efficiently handle large
matrix operations. These registers will also be used in cryptographic
operations.
There are no operations to load/store Dense Math registers from/to
memory. For loading from memory, the 1024 bit value is first loaded into
8 VSX registers which are then copied into a DMR register. Similarly,
to store the contents of a DMR register into memory, the the contents
of the DMR are copied to 8 VSX registers which are then loaded into
memory.
Key Features:
1. Register Infrastructure:
- Adds 8 new DMR registers (dmr0-dmr7), numbered 111-118
- Each register is 1024 bits (128 bytes) in size
- Registers are call-used (caller-saved) following ABI conventions
- Increases total pseudo registers from 111 to 119
2. Data Type Support:
- TDOmode: New 1024-bit mode specifically for DMR operations
- XOmode: Extended to support both MMA accumulators (in FPRs) and
DMR registers, providing flexibility in register allocation
- Both modes support DMR registers when TARGET_DMF is enabled
- TDOmode and XOmode excluded from register tying to prevent
incorrect cross-class allocation
3. Register Allocation:
- Integrated DMR_REGS into the register class hierarchy
- Added to register pressure classes for optimal allocation
- Implements proper register allocation ordering
- DMR registers can be allocated for XOmode and TDOmode values
4. Addressing and Memory Operations:
- Supports offset addressing mode for TDOmode values
- Implements secondary reload mechanisms for DMR ↔ VSX transfers
- New rs6000_dmr_register_move_cost helper computes move costs
between a DMR register and any register class via VSX:
XOmode costs 2, TDOmode costs 4, other modes scale by nregs
- Ensures proper alignment requirements (vector alignment)
- rs6000_register_move_cost and rs6000_memory_move_cost extended
to handle DMR_REGS as source or destination
5. Register Moves and Transfers:
- Enables simple moves between DMR and VSX registers
6. Debugging and Toolchain Support:
- Assigns debugger register numbers 112-119 for DMR registers
Fold `(x == CST) ? x : CST` and `(x != CST) ? CST : x` to `CST` for
integral scalar and vector types. This catches cases where earlier
folding has converted bitwise mask expressions into conditional selects,
including ARM MVE predicate-to-vector mask forms.
James K. Lowden [Tue, 21 Jul 2026 19:41:21 +0000 (15:41 -0400)]
cobol: Enable Bison parser stack growth.
Work around a Bison error when compiling C output with a C++ compiler.
Although the Bison manual states that a user-defined location type
must be trivially copyable, it nevertheless normally does not emit
stack-growth logic if __cplusplus is defined to the preprocessor.
Consequently a large program that drives the stack above 200 elements
aborts with a "memory exhausted" error.
To enable stack growth, define the undocumented YYLTYPE_IS_TRIVIAL
variable. Use a static assert to ensure the type meets the
requirement.
A patch was submitted to the Bison project that hopefully will make
this workaround unnecessary sometime mid-century.
Which is nice, but the whilelo in the pre-header is unneeded. Due to the
architecturally defined minimum and maximum vector lengths[1] we know that at
any vector length the predicate is an all lanes active predicate, i.e. p7 is
always ptrue.
We can use gimple-isel these days while we still have range information on
the operands of .WHILE_ULTs to do this folding.
As such this patch folds whenever possible WHILE_ULTs into ptrue which are
cheaper to execute and so lowers our costs for entering the loops. i.e. the
above generates:
Tamar Christina [Tue, 21 Jul 2026 19:48:39 +0000 (20:48 +0100)]
AArch64: Move SVE ptrue VL folding helpers
The 3rd patch in this series will modify these functions, but I have to re-order
and extract some shared functionality to avoid duplicate and having to forward
declare stuff.
I thus separated out the refactoring bit from the parts that use and change
these functions.
The successive modifications made to 'xtensa_legitimize_address()' have
worsened the readability of the code, and the modifications themselves
are difficult to understand.
Therefore, this patch resolves these issues by completely rewriting the
function to make its intent clear.
gcc/ChangeLog:
* config/xtensa/xtensa.cc (xtensa_legitimize_address):
Completely rewrite it into an equivalent but more easily under-
standable description.
When the Windowed Register Option (TARGET_WINDOWED_ABI) is enabled, and this
macro is not defined, "phantom" DF livenesses occurs in the function epilogue,
which can hinder certain optimizations. Indeed, in the following example,
the low-overhead loop optimization is rejected because the epilogue BB, which
succeeds the target loop BB, is incorrectly identified as using the loop
iterator.
/* example */
void test(char *q, const char *p, unsigned int n) {
do
*q = *p, ++q, ++p;
while (n-- != 1);
}
Tamar Christina [Tue, 21 Jul 2026 19:46:33 +0000 (20:46 +0100)]
vect: replace usages of SLP_TREE_SCALAR_SMTS where possible
Continuing the work started in GCC 12 with g:a0dae768c6f78eba
this patch replaces uses of SLP_TREE_SCALAR_STMTS with SLP_TREE_LANES when used
to determine the number of lanes in the SLP tree. This de-couples the need to
have the same number of scalar statements as lanes in the SLP tree.
gcc/ChangeLog:
* tree-vect-slp-patterns.cc (compatible_complex_nodes_p): Support
mismatched group sizes and use group size to iterate.
* tree-vect-slp.cc (vect_build_slp_instance,
vect_analyze_slp_reduc_chain, vect_analyze_slp_reduction,
vect_analyze_slp_reduction_group, vect_analyze_slp_instance,
vect_analyze_slp): Compare against lanes instead of .length ().
(vect_optimize_slp_pass::get_result_with_layout): replace .length ()
with .exist ().
(vect_transform_slp_perm_load_1): Use lanes instead of .length ().
(vect_remove_slp_scalar_calls): Replace iterators.
* tree-vect-stmts.cc (vectorizable_shift): Use group size over ops
length.
Thomas Koenig [Tue, 21 Jul 2026 17:04:48 +0000 (19:04 +0200)]
Fix a few false positive warnings with unused/undefined warnings.
Trying out the new warnings on actual code found a new false positives.
The charlen of an ALLOCATE was not marked as used, the expression
in SELECT CASE was not marked as used and host-associated variables
were not exempt from testing.
All fixed with the attached patch.
gcc/fortran/ChangeLog:
PR fortran/126333
* resolve.cc (resolve_allocate_deallocate): Resolve charlen of ts
and set as used if present.
(resolve_select): Mark code->expr1 as used.
(find_unused_vs_set): Do not complain about host-associated
variables which are not marked private.
gcc/testsuite/ChangeLog:
PR fortran/126333
* gfortran.dg/warn_undefined_vars_8.f90: New test.
* gfortran.dg/warn_undefined_vars_9.f90: New test.
* gfortran.dg/warn_unused_but_set_variable_5.f90: New test.
Add a new %W print modifier to print_operand that prints the VSX
register number plus two.
Some future Power instruction patterns require printing two VSX
registers corresponding to a __vector_pair operand. The existing
%x print modifier emits the first VSX register using VSX register
numbering. Add a new %W print modifier to emit the second VSX
register of the pair.
Pan Li [Mon, 20 Jul 2026 05:38:42 +0000 (13:38 +0800)]
RISC-V: Add test cases for vfwcvt.f.xu.v reg overlap overlap
Add test cases for vfwcvt.f.xu.v register group overlap, please
note it is not overlap as much as possible.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u16-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u32-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_xu-u8-mf8.c: New test.
Pan Li [Mon, 20 Jul 2026 05:35:43 +0000 (13:35 +0800)]
RISC-V: Add test cases for vfwcvt.f.x.v reg overlap
Add test cases for vfwcvt.f.x.v register group overlap, please
note it is not overlap as much as possible.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m1.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf2.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf4.c: New test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf8.c: New test.
out-of-SSA: Preserve storage for split partition decls [PR126341]
create_tmp_var_raw marks a replacement declaration as ignored. At -O0,
this can change use_register_for_decl from memory for the original user
declaration to a pseudo for the replacement. A partition can already own
memory from a parameter default definition, which then makes set_rtl reject
that memory for another name in the partition.
If the replacement would use a register, copy DECL_IGNORED_P so it keeps the
storage choice made during coalescing. Keep declarations that already use
memory unchanged. Add a checking assertion for the memory invariant.
Bootstrapped and tested on aarch64-none-linux-gnu and x86_64-linux.
gcc/ChangeLog:
PR middle-end/126341
* tree-outof-ssa.cc (split_overlapping_partition_decls): Preserve
DECL_IGNORED_P. Check that the replacement uses memory.
gcc/testsuite/ChangeLog:
PR middle-end/126341
* gcc.dg/pr126341.c: New test.
AVR: Add 64-bit fixed-point multiplications to libgcc.
This patch adds (un)saturated 64-bit fixed-point multiplications
to libgcc. The saturating functions are just aliases of the
vanilla versions, which are also saturating.
projects / thirdparty / gcc.git / log
