Paul Spooren [Tue, 16 Jun 2026 09:24:16 +0000 (11:24 +0200)]
button-hotplug: bump package release
This commit fixes "286f377389a button-hotplug: add KEY_SETUP and KEY_VENDOR
handling" which changed the code without bumping the PKG_RELEASE, resulting in
different binaries under the same version.
Paul Spooren [Tue, 16 Jun 2026 09:20:05 +0000 (11:20 +0200)]
mtd: bump package release
This commit fixes "a5107ad58c6 mtd: fix buffer leak and fd leak in mtd_dump()"
which changed the code but did not increase the release. This causes two
packages with the same version to have different content and thereby hashes.
Ahmed Naseef [Thu, 11 Jun 2026 14:19:40 +0000 (18:19 +0400)]
econet: update patches for 6.18
Fix patch compatibility for kernel 6.18 on econet and refresh with
`make target/linux/refresh V=s`. The shared airoha clk/spi/uart and the
econet-local timer, nand and phy patches are rebased onto the 6.18
upstream code.
Ahmed Naseef [Thu, 11 Jun 2026 14:19:00 +0000 (18:19 +0400)]
econet: remove upstreamed patches for 6.18
Remove all patches that have already been upstreamed for kernel 6.18.
The remaining v6.19/v6.19rc1 backports are kept, in sync with the airoha
target these patches are shared with.
Ahmed Naseef [Thu, 11 Jun 2026 13:05:21 +0000 (17:05 +0400)]
kernel/econet: restore files for v6.12
This is an automatically generated commit which aids following Kernel patch
history, as git will see the move and copy as a rename thus defeating the
purpose.
For the original discussion see:
https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
Ryan Leung [Thu, 21 May 2026 05:31:31 +0000 (15:31 +1000)]
uboot-mediatek: enable true RNG driver for recently added devices
Enable the hardware true random number generator driver added in 2a9dce2d9e81 ("uboot-mediatek: port RNG drivers and enable them")
for recently added devices.
Daniel Tang [Sun, 5 Oct 2025 23:32:30 +0000 (23:32 +0000)]
realtek: add support for V3 variant of SG2008P
Add basic support for the TP-Link SG2008P V3 variant. The switch appears
to be identical to the V1 variant, except that it uses the MP3924
instead of the TPS23861 PoE chip.
Specifications:
---------------
* SoC: Realtek RTL8380M
* Flash: 32 MiB SPI flash (Vendor varies)
* RAM: 256 MiB (Vendor varies)
* Ethernet: 8x 10/100/1000 Mbps with PoE on 4 ports
* Buttons: 1x "Reset" button on front panel
* Power: 53.5V DC barrel jack
* UART: 1x serial header, unpopulated
* PoE: 1x MPS MP3924 I2C PoE controller
Works:
------
- (8) RJ-45 ethernet ports
- Switch functions
- System LED
- Basic PoE support (no driver, but a startup script puts the chip
into AUTO mode)
Not yet enabled:
----------------
- PoE, Link/Act, PoE max and System LEDs
Install via web interface:
-------------------------
Not supported at this time.
Install via serial console/tftp:
--------------------------------
The footprints R27 (0201) and R28 (0402) are not populated. To enable
serial console, 50 ohm resistors should be soldered -- any value from
0 ohm to 50 ohm will work. R27 can be replaced by a solder bridge.
The u-boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.
Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. The sysupgrade image can also be flashed. To install OpenWRT:
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
Power on device, and stop boot by pressing any key.
Once the shell is active:
1. Ground out the CLK (pin 16) of the ROM (U7)
2. Select option "3. Start"
3. Bootloader notes that "The kernel has been damaged!"
4. Release CLK as sson as bootloader thinks image is corrupted.
5. Bootloader enters automatic recovery -- details printed on console
6. Watch as the bootloader flashes and boots OpenWRT.
Blind install via tftp:
-----------------------
This method works when it's not feasible to install a serial header.
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
3. Watch network traffic (tcpdump or wireshark works)
4. Power on the device.
5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U7)
6. When 192.168.0.30 makes tftp requests, release pin 16
7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT
Hauke Mehrtens [Mon, 15 Jun 2026 23:39:41 +0000 (01:39 +0200)]
uhttpd: update to Git HEAD (2026-06-16)
ae015e099986 client: reject unhandled Transfer-Encoding values b78f51847879 client: close connection on invalid chunk length 7b1bec45826b ubus: close connection on POST body parse error
Hauke Mehrtens [Fri, 12 Jun 2026 22:34:46 +0000 (00:34 +0200)]
ead: fix integer underflow in handle_send_a()
handle_send_a() computed the SRP "A" parameter length as
len = ntohl(msg->len) - sizeof(struct ead_msg_number);
sizeof(struct ead_msg_number) is 1, and the subtraction is evaluated in
unsigned arithmetic. A packet with msg->len == 0 therefore wraps the
result to a huge value which, assigned to the signed int len, becomes -1.
The following bounds check is signed:
if (len > MAXPARAMLEN + 1)
return false;
so -1 passes, and memcpy(A.data, number->data, len) runs with len cast to
size_t (~SIZE_MAX) against the 257-byte abuf, crashing the daemon.
Neither parse_message() nor handle_packet() validate msg->len (only the
captured packet length), so an unauthenticated attacker on the local
segment can reach this path and crash ead with a single crafted packet.
Validate the claimed length in unsigned arithmetic before the subtraction
and bound it on both sides. Doing the upper-bound check unsigned as well
also closes a 32-bit-only variant where sizeof(ead_packet) + msg->len
overflows in handle_packet(), letting a large msg->len reach the same
negative-len path.
Hauke Mehrtens [Fri, 12 Jun 2026 23:17:23 +0000 (01:17 +0200)]
fritz-tools: fix out-of-bounds memset in TFFS segment expansion
When growing the segment array in find_entry(), the memset() that zeroes
the newly allocated slots computed the destination with redundant sizeof
scaling:
segments is a typed pointer, so pointer arithmetic already scales by the
element size. Multiplying the offset by sizeof again advances the
destination by num_segments * sizeof^2 bytes, landing far outside the
realloc()'d buffer and zeroing unrelated heap memory whenever a TFFS
entry spans multiple segments that require array expansion.
Drop the redundant multiplication so the memset targets segments[num_segments].
This is a robustness fix for malformed/corrupt TFFS content; the parser
only reads the on-device nand-tffs MTD partition as root, so it is not
considered security relevant.
Rosen Penev [Sat, 13 Jun 2026 18:30:18 +0000 (11:30 -0700)]
mac80211: backport ath9k memset fixes from upstream
Backport two upstream commits that replace memset() on coherent DMA
descriptor rings with explicit WRITE_ONCE() status word stores.
On 32-bit PowerPC platforms like apm821xx, coherent DMA memory may be
mapped uncached. The optimized memset() path can use dcbz there, which
triggers alignment warnings and spams the kernel log.
Carlo Szelinsky [Tue, 9 Jun 2026 20:58:59 +0000 (22:58 +0200)]
realtek: add hasivo-mcu sensor driver
Add a temperature/fan sensor (hwmon) driver for the Hasivo / Horaco
management MCU as a second child of the hasivo MCU MFD (alongside the
watchdog). It exposes the CPU and system temperatures and a 3-state fan
control (auto / force-on / force-off), read/written through the parent's
shared syscon regmap.
The register protocol was reverse-engineered from the stock 'imi' firmware
and verified on hardware. The fan-status register (0xFB) reflects the MCU's
effective drive state, not actual rotation (a blocked fan still reads
force-on), so no fanN_alarm is exposed. pwm1 echoes the commanded state so
a write reads back consistently, and falls back to the live drive state in
automatic mode. The register map is shared across boards.
Carlo Szelinsky [Sun, 7 Jun 2026 17:56:51 +0000 (19:56 +0200)]
realtek: convert hasivo-mcu-wdt to a hasivo-mcu-mfd child
The watchdog and the temperature/fan hwmon are the same management MCU at
a single I2C address (0x6f). Linux binds one driver per I2C client, so the
watchdog cannot keep owning the address directly if the hwmon is to live
on the same chip. Convert it from a standalone i2c_driver into a
platform_driver child of the hasivo MCU MFD that reaches the chip through
the parent's shared regmap (syscon), and depend on kmod-mfd-hasivo-stc8.
Add the mandatory activate/deactivate bring-up hooks to rtpcs_sds_ops
and let rtpcs_pcs_config() drive the full sequence around the variant
configuration:
The per-variant calls that were open-coded at the start and end of the
setup_serdes() functions are removed in favour of these indirections.
RTL839X never powered the SerDes down/up, so it gets no-op stubs to
satisfy the contract for now. Execution order is preserved for all
variants.
Jonas Jelonek [Sat, 6 Jun 2026 21:51:47 +0000 (21:51 +0000)]
realtek: pcs: add post_config sds_ops hook
Some variants need finalization that must run only after the SerDes is
powered up: RTL838X performs a one-shot switch queue reset on first
start, RTL930X runs RX calibration and the TX config. So far this lived
at the tail of the variant setup_serdes() functions.
Add an optional post_config hook to rtpcs_sds_ops and call it from
rtpcs_pcs_config() right after setup_serdes(), then relocate the
RTL838X and RTL930X tail work into it. As activate() still runs at the
end of setup_serdes() here, the execution order is unchanged.
Jonas Jelonek [Thu, 11 Jun 2026 20:05:28 +0000 (20:05 +0000)]
realtek: pcs: rtl930x: apply tx config before activation
In RTL930x setup, tx config was called at then end of the procedure
after configuration and calibration ran. This is still a leftover from
the old code located in DSA/PHY. However, applying TX configuration like
amplification factors, etc. doesn't make sense after calibration, it
should run before. Moreover the call was commented with "leave loopback
mode" which is just wrong and doesn't describe what the function does.
Fix this misery.
Testing on device with different interface modes shows no difference so
far, especially no negative effects.
Ryan Leung [Sat, 6 Jun 2026 11:19:46 +0000 (19:19 +0800)]
mediatek: wavlink wl-wn536ax6 rev a: add "network" LED trigger
Currently the "WiFi" LED indicator light is triggered only by activity on the 5 GHz PHY.
Change it to be triggered by WLAN activity on either Wi-Fi PHY, matching stock behaviour, by using
`kmod-ledtrig-network` added in 2aa1185fb05e ('leds: add "network" LED trigger (lan/wan/wlan)').
Ryan Leung [Sat, 6 Jun 2026 11:19:24 +0000 (19:19 +0800)]
mediatek: wavlink wl-wn536ax6 rev a: fix WLAN 5GHz MAC address
The second WLAN MAC address in the "Factory" partition at 0x0a is not the same as the
WLAN 5GHz BSSID observed when using the manufacturer's stock firmware, which is derived from
the 2.4GHz/label MAC address by setting bits 26 and 7 (Locally Administered).
While at it, also fix alphabetical ordering of some other device names.
Fixes: 1748ce829537 ("mediatek: add support for WAVLINK WL-WN536AX6 Rev a") Signed-off-by: Ryan Leung <untilscour@protonmail.com> Link: https://github.com/openwrt/openwrt/pull/23682 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Ryan Leung [Sat, 6 Jun 2026 11:19:12 +0000 (19:19 +0800)]
mediatek: wavlink wl-wn536ax6 rev a: change nvmem layout for MAC addresses
Currently the WAN MAC address is read from the first (LAN) MAC address in the "HW" partition and
then incremented by 1 instead of being read directly from the second MAC address.
Change to reading the two MAC addresses (LAN/WAN) directly from "Factory" partition.
Fixes: 1748ce829537 ("mediatek: add support for WAVLINK WL-WN536AX6 Rev a") Signed-off-by: Ryan Leung <untilscour@protonmail.com> Link: https://github.com/openwrt/openwrt/pull/23682 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Ryan Leung [Sat, 6 Jun 2026 11:18:45 +0000 (19:18 +0800)]
mediatek: wavlink wl-wn536ax6 rev a: enable nmbm bad block management
Enable nmbm bad block management with up to 8 MiB reserved. The manufacturer's stock device tree
contains the property `compatible = "generic,nmbm";` in node `nmbm_spim_nand` and
manufacturer's stock bootlog contains "nmbm nmbm_spim_nand: NMBM has been successfully attached"
Fixes: 1748ce829537 ("mediatek: add support for WAVLINK WL-WN536AX6 Rev a") Signed-off-by: Ryan Leung <untilscour@protonmail.com> Link: https://github.com/openwrt/openwrt/pull/23682 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Qingfang Deng [Thu, 21 May 2026 01:53:46 +0000 (09:53 +0800)]
kernel: modules: mppe: clean up
Remove kmod-crypto-arc4 and kmod-crypto-ecb from depends, as it no
longer uses skcipher API for encryption.
Remove the non-existent CONFIG_PPP_MPPE_MPPC symbol.
In previous versions of OpenWrt, ethernet was partially working,
sometimes depending on initialization state left by bootloader.
Since the switch to NSS drivers, it is completely broken.
- swap GMAC to PHY address mapping
- use rgmii internal delay
- drop `fixed-link` rates
- add pinctrl settings for rgmii0
- declare reset GPIO 51 (used for both PHYs)
- disable hibernation
Paul Spooren [Fri, 12 Jun 2026 14:49:44 +0000 (16:49 +0200)]
build: fixup version.date creation for source archives
Published sources archives may contain a mixture of MTIMEs, so taking the time
of the first file found varies based on filesystem order. To fix this, sort all
MTIMEs and take the latest.
Since piping into a file directly creates that file, we also need to
specifically tell `find` to ignore `version.date`.
Furthermore, move this prior to the ./src copy step, since for some packages,
the OpenWrt build system ships extra ./src files, which would introduce the
wrong timestamps again.
generic: mxl862xx: allow CPU/SerDes ports to probe on firmware < 1.0.84
The firmware-version gate in mxl862xx_phylink_get_caps() leaves
config->supported_interfaces empty for the CPU/SerDes ports (9, 13) when
the switch runs firmware older than 1.0.84. phylink rejects an empty
supported_interfaces bitmap, so the switch fails to probe at all:
mxl862xx mdio-bus:10: switch ready after 2480ms, firmware 1.0.70 (build 70)
mxl862xx mdio-bus:10: phylink: error: empty supported_interfaces
error creating PHYLINK: -22
mxl862xx mdio-bus:10: probe with driver mxl862xx failed with error -22
This regresses boards still shipping the older vendor firmware (e.g. the
BananaPi BPi-R4 Pro 8X, which ships 1.0.70) where all LAN ports disappear.
Ungate only the CPU/SerDes ports (9, 13) so the switch probes and the user
can update the firmware; ports 10..12 and 14..16 stay gated as they are
genuinely unsupported by the old firmware.
Tested on a BPi-R4 Pro 8X with switch firmware 1.0.70 (kernel 6.18); the
6.12 patch receives the identical change for parity.
Michał Kępień [Fri, 12 Jun 2026 07:28:03 +0000 (09:28 +0200)]
ath79: mikrotik: also compile AG71XX_LEGACY as a module
Commit 9091c9f8cbd9 ("ath79: mikrotik: compile SWCONFIG and AR8216_PHY
as modules") caused the hybrid PHY/MDIO ar8xxx driver to be built as a
module instead of built-in. On at least MikroTik RouterBOARD 951G-2HnD,
this prevents the kernel from binding the correct PHY driver at boot
because the ar8xxx driver is not yet available when the MDIO bus is
probed:
- before:
ag71xx-legacy 19000000.eth: invalid MAC address, using random address
switch0: Atheros AR8327 rev. 4 switch registered on mdio.0
ag71xx-legacy 19000000.eth: connected to PHY at mdio.0:00 [uid=004dd034, driver=Atheros AR8216/AR8236/AR8316]
eth0: Atheros AG71xx at 0xb9000000, irq 4, mode: rgmii
- after:
ag71xx-legacy 19000000.eth: invalid MAC address, using random address
ag71xx-legacy 19000000.eth: connected to PHY at mdio.0:00 [uid=004dd034, driver=Generic PHY]
eth0: Atheros AG71xx at 0xb9000000, irq 4, mode: rgmii
As the PHY is already bound to the fallback "Generic PHY" driver when
the ar8xxx module is loaded, the switch remains non-functional and the
router has no network connectivity.
Fix by also compiling the MAC driver (ag71xx-legacy) as a module,
deferring switch initialization until control is transferred to
userspace during boot. The configured module autoload priorities
(ar8xxx: 43, ag71xx-legacy: 50) ensure that the ar8xxx driver is loaded
before ag71xx-legacy.
Fixes: https://github.com/openwrt/openwrt/issues/23739 Fixes: 9091c9f8cbd9 ("ath79: mikrotik: compile SWCONFIG and AR8216_PHY as modules") Suggested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Michał Kępień <openwrt@kempniu.pl> Link: https://github.com/openwrt/openwrt/pull/23748 Signed-off-by: Robert Marko <robimarko@gmail.com>
Jonas Jelonek [Thu, 11 Jun 2026 22:05:16 +0000 (22:05 +0000)]
realtek: pcs: rtl838x: drop redundant reset writes
Sometimes redundancy is so obvious that one likely misses it. Trying to
bring all SerDes setup into a unified shape, one thinks twice if
something is really needed or not.
For the RTL838x case, the single writes for take/release reset were still
an outlier. Looking closer at them one can see that the same bits are all
covered already in deactivate/activate. So before, they have been put
into the desired state but those outlier writes mess with them again.
[0, 3, 0x7146/0x7106] just deals with the SOFT_RST bit that is already
covered by rtpcs_838x_sds_reset.
[0, 0, 0xc00] touches multiple bits, amongst the EN_RX/EN_TX bits
already covered in deactivate/active. Moreover, it potentially forces
other bits into a state causing broken functionality, e.g.
INV_HSI/INV_HSO which deal with the polarity. This has no effect right
no right now but might be a latent issue in the future.
Also move the reset call down to the end of the function, doing a
soft/RX reset after every configuration is done. This is likely what the
SDK also intended, and mirrors the 839x behavior.
Jonas Jelonek [Thu, 11 Jun 2026 18:40:32 +0000 (18:40 +0000)]
realtek: pcs: rtl838x: replace literal with macro
Replace 0 with MII_BMCR because in this context, it maps cleanly to
normal PHY register structure. BMCR_PDOWN is already used there to show
which bits are set.
Jonas Jelonek [Sat, 6 Jun 2026 21:03:07 +0000 (21:03 +0000)]
realtek: pcs: rtl838x: merge and simplify patching
Reduce the per-SerDes patching to a per-mode patching since they share a
lot of similarities, especially for QSGMII.
For fiber patching, the differences are bigger. This takes an approach
to merge the sequences completely despite applying some settings which
weren't applied before on one of the SerDes. Testing and SerDes dumps
showed no or minimal differences, and no practical effect on
functionality. A look at the SerDes register documentation we have shows
reordering the writes isn't problematic because most of the bits aren't
any trigger bits.
With all its users gone, we can now drop also the workaround SDS macro.
Jonas Jelonek [Thu, 11 Jun 2026 08:28:27 +0000 (08:28 +0000)]
realtek: pcs: rtl838x: carve out writes for SerDes 0/1
For an attempt to simplify and reduce patching, carve out two special
writes for SerDes 0/1. While their exact purpose isn't fully known, they
need to match to make QSGMII on those two SerDes work. In order to be
able to merge the per-SerDes QSGMII patching sequences, carve them out
to the patching function one level above.
Jonas Jelonek [Sat, 6 Jun 2026 19:17:32 +0000 (19:17 +0000)]
realtek: pcs: rtl838x: set mode after patching
In order to have a unified SerDes setup sequence, align RTL838x to all
other variants. Set the mode after patching has been applied. Testing on
devices showed the order is rather irrelevant.
Jonas Jelonek [Wed, 22 Apr 2026 13:54:15 +0000 (13:54 +0000)]
realtek: pcs: rtl838x: fold lane enables and fiber path into {de,}activate
Expand the 838x deactivate/activate helpers to also cover the analog lane
enables (REG0 EN_RX/EN_TX) and the fiber path power-down (FIB_REG0
CFG_FIB_PDOWN), which are operational-state concerns rather than reset
concerns:
- _deactivate: clear EN_RX/EN_TX and set CFG_FIB_PDOWN in addition to
block-level power off.
- _activate: clear CFG_FIB_PDOWN and set EN_RX/EN_TX before block-level
power on. The pulse-start EN=0 is omitted since _deactivate already
established EN=0 and nothing in between touches REG0[1:0].
Shrink rtpcs_838x_sds_reset() accordingly: it now owns only the SOFT_RST
toggle, making it a pure digital reset primitive. The stale "SerDes %d
reset" dev_info was dropped along with the analog/fiber writes.
Behavioural note: the EN and FIB_PDOWN writes now happen *after* the
SOFT_RST release inside rtpcs_838x_sds_reset(), rather than before it as
in the old combined sds_reset. This creates a brief window where the
SerDes is out of digital reset with lanes still disabled, before
activate re-enables them. Consistent with the new
power_off/deactivate -> configure -> reset -> activate/power_on phase
structure, but diverges from the SDK ordering (EN pulse before SOFT_RST
release). Testing on real hardware shows no difference.
Backport several fixes and enhancements for the rtl8365mb DSA driver
from upstream.
The backport includes the following changes:
- Fix for rtl8_4 tag (from v7.1)
- VLAN and Forwarding offload (from v7.2)
Before this backport, all bridge forwarding was handled by the CPU,
causing a significant performance drop between LAN ports, similar
to standard WAN/LAN routing. Enabling hardware forwarding offload
alleviates CPU overhead and restores line-rate switching performance.
Shine [Sun, 31 May 2026 13:16:09 +0000 (15:16 +0200)]
scripts: dhcp/dhcpv6: handling of invalid client ID values
Verify and clean up client ID and global DUID config values before use, in
order to prevent DHCP client malfunction and loss of IPv4 and/or IPv6
connectivity.
- Accept common separators in the string (colon, dash, spaces/tabs, lf)
- Ignore invalid values (non-hex or odd-numbered length)
- Log a warning for invalid settings
The fall back mechanism is as follows:
If a (user-configured) network.<ifname>.clientid setting is found invalid,
ignore and fall back to using network.globals.dhcp_default_duid. In case
that's also invalid (e.g. has been tampered with), don't pass a client
ID to updhc/odhcpc. In that case, udhcpc/odhcpc will use their defaults,
which currently is the i/f MAC address resp. the i/f DUID-LL.
Only error handling is introduced, no behavior change for valid settings.
projects / thirdparty / openwrt.git / log
