]> git.ipfire.org Git - thirdparty/qemu.git/log
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2 years agotarget/mips: Populate CPUClass.mmu_index
Richard Henderson [Sun, 28 Jan 2024 23:46:54 +0000 (09:46 +1000)] 
target/mips: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/mips: Split out mips_env_mmu_index
Richard Henderson [Sun, 28 Jan 2024 06:00:39 +0000 (16:00 +1000)] 
target/mips: Split out mips_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill
Richard Henderson [Sun, 28 Jan 2024 05:58:52 +0000 (15:58 +1000)] 
target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill

Rather than adjust env->hflags so that the value computed
by cpu_mmu_index() changes, compute the mmu_idx that we
want directly and pass it down.

Introduce symbolic constants for MMU_{KERNEL,ERL}_IDX.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/microblaze: Populate CPUClass.mmu_index
Richard Henderson [Sun, 28 Jan 2024 23:44:10 +0000 (09:44 +1000)] 
target/microblaze: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/m68k: Populate CPUClass.mmu_index
Richard Henderson [Sun, 28 Jan 2024 23:38:31 +0000 (09:38 +1000)] 
target/m68k: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/loongarch: Rename MMU_IDX_*
Richard Henderson [Fri, 2 Feb 2024 05:49:51 +0000 (15:49 +1000)] 
target/loongarch: Rename MMU_IDX_*

The expected form is MMU_FOO_IDX, not MMU_IDX_FOO.
Rename to match generic code.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/loongarch: Populate CPUClass.mmu_index
Richard Henderson [Fri, 2 Feb 2024 05:49:50 +0000 (15:49 +1000)] 
target/loongarch: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/i386: Populate CPUClass.mmu_index
Richard Henderson [Sun, 28 Jan 2024 23:31:15 +0000 (09:31 +1000)] 
target/i386: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/hppa: Populate CPUClass.mmu_index
Richard Henderson [Sun, 28 Jan 2024 23:22:51 +0000 (09:22 +1000)] 
target/hppa: Populate CPUClass.mmu_index

Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/cris: Populate CPUClass.mmu_index
Richard Henderson [Sun, 28 Jan 2024 23:17:09 +0000 (09:17 +1000)] 
target/cris: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/cris: Cache mem_index in DisasContext
Richard Henderson [Sun, 28 Jan 2024 05:05:06 +0000 (15:05 +1000)] 
target/cris: Cache mem_index in DisasContext

Compute this value once for each translation.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/avr: Populate CPUClass.mmu_index
Richard Henderson [Sun, 28 Jan 2024 23:12:17 +0000 (09:12 +1000)] 
target/avr: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/arm: Populate CPUClass.mmu_index
Richard Henderson [Sun, 28 Jan 2024 23:08:57 +0000 (09:08 +1000)] 
target/arm: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/arm: Split out arm_env_mmu_index
Richard Henderson [Sun, 28 Jan 2024 04:56:54 +0000 (14:56 +1000)] 
target/arm: Split out arm_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/alpha: Populate CPUClass.mmu_index
Richard Henderson [Sun, 28 Jan 2024 22:53:49 +0000 (08:53 +1000)] 
target/alpha: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/alpha: Split out alpha_env_mmu_index
Richard Henderson [Sun, 28 Jan 2024 04:47:19 +0000 (14:47 +1000)] 
target/alpha: Split out alpha_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agoinclude/hw/core: Add mmu_index to CPUClass
Richard Henderson [Sun, 28 Jan 2024 22:47:40 +0000 (08:47 +1000)] 
include/hw/core: Add mmu_index to CPUClass

To be used after all targets have populated the hook.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 years agoMerge tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu...
Peter Maydell [Fri, 2 Feb 2024 18:56:32 +0000 (18:56 +0000)] 
Merge tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target/arm: fix exception syndrome for AArch32 bkpt insn
pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset
system/vl.c: Fix handling of '-serial none -serial something'
target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array
target/arm: Reinstate "vfp" property on AArch32 CPUs
doc/sphinx/hxtool.py: add optional label argument to SRST directive
hw/arm: Check for CPU types in machine_run_board_init() for various boards
pci-host: designware: Limit value range of iATU viewport register
hw/arm: Convert some DPRINTF macros to trace events and guest errors
hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices
hw/arm: Implement BCM2835 SPI Controller

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# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits)
  hw/arm: Connect SPI Controller to BCM2835
  hw/ssi: Implement BCM2835 SPI Controller
  tests/qtest: Adding PCS Module test to GMAC Qtest
  hw/net: GMAC Tx Implementation
  hw/net: GMAC Rx Implementation
  tests/qtest: Creating qtest for GMAC Module
  hw/arm: Add GMAC devices to NPCM7XX SoC
  hw/net: Add NPCMXXX GMAC device
  hw/xen: convert stderr prints to error/warn reports
  hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints
  hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints
  hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports
  hw/arm/z2: convert DPRINTF to trace events and guest errors
  hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors
  pci-host: designware: Limit value range of iATU viewport register
  hw/arm/zynq: Check for CPU types in machine_run_board_init()
  hw/arm/vexpress: Check for CPU types in machine_run_board_init()
  hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[]
  hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[]
  hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[]
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge tag 'pull-nic-config-2-20240202' of git://git.infradead.org/users/dwmw2/qemu...
Peter Maydell [Fri, 2 Feb 2024 16:47:36 +0000 (16:47 +0000)] 
Merge tag 'pull-nic-config-2-20240202' of git://git.infradead.org/users/dwmw2/qemu into staging

Rework matching of network devices to -nic options (v2)

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# gpg:                issuer "dwmw@amazon.co.uk"
# gpg: Good signature from "David Woodhouse <dwmw@amazon.co.uk>" [unknown]
# gpg:                 aka "David Woodhouse <dwmw@amazon.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 314B 08AC D0DE 4811 33A5  F286 9BE9 80FD 0AC0 1544

* tag 'pull-nic-config-2-20240202' of git://git.infradead.org/users/dwmw2/qemu: (47 commits)
  net: make nb_nics and nd_table[] static in net/net.c
  net: remove qemu_show_nic_models(), qemu_find_nic_model()
  hw/pci: remove pci_nic_init_nofail()
  net: remove qemu_check_nic_model()
  hw/xtensa/xtfpga: use qemu_create_nic_device()
  hw/sparc/sun4m: use qemu_find_nic_info()
  hw/s390x/s390-virtio-ccw: use qemu_create_nic_device()
  hw/riscv: use qemu_configure_nic_device()
  hw/openrisc/openrisc_sim: use qemu_create_nic_device()
  hw/net/lasi_i82596: use qemu_create_nic_device()
  hw/net/lasi_i82596: Re-enable build
  hw/mips/jazz: use qemu_find_nic_info()
  hw/mips/mipssim: use qemu_create_nic_device()
  hw/microblaze: use qemu_configure_nic_device()
  hw/m68k/q800: use qemu_find_nic_info()
  hw/m68k/mcf5208: use qemu_create_nic_device()
  hw/net/etraxfs-eth: use qemu_configure_nic_device()
  hw/arm: use qemu_configure_nic_device()
  hw/arm/stellaris: use qemu_find_nic_info()
  hw/arm/npcm7xx: use qemu_configure_nic_device, allow emc0/emc1 as aliases
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agonet: make nb_nics and nd_table[] static in net/net.c
David Woodhouse [Mon, 23 Oct 2023 08:38:01 +0000 (09:38 +0100)] 
net: make nb_nics and nd_table[] static in net/net.c

Also remove the stale declaration of host_net_devices; the actual
definition was removed long ago in commit 7cc28cb06104 ("net: Remove
the deprecated 'host_net_add' and 'host_net_remove' HMP commands")

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agonet: remove qemu_show_nic_models(), qemu_find_nic_model()
David Woodhouse [Mon, 23 Oct 2023 08:38:00 +0000 (09:38 +0100)] 
net: remove qemu_show_nic_models(), qemu_find_nic_model()

These old functions can be removed now too. Let net_param_nic() print
the full set of network devices directly, and also make it note that a
list more specific to this platform/config will be available by using
'-nic model=help' instead.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/pci: remove pci_nic_init_nofail()
David Woodhouse [Mon, 23 Oct 2023 08:37:59 +0000 (09:37 +0100)] 
hw/pci: remove pci_nic_init_nofail()

This function is no longer used, as all its callers have been converted
to use pci_init_nic_devices() instead.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agonet: remove qemu_check_nic_model()
David Woodhouse [Mon, 23 Oct 2023 08:37:58 +0000 (09:37 +0100)] 
net: remove qemu_check_nic_model()

There are no callers of this function any more, as they have all been
converted to qemu_{create,configure}_nic_device().

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/xtensa/xtfpga: use qemu_create_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:56 +0000 (09:37 +0100)] 
hw/xtensa/xtfpga: use qemu_create_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/sparc/sun4m: use qemu_find_nic_info()
David Woodhouse [Mon, 23 Oct 2023 08:37:55 +0000 (09:37 +0100)] 
hw/sparc/sun4m: use qemu_find_nic_info()

Obtain the MAC address from the NIC configuration if there is one, or
generate one explicitly so that it can be placed in the PROM.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/s390x/s390-virtio-ccw: use qemu_create_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:54 +0000 (09:37 +0100)] 
hw/s390x/s390-virtio-ccw: use qemu_create_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Acked-by: Thomas Huth <thuth@redhat.com>
2 years agohw/riscv: use qemu_configure_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:53 +0000 (09:37 +0100)] 
hw/riscv: use qemu_configure_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/openrisc/openrisc_sim: use qemu_create_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:52 +0000 (09:37 +0100)] 
hw/openrisc/openrisc_sim: use qemu_create_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/net/lasi_i82596: use qemu_create_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:50 +0000 (09:37 +0100)] 
hw/net/lasi_i82596: use qemu_create_nic_device()

Create the device only if there is a corresponding NIC config for it.
Remove the explicit check on nd_table[0].used from hw/hppa/machine.c
which (since commit d8a3220005d7) tries to do the same thing.

The lasi_82596 support has been disabled since it was first introduced,
since enable_lasi_lan() has always been zero. This allows the user to
enable it by explicitly requesting a NIC model 'lasi_82596' or just
using the alias 'lasi'. Otherwise, it defaults to a PCI NIC as before.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/net/lasi_i82596: Re-enable build
David Woodhouse [Fri, 26 Jan 2024 10:06:07 +0000 (10:06 +0000)] 
hw/net/lasi_i82596: Re-enable build

When converting to the shiny build-system-du-jour, a typo prevented the
last_i82596 driver from being built. Correct the config option name to
re-enable the build. And include "sysemu/sysemu.h" so it actually builds.

Fixes: b1419fa66558 ("meson: convert hw/net")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2144
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/mips/jazz: use qemu_find_nic_info()
David Woodhouse [Mon, 23 Oct 2023 08:37:49 +0000 (09:37 +0100)] 
hw/mips/jazz: use qemu_find_nic_info()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/mips/mipssim: use qemu_create_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:48 +0000 (09:37 +0100)] 
hw/mips/mipssim: use qemu_create_nic_device()

The MIPS SIM platform instantiates its NIC only if a corresponding
configuration exists for it. Use qemu_create_nic_device() function for
that.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/microblaze: use qemu_configure_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:47 +0000 (09:37 +0100)] 
hw/microblaze: use qemu_configure_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/m68k/q800: use qemu_find_nic_info()
David Woodhouse [Mon, 23 Oct 2023 08:37:45 +0000 (09:37 +0100)] 
hw/m68k/q800: use qemu_find_nic_info()

If a corresponding NIC configuration was found, it will have a MAC address
already assigned, so use that. Else, generate and assign a default one.

Using qemu_find_nic_info() is simpler than the alternative of using
qemu_configure_nic_device() and then having to fetch the "mac" property
as a string and convert it.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/m68k/mcf5208: use qemu_create_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:44 +0000 (09:37 +0100)] 
hw/m68k/mcf5208: use qemu_create_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/net/etraxfs-eth: use qemu_configure_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:43 +0000 (09:37 +0100)] 
hw/net/etraxfs-eth: use qemu_configure_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/arm: use qemu_configure_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:41 +0000 (09:37 +0100)] 
hw/arm: use qemu_configure_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/arm/stellaris: use qemu_find_nic_info()
David Woodhouse [Mon, 23 Oct 2023 08:37:40 +0000 (09:37 +0100)] 
hw/arm/stellaris: use qemu_find_nic_info()

Rather than just using qemu_configure_nic_device(), populate the MAC
address in the system-registers device by peeking at the NICInfo before
it's assigned to the device.

Generate the MAC address early, if there is no matching -nic option.
Otherwise the MAC address wouldn't be generated until net_client_init1()
runs.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/arm/npcm7xx: use qemu_configure_nic_device, allow emc0/emc1 as aliases
David Woodhouse [Mon, 23 Oct 2023 08:37:39 +0000 (09:37 +0100)] 
hw/arm/npcm7xx: use qemu_configure_nic_device, allow emc0/emc1 as aliases

Also update the test to specify which device to attach the test socket
to, and remove the comment lamenting the fact that we can't do so.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/arm/highbank: use qemu_create_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:37 +0000 (09:37 +0100)] 
hw/arm/highbank: use qemu_create_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/net/lan9118: use qemu_configure_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:36 +0000 (09:37 +0100)] 
hw/net/lan9118: use qemu_configure_nic_device()

Some callers instantiate the device unconditionally, others will do so only
if there is a NICInfo to go with it. This appears to be fairly random, but
preseve the existing behaviour for now.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/net/smc91c111: use qemu_configure_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:35 +0000 (09:37 +0100)] 
hw/net/smc91c111: use qemu_configure_nic_device()

Some callers instantiate the device unconditionally, others will do so only
if there is a NICInfo to go with it. This appears to be fairly random, but
preserve the existing behaviour of each caller for now.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/arm/fsl: use qemu_configure_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:34 +0000 (09:37 +0100)] 
hw/arm/fsl: use qemu_configure_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/arm/exynos4: use qemu_create_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:31 +0000 (09:37 +0100)] 
hw/arm/exynos4: use qemu_create_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/arm/aspeed: use qemu_configure_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:30 +0000 (09:37 +0100)] 
hw/arm/aspeed: use qemu_configure_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Acked-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
2 years agohw/arm/allwinner: use qemu_configure_nic_device()
David Woodhouse [Mon, 23 Oct 2023 08:37:28 +0000 (09:37 +0100)] 
hw/arm/allwinner: use qemu_configure_nic_device()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/xtensa/virt: use pci_init_nic_devices()
David Woodhouse [Mon, 23 Oct 2023 08:37:27 +0000 (09:37 +0100)] 
hw/xtensa/virt: use pci_init_nic_devices()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/sparc64/sun4u: use pci_init_nic_devices()
David Woodhouse [Mon, 23 Oct 2023 08:37:26 +0000 (09:37 +0100)] 
hw/sparc64/sun4u: use pci_init_nic_devices()

The first sunhme NIC gets placed a function 1 on slot 1 of PCI bus A,
and the rest are dynamically assigned on PCI bus B.

Previously, any PCI NIC would get the special treatment purely by
virtue of being first in the list.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/sh4/r2d: use pci_init_nic_devices()
David Woodhouse [Mon, 23 Oct 2023 08:37:23 +0000 (09:37 +0100)] 
hw/sh4/r2d: use pci_init_nic_devices()

Previously, the first PCI NIC would be assigned to slot 2 even if the
user override the model and made it something other than an rtl8139
which is the default. Everything else would be dynamically assigned.

Now, the first rtl8139 gets slot 2 and everything else is dynamic.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
2 years agohw/ppc: use pci_init_nic_devices()
David Woodhouse [Mon, 23 Oct 2023 08:37:19 +0000 (09:37 +0100)] 
hw/ppc: use pci_init_nic_devices()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/ppc/spapr: use qemu_get_nic_info() and pci_init_nic_devices()
David Woodhouse [Mon, 23 Oct 2023 08:37:17 +0000 (09:37 +0100)] 
hw/ppc/spapr: use qemu_get_nic_info() and pci_init_nic_devices()

Avoid directly referencing nd_table[] by first instantiating any
spapr-vlan devices using a qemu_get_nic_info() loop, then calling
pci_init_nic_devices() to do the rest.

No functional change intended.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/ppc/prep: use pci_init_nic_devices()
David Woodhouse [Mon, 23 Oct 2023 08:37:14 +0000 (09:37 +0100)] 
hw/ppc/prep: use pci_init_nic_devices()

Previously, the first PCI NIC would be placed in PCI slot 3 and the rest
would be dynamically assigned. Even if the user overrode the default NIC
type and made it something other than PCNet.

Now, the first PCNet NIC (that is, anything not explicitly specified
to be anything different) will go to slot 3 even if it isn't the first
NIC specified on the command line. And anything else will be dynamically
assigned.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/mips/loongson3_virt: use pci_init_nic_devices()
David Woodhouse [Sat, 21 Oct 2023 20:34:11 +0000 (21:34 +0100)] 
hw/mips/loongson3_virt: use pci_init_nic_devices()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/mips/malta: use pci_init_nic_devices()
David Woodhouse [Sat, 21 Oct 2023 20:30:51 +0000 (21:30 +0100)] 
hw/mips/malta: use pci_init_nic_devices()

The Malta board setup code would previously place the first NIC into PCI
slot 11 if was a PCNet card, and the rest (including the first if it was
anything other than a PCNet card) would be dynamically assigned.

Now it will place any PCNet NIC into slot 11, and then anything else will
be dynamically assigned.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/mips/fuloong2e: use pci_init_nic_devices()
David Woodhouse [Sat, 21 Oct 2023 20:26:19 +0000 (21:26 +0100)] 
hw/mips/fuloong2e: use pci_init_nic_devices()

The previous behaviour was: *if* the first NIC specified on the command
line was an RTL8139 (or unspecified model) then it gets assigned to PCI
slot 7, which is where the Fuloong board had an RTL8139. All other
devices (including the first, if it was specified as anything other than
an rtl8319) get dynamically assigned on the bus.

The new behaviour is subtly different: If the first NIC was given a
specific model *other* than rtl8139, and a subsequent NIC was not,
then the rtl8139 (or unspecified) NIC will go to slot 7 and the rest
will be dynamically assigned.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/loongarch: use pci_init_nic_devices()
David Woodhouse [Sat, 21 Oct 2023 20:21:03 +0000 (21:21 +0100)] 
hw/loongarch: use pci_init_nic_devices()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Song Gao <gaosong@loongson.cn>
2 years agohw/hppa: use pci_init_nic_devices()
David Woodhouse [Sat, 21 Oct 2023 20:20:34 +0000 (21:20 +0100)] 
hw/hppa: use pci_init_nic_devices()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/arm/virt: use pci_init_nic_devices()
David Woodhouse [Sat, 21 Oct 2023 20:19:27 +0000 (21:19 +0100)] 
hw/arm/virt: use pci_init_nic_devices()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/arm/sbsa-ref: use pci_init_nic_devices()
David Woodhouse [Fri, 20 Oct 2023 10:45:58 +0000 (11:45 +0100)] 
hw/arm/sbsa-ref: use pci_init_nic_devices()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
2 years agohw/alpha/dp264: use pci_init_nic_devices()
David Woodhouse [Fri, 20 Oct 2023 00:15:45 +0000 (01:15 +0100)] 
hw/alpha/dp264: use pci_init_nic_devices()

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/xen: use qemu_create_nic_bus_devices() to instantiate Xen NICs
David Woodhouse [Tue, 17 Oct 2023 16:53:58 +0000 (17:53 +0100)] 
hw/xen: use qemu_create_nic_bus_devices() to instantiate Xen NICs

When instantiating XenBus itself, for each NIC which is configured with
either the model unspecified, or set to to "xen" or "xen-net-device",
create a corresponding xen-net-device for it.

Now we can revert the previous more hackish version which relied on the
platform code explicitly registering the NICs on its own XenBus, having
returned the BusState* from xen_bus_init() itself.

This also fixes the setup for Xen PV guests, which was previously broken
in various ways and never actually managed to peer with the netdev.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
2 years agohw/i386/pc: use qemu_get_nic_info() and pci_init_nic_devices()
David Woodhouse [Thu, 19 Oct 2023 23:07:45 +0000 (00:07 +0100)] 
hw/i386/pc: use qemu_get_nic_info() and pci_init_nic_devices()

Eliminate direct access to nd_table[] and nb_nics by processing the the
Xen and ISA NICs first and then calling pci_init_nic_devices() for the
rest.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
2 years agohw/pci: add pci_init_nic_devices(), pci_init_nic_in_slot()
David Woodhouse [Fri, 20 Oct 2023 00:05:31 +0000 (01:05 +0100)] 
hw/pci: add pci_init_nic_devices(), pci_init_nic_in_slot()

The loop over nd_table[] to add PCI NICs is repeated in quite a few
places. Add a helper function to do it.

Some platforms also try to instantiate a specific model in a specific
slot, to match the real hardware. Add pci_init_nic_in_slot() for that
purpose.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
2 years agonet: add qemu_create_nic_bus_devices()
David Woodhouse [Sun, 22 Oct 2023 08:13:41 +0000 (09:13 +0100)] 
net: add qemu_create_nic_bus_devices()

This will instantiate any NICs which live on a given bus type. Each bus
is allowed *one* substitution (for PCI it's virtio → virtio-net-pci, for
Xen it's xen → xen-net-device; no point in overengineering it unless we
actually want more).

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agonet: report list of available models according to platform
David Woodhouse [Sat, 21 Oct 2023 22:09:38 +0000 (23:09 +0100)] 
net: report list of available models according to platform

By noting the models for which a configuration was requested, we can give
the user an accurate list of which NIC models were actually available on
the platform/configuration that was otherwise chosen.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
2 years agonet: add qemu_{configure,create}_nic_device(), qemu_find_nic_info()
David Woodhouse [Thu, 19 Oct 2023 20:28:29 +0000 (21:28 +0100)] 
net: add qemu_{configure,create}_nic_device(), qemu_find_nic_info()

Most code which directly accesses nd_table[] and nb_nics uses them for
one of two things. Either "I have created a NIC device and I'd like a
configuration for it", or "I will create a NIC device *if* there is a
configuration for it".  With some variants on the theme around whether
they actually *check* if the model specified in the configuration is
the right one.

Provide functions which perform both of those, allowing platforms to
be a little more consistent and as a step towards making nd_table[]
and nb_nics private to the net code.

One might argue that platforms ought to be consistent about whether
they create the unconfigured devices or not, but making significant
user-visible changes is explicitly *not* the intent right now.

The new functions leave the 'model' field of the NICInfo as NULL after
using it for the default NIC model, unlike the qemu_check_nic_model()
function which does set nd->model to match default_model explicitly.
This is acceptable because there is no code which consumes nd->model
except this NIC-matching code in net/net.c, and no reasonable excuse
for any code wanting to use nd->model in future.

Also export the qemu_find_nic_info() helper, as some platforms have
special cases they need to handle.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2 years agohw/arm: Connect SPI Controller to BCM2835
Rayhan Faizel [Mon, 29 Jan 2024 22:18:08 +0000 (03:48 +0530)] 
hw/arm: Connect SPI Controller to BCM2835

This patch will allow the SPI controller to be accessible from BCM2835 based
boards as SPI0. SPI driver is usually disabled by default and config.txt does
not work.

Instead, dtmerge can be used to apply spi=on on a bcm2835 dtb file.

Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Message-id: 20240129221807.2983148-3-rayhan.faizel@gmail.com
[PMM: indent tweak]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/ssi: Implement BCM2835 SPI Controller
Rayhan Faizel [Mon, 29 Jan 2024 22:18:07 +0000 (03:48 +0530)] 
hw/ssi: Implement BCM2835 SPI Controller

This patch adds the SPI controller for the BCM2835. Polling and interrupt modes
of transfer are supported. DMA and LoSSI modes are currently unimplemented.

Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Message-id: 20240129221807.2983148-2-rayhan.faizel@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotests/qtest: Adding PCS Module test to GMAC Qtest
Nabih Estefan Diaz [Wed, 31 Jan 2024 00:27:59 +0000 (00:27 +0000)] 
tests/qtest: Adding PCS Module test to GMAC Qtest

 - Add PCS Register check to npcm_gmac-test

Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-7-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/net: GMAC Tx Implementation
Nabih Estefan Diaz [Wed, 31 Jan 2024 00:27:58 +0000 (00:27 +0000)] 
hw/net: GMAC Tx Implementation

- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
  memory for Tx

Added relevant trace-events

NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.

Change-Id: Icf14f9fcc6cc7808a41acd872bca67c9832087e6
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-6-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/net: GMAC Rx Implementation
Nabih Estefan Diaz [Wed, 31 Jan 2024 00:27:57 +0000 (00:27 +0000)] 
hw/net: GMAC Rx Implementation

- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
  memory for Rx

When RX starts, we need to flush the queued packets so that they
can be received by the GMAC device. Without this it won't work
with TAP NIC device.

When RX descriptor list is full, it returns a DMA_STATUS for
software to handle it. But there's no way to indicate the software has
handled all RX descriptors and the whole pipeline stalls.

We do something similar to NPCM7XX EMC to handle this case.

1. Return packet size when RX descriptor is full, effectively dropping
these packets in such a case.
2. When software clears RX descriptor full bit, continue receiving
further packets by flushing QEMU packet queue.

Added relevant trace-events

Change-Id: I132aa254a94cda1a586aba2ea33bbfc74ecdb831
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-5-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotests/qtest: Creating qtest for GMAC Module
Nabih Estefan Diaz [Wed, 31 Jan 2024 00:27:56 +0000 (00:27 +0000)] 
tests/qtest: Creating qtest for GMAC Module

 - Created qtest to check initialization of registers in GMAC Module.
 - Implemented test into Build File.

Change-Id: I8b2fe152d3987a7eec4cf6a1d25ba92e75a5391d
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-4-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm: Add GMAC devices to NPCM7XX SoC
Hao Wu [Wed, 31 Jan 2024 00:27:55 +0000 (00:27 +0000)] 
hw/arm: Add GMAC devices to NPCM7XX SoC

Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-3-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/net: Add NPCMXXX GMAC device
Hao Wu [Wed, 31 Jan 2024 00:27:54 +0000 (00:27 +0000)] 
hw/net: Add NPCMXXX GMAC device

This patch implements the basic registers of GMAC device and sets
registers for networking functionalities.
Squashed IRQ Implementation patch into this one for compliation.
Tested:
The following message shows up with the change:
Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E] (mii_bus:phy_addr=stmmac-0:00, irq=POLL)
stmmaceth f0802000.eth eth0: Link is Up - 1Gbps/Full - flow control rx/tx

Change-Id: If71c6d486b95edcccba109ba454870714d7e0940
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan Diaz <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240131002800.989285-2-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/xen: convert stderr prints to error/warn reports
Manos Pitsidianakis [Mon, 29 Jan 2024 16:09:42 +0000 (18:09 +0200)] 
hw/xen: convert stderr prints to error/warn reports

According to the QEMU Coding Style document:

> Do not use printf(), fprintf() or monitor_printf(). Instead, use
> error_report() or error_vreport() from error-report.h. This ensures the
> error is reported in the right place (current monitor or stderr), and in
> a uniform format.
> Use error_printf() & friends to print additional information.

This commit changes fprintfs that report warnings and errors to the
appropriate report functions.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 42a8953553cf68e8bacada966f93af4fbce45919.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints
Manos Pitsidianakis [Mon, 29 Jan 2024 16:09:41 +0000 (18:09 +0200)] 
hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints

Tracing DPRINTFs to stderr might not be desired. A developer that relies
on tracepoints should be able to opt-in to each tracepoint and rely on
QEMU's log redirection, instead of stderr by default.

This commit converts DPRINTFs in this file that are used for tracing
into tracepoints.

Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: b000ab73022dfeb7a7ab0ee8fd0f41fb208adaf0.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/xen/xen-mapcache.c: convert DPRINTF to tracepoints
Manos Pitsidianakis [Mon, 29 Jan 2024 16:09:40 +0000 (18:09 +0200)] 
hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints

Tracing DPRINTFs to stderr might not be desired. A developer that relies
on tracepoints should be able to opt-in to each tracepoint and rely on
QEMU's log redirection, instead of stderr by default.

This commit converts DPRINTFs in this file that are used for tracing
into tracepoints.

Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 2fbe1fbc59078e384761c932e97cfa4276a53d75.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports
Manos Pitsidianakis [Mon, 29 Jan 2024 16:09:38 +0000 (18:09 +0200)] 
hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports

Tracing DPRINTFs to stderr might not be desired. A developer that relies
on trace events should be able to opt-in to each trace event and rely on
QEMU's log redirection, instead of stderr by default.

This commit converts DPRINTFs in this file that are used for tracing
into trace events. Errors or warnings are converted to error_report and
warn_report calls.

Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: fe5e3bd54231abe933f95a24e0e88208cd8cfd8f.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/z2: convert DPRINTF to trace events and guest errors
Manos Pitsidianakis [Mon, 29 Jan 2024 16:09:37 +0000 (18:09 +0200)] 
hw/arm/z2: convert DPRINTF to trace events and guest errors

Tracing DPRINTFs to stderr might not be desired. A developer that relies
on trace events should be able to opt-in to each trace event and rely on
QEMU's log redirection, instead of stderr by default.

This commit converts DPRINTFs in this file that are used for tracing
into trace events. DPRINTFs that report guest errors are logged with
LOG_GUEST_ERROR.

Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 799c5141c5751cf2341e1d095349612e046424a8.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/strongarm.c: convert DPRINTF to trace events and guest errors
Manos Pitsidianakis [Mon, 29 Jan 2024 16:09:36 +0000 (18:09 +0200)] 
hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors

Tracing DPRINTFs to stderr might not be desired. A developer that relies
on trace events should be able to opt-in to each trace event and rely on
QEMU's log redirection, instead of stderr by default.

This commit converts DPRINTFs in this file that are used for tracing
into trace events. DPRINTFs that report guest errors are logged with
LOG_GUEST_ERROR.#

Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 39db71dd87bf2007cf7812f3d91dde53887f1f2f.1706544115.git.manos.pitsidianakis@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agopci-host: designware: Limit value range of iATU viewport register
Guenter Roeck [Mon, 29 Jan 2024 06:00:55 +0000 (22:00 -0800)] 
pci-host: designware: Limit value range of iATU viewport register

The latest version of qemu (v8.2.0-869-g7a1dc45af5) crashes when booting
the mcimx7d-sabre emulation with Linux v5.11 and later.

qemu-system-arm: ../system/memory.c:2750: memory_region_set_alias_offset: Assertion `mr->alias' failed.

Problem is that the Designware PCIe emulation accepts the full value range
for the iATU Viewport Register. However, both hardware and emulation only
support four inbound and four outbound viewports.

The Linux kernel determines the number of supported viewports by writing
0xff into the viewport register and reading the value back. The expected
value when reading the register is the highest supported viewport index.
Match that code by masking the supported viewport value range when the
register is written. With this change, the Linux kernel reports

imx6q-pcie 33800000.pcie: iATU: unroll F, 4 ob, 4 ib, align 0K, limit 4G

as expected and supported.

Fixes: d64e5eabc4c7 ("pci: Add support for Designware IP block")
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20240129060055.2616989-1-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/zynq: Check for CPU types in machine_run_board_init()
Philippe Mathieu-Daudé [Mon, 29 Jan 2024 15:18:28 +0000 (16:18 +0100)] 
hw/arm/zynq: Check for CPU types in machine_run_board_init()

Leverage the common code introduced in commit c9cf636d48 ("machine:
Add a valid_cpu_types property") to check for the single valid CPU
type. Remove the now unused MachineClass::default_cpu_type field.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-10-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/vexpress: Check for CPU types in machine_run_board_init()
Philippe Mathieu-Daudé [Mon, 29 Jan 2024 15:18:27 +0000 (16:18 +0100)] 
hw/arm/vexpress: Check for CPU types in machine_run_board_init()

Leverage the common code introduced in commit c9cf636d48 ("machine:
Add a valid_cpu_types property") to check for the single valid CPU
type. Remove the now unused MachineClass::default_cpu_type field.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-9-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[]
Philippe Mathieu-Daudé [Mon, 29 Jan 2024 15:18:26 +0000 (16:18 +0100)] 
hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[]

The npcm7xx Soc is created with a Cortex-A9 core, see in
hw/arm/npcm7xx.c:

  static void npcm7xx_init(Object *obj)
  {
      NPCM7xxState *s = NPCM7XX(obj);

      for (int i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
          object_initialize_child(obj, "cpu[*]", &s->cpu[i],
                                  ARM_CPU_TYPE_NAME("cortex-a9"));
      }

The MachineClass::default_cpu_type field is ignored: delete it.

Use the common code introduced in commit c9cf636d48 ("machine: Add
a valid_cpu_types property") to check for valid CPU type at the
board level.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/musca: Simplify setting MachineClass::valid_cpu_types[]
Philippe Mathieu-Daudé [Mon, 29 Jan 2024 15:18:25 +0000 (16:18 +0100)] 
hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[]

Musca boards use the embedded subsystems (SSE) tied to a specific
Cortex core. Our models only use the Cortex-M33.

Use the common code introduced in commit c9cf636d48 ("machine: Add
a valid_cpu_types property") to check for valid CPU type at the
board level.

Remove the now unused MachineClass::default_cpu_type field.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[]
Philippe Mathieu-Daudé [Mon, 29 Jan 2024 15:18:24 +0000 (16:18 +0100)] 
hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[]

The M2Sxxx SoC family can only be used with Cortex-M3.
Propagating the CPU type from the board level is pointless.

Hard-code the CPU type at the SoC level.
Remove the now ignored MachineClass::default_cpu_type field.

Use the common code introduced in commit c9cf636d48 ("machine: Add
a valid_cpu_types property") to check for valid CPU type at the
board level.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/highbank: Check for CPU types in machine_run_board_init()
Philippe Mathieu-Daudé [Mon, 29 Jan 2024 15:18:23 +0000 (16:18 +0100)] 
hw/arm/highbank: Check for CPU types in machine_run_board_init()

Restrict MachineClass::valid_cpu_types[] to the single
valid CPU types.

Instead of ignoring invalid CPU type requested by the user:

  $ qemu-system-arm -M midway -cpu cortex-a7 -S -monitor stdio
  QEMU 8.2.50 monitor - type 'help' for more information
  (qemu) info qom-tree
  /machine (midway-machine)
    /cpu[0] (cortex-a15-arm-cpu)
    ...

we now display an error:

  $ qemu-system-arm -M midway -cpu cortex-a7
  qemu-system-arm: Invalid CPU model: cortex-a7
  The only valid type is: cortex-a15

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20240129151828.59544-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/highbank: Add missing QOM parent for CPU cores
Philippe Mathieu-Daudé [Mon, 29 Jan 2024 15:18:22 +0000 (16:18 +0100)] 
hw/arm/highbank: Add missing QOM parent for CPU cores

QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20240129151828.59544-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/exynos: Check for CPU types in machine_run_board_init()
Philippe Mathieu-Daudé [Mon, 29 Jan 2024 15:18:21 +0000 (16:18 +0100)] 
hw/arm/exynos: Check for CPU types in machine_run_board_init()

Restrict MachineClass::valid_cpu_types[] to the single
valid CPU type.

Instead of ignoring invalid CPU type requested by the user:

  $ qemu-system-arm -M nuri -cpu cortex-a7 -S -monitor stdio
  QEMU 8.2.50 monitor - type 'help' for more information
  (qemu) info qom-tree
  /machine (nuri-machine)
    /soc (exynos4210)
      /cpu[0] (cortex-a9-arm-cpu)
      ...

We now display an error:

  $ qemu-system-arm -M nuri -cpu cortex-a7
  qemu-system-arm: Invalid CPU model: cortex-a7
  The only valid type is: cortex-a9

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20240129151828.59544-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/exynos: Add missing QOM parent for CPU cores
Philippe Mathieu-Daudé [Mon, 29 Jan 2024 15:18:20 +0000 (16:18 +0100)] 
hw/arm/exynos: Add missing QOM parent for CPU cores

QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20240129151828.59544-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agodoc/sphinx/hxtool.py: add optional label argument to SRST directive
David Woodhouse [Tue, 30 Jan 2024 19:01:43 +0000 (19:01 +0000)] 
doc/sphinx/hxtool.py: add optional label argument to SRST directive

We can't just embed labels directly into files like qemu-options.hx which
are included from multiple top-level rST files, because Sphinx sees the
labels as duplicate: https://github.com/sphinx-doc/sphinx/issues/9707

So add an optional argument to the SRST directive which causes a label
of the form '.. _DOCNAME-HXFILE-LABEL:' to be emitted, where 'DOCNAME'
is the name of the top level rST file, 'HXFILE' is the filename of the
.hx file, and 'LABEL' is the text provided within the 'SRST()' directive.
Using the DOCNAME of the top-level rST document means that it is unique
even when the .hx file is included from two different documents, as is
the case for qemu-options.hx

Now where the Xen PV documentation refers to the documentation for the
-initrd command line option, it can emit a link directly to it as
'<system/invocation-qemu-options-initrd>'.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240130190348.682912-1-dwmw2@infradead.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Reinstate "vfp" property on AArch32 CPUs
Peter Maydell [Fri, 26 Jan 2024 19:34:32 +0000 (19:34 +0000)] 
target/arm: Reinstate "vfp" property on AArch32 CPUs

In commit 4315f7c614743 we restructured the logic for creating the
VFP related properties to avoid testing the aa32_simd_r32 feature on
AArch64 CPUs.  However in the process we accidentally stopped
exposing the "vfp" QOM property on AArch32 TCG CPUs.

This mostly hasn't had any ill effects because not many people want
to disable VFP, but it wasn't intentional.  Reinstate the property.

Cc: qemu-stable@nongnu.org
Fixes: 4315f7c614743 ("target/arm: Restructure has_vfp_d32 test")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2098
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240126193432.2210558-1-peter.maydell@linaro.org

2 years agotests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array
Peter Maydell [Thu, 25 Jan 2024 17:32:10 +0000 (17:32 +0000)] 
tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array

This test program is the last use of any variable length array in the
codebase.  If we can get rid of all uses of VLAs we can make the
compiler error on new additions.  This is a defensive measure against
security bugs where an on-stack dynamic allocation isn't correctly
size-checked (e.g.  CVE-2021-3527).

In this case the test code didn't even want a variable-sized
array, it was just accidentally using syntax that gave it one.
(The array size for C has to be an actual constant expression,
not just something that happens to be known to be constant...)

Remove the VLA usage.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240125173211.1786196-2-peter.maydell@linaro.org

2 years agotarget/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
Peter Maydell [Thu, 25 Jan 2024 13:43:04 +0000 (13:43 +0000)] 
target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set

In kernel commit 5d5b4e8c2d9ec ("arm64/sve: Report FEAT_SVE_B16B16 to
userspace") Linux added ID_AA64ZFR0_el1.B16B16 to the set of ID
register fields which it exposes to userspace.  Update our
exported_bits mask to include this.

(This doesn't yet change any behaviour for us, because we don't yet
have any CPUs that implement this feature, which is part of SVE2.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240125134304.1470404-1-peter.maydell@linaro.org

2 years agoqemu-options.hx: Improve -serial option documentation
Peter Maydell [Mon, 22 Jan 2024 16:36:07 +0000 (16:36 +0000)] 
qemu-options.hx: Improve -serial option documentation

The -serial option documentation is a bit brief about '-serial none'
and '-serial null'. In particular it's not very clear about the
difference between them, and it doesn't mention that it's up to
the machine model whether '-serial none' means "don't create the
serial port" or "don't wire the serial port up to anything".

Expand on these points.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240122163607.459769-3-peter.maydell@linaro.org

2 years agosystem/vl.c: Fix handling of '-serial none -serial something'
Peter Maydell [Mon, 22 Jan 2024 16:36:06 +0000 (16:36 +0000)] 
system/vl.c: Fix handling of '-serial none -serial something'

Currently if the user passes multiple -serial options on the command
line, we mostly treat those as applying to the different serial
devices in order, so that for example
 -serial stdio -serial file:filename
will connect the first serial port to stdio and the second to the
named file.

The exception to this is the '-serial none' serial device type.  This
means "don't allocate this serial device", but a bug means that
following -serial options are not correctly handled, so that
 -serial none -serial stdio
has the unexpected effect that stdio is connected to the first serial
port, not the second.

This is a very long-standing bug that dates back at least as far as
commit 998bbd74b9d81 from 2009.

Make the 'none' serial type move forward in the indexing of serial
devices like all the other serial types, so that any subsequent
-serial options are correctly handled.

Note that if your commandline mistakenly had a '-serial none' that
was being overridden by a following '-serial something' option, you
should delete the unnecessary '-serial none'.  This will give you the
same behaviour as before, on QEMU versions both with and without this
bug fix.

Cc: qemu-stable@nongnu.org
Reported-by: Bohdan Kostiv <bohdan.kostiv@tii.ae>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240122163607.459769-2-peter.maydell@linaro.org
Fixes: 998bbd74b9d81 ("default devices: core code & serial lines")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/core: Remove transitional infrastructure from BusClass
Peter Maydell [Fri, 19 Jan 2024 16:35:12 +0000 (16:35 +0000)] 
hw/core: Remove transitional infrastructure from BusClass

BusClass currently has transitional infrastructure to support
subclasses which implement the legacy BusClass::reset method rather
than the Resettable interface.  We have now removed all the users of
BusClass::reset in the tree, so we can remove the transitional
infrastructure.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240119163512.3810301-6-peter.maydell@linaro.org

2 years agohw/s390x/css-bridge: switch virtual-css bus to 3-phase-reset
Peter Maydell [Fri, 19 Jan 2024 16:35:11 +0000 (16:35 +0000)] 
hw/s390x/css-bridge: switch virtual-css bus to 3-phase-reset

Switch the s390x virtual-css bus from using BusClass::reset to the
Resettable interface.

This has no behavioural change, because the BusClass code to support
subclasses that use the legacy BusClass::reset will call that method
in the hold phase of 3-phase reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Halil Pasic <pasic@linux.ibm.com>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240119163512.3810301-5-peter.maydell@linaro.org

2 years agoadb: Switch bus reset to 3-phase-reset
Peter Maydell [Fri, 19 Jan 2024 16:35:10 +0000 (16:35 +0000)] 
adb: Switch bus reset to 3-phase-reset

Switch the ADB bus from using BusClass::reset to the Resettable
interface.

This has no behavioural change, because the BusClass code to support
subclasses that use the legacy BusClass::reset will call that method
in the hold phase of 3-phase reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240119163512.3810301-4-peter.maydell@linaro.org

2 years agovmbus: Switch bus reset to 3-phase-reset
Peter Maydell [Fri, 19 Jan 2024 16:35:09 +0000 (16:35 +0000)] 
vmbus: Switch bus reset to 3-phase-reset

Switch vmbus from using BusClass::reset to the Resettable interface.

This has no behavioural change, because the BusClass code to support
subclasses that use the legacy BusClass::reset will call that method
in the hold phase of 3-phase reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Tested-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-id: 20240119163512.3810301-3-peter.maydell@linaro.org