All other handlers now have _errp() variants. Should we go this way
for .post_save()? Actually it's rather strange, when the vmstate do
successful preparations in .pre_save(), then successfully save all
sections and subsections, end then fail when all the state is
successfully transferred to the target.
Happily, we have only three .post_save() realizations, all always
successful. Let's make this a rule.
Also note, that we call .post_save() in two places, and handle
its (theoretical) failure inconsistently. Fix that too.
We may call error_setg twice on same errp if inner
vmstate_save_state_v() or vmstate_save_state() call fails. Next we will
crash on assertion in error_setv().
tests/functional: Make socat wait longer in migration exec test
The migration_with_exec test is failing sporadically for all
architectures due to a race when the destination socat process takes
too long to start listening while the source process is already
issuing connect().
The race is inherent because the exec: migration spawns the
to-be-exec'ed command asynchronously and returns from the
migrate-incoming command. The localhost-only testcase is not
representative of the majority of migrations. In a real scenario
between two different hosts that race wouldn't happen.
Fix the testcase by configuring the source socat command to wait
indefinitely while trying to connect.
While sanity checking a create blob operation the use of the auto
freed res variable could lead to inadvertently freeing an existing
blob.
Avoid this by in-lining the virtio_gpu_virgl_find_resource() check as
the value is not needed anyway.
While at it add a comment to the end and use g_steal_pointer to make
it clearer the object lifetime exceeds the function bounds if we pass
all the checks.
Anthony Roberts [Thu, 9 Apr 2026 11:02:55 +0000 (12:02 +0100)]
ui/sdl2: Fix assumption of EGL presence at runtime
The original commit had a section of code which worked on the assumption
that if OpenGL was enabled at build, it was present on the end user machine,
and calls could be made to it. This is not always the case (such as Windows
on Arm devices).
This line should have also included a runtime check.
This commit moves the relevant line to inside a runtime check for OpenGL.
Fixes: 52053b7e0a0e ("ui/sdl2: Implement dpy dmabuf functions")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3347 Cc: qemu-stable@nongnu.org Signed-off-by: Anthony Roberts <anthony.roberts@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-ID: <20260409110256.684-1-anthony.roberts@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
checkpatch: Allow spaces after all coroutine annotations
The coroutine annotations may be used in the declaration of function
pointers, which triggers checkpatch due to the space before the
parentheses. E.g:
int coroutine_fn (*run)(Job *job, Error **errp);
^
The coroutine_fn annotation is already included in the list of terms
where spaces are allowed. Add the other coroutine annotations:
coroutine_mixed_fn and no_coroutine_fn.
Bin Guo [Tue, 31 Mar 2026 06:07:31 +0000 (14:07 +0800)]
memory: Optimize flatview_simplify() to eliminate redundant memmove calls
The original flatview_simplify() implementation uses memmove() to shift
array elements after each merge operation, resulting in O(n²) time
complexity in the worst case. This is inefficient for VMs with large
memory topologies containing hundreds of MemoryRegions.
Replace the memmove-based approach with a two-pointer in-place compression
algorithm that achieves O(n) time complexity. The new algorithm uses a
write pointer i and a read pointer j, where i ≤ j is always maintained.
This invariant ensures we never overwrite unprocessed data, making memmove
unnecessary.
Paolo Bonzini [Mon, 30 Mar 2026 14:17:15 +0000 (16:17 +0200)]
thread-win32: replace CRITICAL_SECTION with SRWLOCK
SRWLOCK is a much cheaper primitive than CRITICAL_SECTION, which
basically exists only as a legacy API. The SRWLOCK is a single word
in memory and it is cheaper to just initialize it always.
Reviewed-by: Kostiantyn Kostiuk <kkostiuk@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
However, this is incorrect. Both MOVBE and (for 0xF1) CRC32
take Gv, Ev or Mv operands. In 16-bit mode therefore the
operand is of 16-bit size without prefix and 32-bit mode
with 0x66 (the data size override).
accel/mshv: return correct errno value from ioeventfd failure
Returning the raw ioctl return value results in misleading error
message. Ensure that actual failure reason is propagated by returning
-errno for ioeventfd failure.
accel/mshv: fix ioeventfd deassignment to forward correct datamatch value
unregister_ioevent() is not forwarding the datamatch (queue index) to
the mshv driver, causing only the first VirtIO-MMIO queue to be
deassigned correctly. Subsequent queues fail with `-ENOENT`, triggering
a fatal abort().
This failure was discovered while booting arm64 EDK2 firmware with mshv
accel.
Magnus Kulke [Fri, 10 Apr 2026 14:26:52 +0000 (16:26 +0200)]
target/i386/mshv: Fix segment regression in MMIO emu
When the segmentation code has been reworked, there is now an
unconditional call to emul_ops->read_segment_descriptor(). The MSHV impl
was delegating this to x86_read_segement_descriptor(), which read from
the GDT in guest memory. This fails for selector.idx == 0 and when no
GDT is set up (which is the case in real mode).
In the fix we change the MSHV impl to fill segment descriptor from
SegmentCache, that was populated from the hypervisor by mshv_load_regs()
before instruction emulation.
We dropped the use of PATH_MAX in commit f3a8bdc1d5b26 (which
basically completely rewrote the path handling).
Now we don't need any sys/param.h defines.
hw/ppc: Use glib2 instead of strcasecmp/strncasecmp
This is a change in semantics. g_ascii_strcasecmp() doesn't honour
locale but strcasecmp() does. But this is OK for at least one reason:
(1) QEMU always runs with the C locale so there's not an actual
behaviour change here
target/xtensa: Use glib2 instead of strcasecmp/strncasecmp
This is a change in semantics. g_ascii_strcasecmp() doesn't honour
locale but strcasecmp() does. But this is OK for at least one reason:
(1) QEMU always runs with the C locale so there's not an actual
behaviour change here
target/ppc: Use glib2 instead of strcasecmp/strncasecmp
This is a change in semantics. g_ascii_strcasecmp() doesn't honour
locale but strcasecmp() does. But this is OK for at least one reason:
(1) QEMU always runs with the C locale so there's not an actual
behaviour change here
target/riscv: Use glib2 instead of strcasecmp/strncasecmp
This is a change in semantics. g_ascii_strcasecmp() doesn't honour
locale but strcasecmp() does. But this is OK for at least one reason:
(1) QEMU always runs with the C locale so there's not an actual
behaviour change here
Signed-off-by: Kostiantyn Kostiuk <kkostiuk@redhat.com> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Link: https://lore.kernel.org/r/20260327134401.270186-8-kkostiuk@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/sparc: Use glib2 instead of strcasecmp/strncasecmp
This is a change in semantics. g_ascii_strcasecmp() doesn't honour
locale but strcasecmp() does. But this is OK for at least one reason:
(1) QEMU always runs with the C locale so there's not an actual
behaviour change here
(2) we want the comparison on boolean property value to be a plain
ASCII one, not to do weird things with "I" in Turkish locales,
so g_ascii_strcasecmp() is better as it's explicit about that
This is a change in semantics. g_ascii_strcasecmp() doesn't honour
locale but strcasecmp() does. But this is OK for at least one reason:
(1) QEMU always runs with the C locale so there's not an actual
behaviour change here
(2) we want the comparison data in HTTP header and it should be a plain
ASCII one, not to do weird things with "I" in Turkish locales,
so g_ascii_strcasecmp() is better as it's explicit about that
block: Use glib2 instead of strcasecmp/strncasecmp
This is a change in semantics. g_ascii_strcasecmp() doesn't honour
locale but strcasecmp() does. But this is OK for at least one reason:
(1) QEMU always runs with the C locale so there's not an actual
behaviour change here
(2) we want the comparison on url prefix and it should be a plain ASCII
one, not to do weird things with "I" in Turkish locales,
so g_ascii_strcasecmp() is better as it's explicit about that
This is a change in semantics. g_ascii_strcasecmp() doesn't honour
locale but strcasecmp() does. But this is OK for at least one reason:
(1) QEMU always runs with the C locale so there's not an actual
behaviour change here
(2) we want the comparison on class names to be a plain ASCII
one, not to do weird things with "I" in Turkish locales,
so g_ascii_strcasecmp() is better as it's explicit about that
POSIX says stddef.h provides size_t, which is the only thing
we care about here. unistd.h can be missing in non-POSIX runtimes,
so include stddef.h instead.
hw: i386: vapic: restore IRQ polling for non-kernel irqchip backends
69dfc078 extended vAPIC handling for WHPX with user-mode irqchip, but it
also changed vapic_write() case 4 in a way that excludes TCG from
apic_poll_irq().
Before that change, IRQ polling happened whenever no in-kernel irqchip
was active. After the change, it only happened for KVM or WHPX with a
user-mode irqchip. Under TCG, both kvm_enabled() and whpx_enabled() are
false, so the poll never happens.
This regresses 32-bit Windows XP guests on a Windows host with
-machine pc-i440fx-10.0,accel=tcg, causing a STOP 0x0000000A during boot.
Fix it by making the decision depend on whether KVM or WHPX is using an
in-kernel irqchip, instead of whether either accelerator is enabled.
Fixes: 69dfc078a6f0 ("hw: i386: vapic: enable on WHPX with user-mode irqchip") Signed-off-by: rickgcn <rickgcn@gmail.com> Link: https://lore.kernel.org/r/20260418061429.16898-1-rickgcn@gmail.com Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Simon Scherer [Mon, 13 Apr 2026 11:56:22 +0000 (13:56 +0200)]
target/i386: fix missing PF_INSTR in SIGSEGV context
When running linux-user emulation, the SIGSEGV handler does not
correctly set the 4th bit (PF_INSTR) in the error_code variable of
the context argument (context->uc_mcontext.gregs[REG_ERR]).
Because this bit is never set, guest applications cannot distinguish
if a fault was due to missing executable permissions. This patch
ensures that when a page fault occurs during an instruction fetch,
the PF_INSTR flag is properly populated in the signal context.
target/i386: fix strList leak in x86_cpu_get_unavailable_features
The result list built by x86_cpu_list_feature_names() was never freed
after being visited, causing a memory leak detected by ASan.
(the getter visitor is VISITOR_OUTPUT kind and doesn't own data)
Peter Maydell [Thu, 16 Apr 2026 09:16:54 +0000 (10:16 +0100)]
MAINTAINERS: Remove Xie Changlong
Xie Changlong has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
This makes the "Replication" block filter orphan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Message-id: 20260416091654.316158-29-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:53 +0000 (10:16 +0100)]
MAINTAINERS: Remove Xiao Guangrong
Xiao Guangrong has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-28-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:52 +0000 (10:16 +0100)]
MAINTAINERS: Remove Wen Congyang
Wen Congyang has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Lukas Straub <lukasstraub2@web.de>
Message-id: 20260416091654.316158-27-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:51 +0000 (10:16 +0100)]
MAINTAINERS: Remove Yanan Wang
Yanan Wang has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20260416091654.316158-26-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:50 +0000 (10:16 +0100)]
MAINTAINERS: Remove Vijai Kumar K
Vijai Kumar K has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
This makes the Shakti C class RISC-V SoC orphan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-25-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:49 +0000 (10:16 +0100)]
MAINTAINERS: Remove Su Hang
Su Hang has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
This makes the Intel Hexadecimal Object File Loader orphan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-24-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:48 +0000 (10:16 +0100)]
MAINTAINERS: Remove Shannon Zhao
Shannon Zhao has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
This makes the "ARM ACPI Subsystem" orphan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-23-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:47 +0000 (10:16 +0100)]
MAINTAINERS: Remove Ryo ONODERA
Ryo ONODERA has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-22-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:46 +0000 (10:16 +0100)]
MAINTAINERS: Remove Ronnie Sahlberg
Ronnie Sahlberg has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-21-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:45 +0000 (10:16 +0100)]
MAINTAINERS: Remove Luigi Rizzo
Luigi Rizzo has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-20-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:44 +0000 (10:16 +0100)]
MAINTAINERS: Remove Qiuhao Li
Qiuhao Li has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-19-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:43 +0000 (10:16 +0100)]
MAINTAINERS: Remove Jia Liu
Jia Liu has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
This makes the or1k-sim OpenRISC machine orphan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-18-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:42 +0000 (10:16 +0100)]
MAINTAINERS: Remove Paul Burton
Paul Burton has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-17-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:41 +0000 (10:16 +0100)]
MAINTAINERS: Remove Aarushi Mehta
Aarushi Mehta has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-16-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:40 +0000 (10:16 +0100)]
MAINTAINERS: Remove Marcel Apfelbaum
Marcel Apfelbaum has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-15-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:39 +0000 (10:16 +0100)]
MAINTAINERS: Remove Magnus Damm
Magnus Damm has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-14-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:38 +0000 (10:16 +0100)]
MAINTAINERS: Remove Mahmoud Mandour
Mahmoud Mandour has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-13-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:37 +0000 (10:16 +0100)]
MAINTAINERS: Remove Bastian Koppelmann
Bastian Koppelmann has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
This makes the Tricore TCG CPUs orphan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-12-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:36 +0000 (10:16 +0100)]
MAINTAINERS: Remove Huai-Cheng Kuo
Huai-Cheng Kuo has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
This makes "PCIE DOE" orphan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-11-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:34 +0000 (10:16 +0100)]
MAINTAINERS: Remove Dongjiu Geng
Dongjiu Geng has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
This makes the "ACPI/HEST/GHES" section orphan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-9-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:33 +0000 (10:16 +0100)]
MAINTAINERS: Remove Ed Maste
Ed Maste has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-8-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:32 +0000 (10:16 +0100)]
MAINTAINERS: Remove Damien Hedde
Damien Hedde has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-7-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:31 +0000 (10:16 +0100)]
MAINTAINERS: Remove Coiby Xu
Coiby Xu has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
This makes the "Vhost-user block device backend server" orphan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-6-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:30 +0000 (10:16 +0100)]
MAINTAINERS: Remove Jeff Cody
Jeff Cody has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
This makes the "VHDX" block driver orphan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-5-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:29 +0000 (10:16 +0100)]
MAINTAINERS: Remove Beniamino Galvani
Beniamino Galvani has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-4-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:28 +0000 (10:16 +0100)]
MAINTAINERS: Remove Anup Patel
Anup Patel has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-3-peter.maydell@linaro.org
Peter Maydell [Thu, 16 Apr 2026 09:16:27 +0000 (10:16 +0100)]
MAINTAINERS: Remove Ahmed Karaman
Ahmed Karaman has not posted to qemu-devel in some years and did not
respond to a query about whether they still wished to be listed in
our MAINTAINERS file. Remove them, on the assumption that they are
no longer active in QEMU.
This makes the "Performance Tools and Tests" orphan.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260416091654.316158-2-peter.maydell@linaro.org
target/arm: Remove target_ulong use in hvf_handle_psci_call()
Similarly to commit 3580aa03547 ("target/arm/tcg/psci.c: make
compilation unit common") which replaced the target_ulong use in
arm_handle_psci_call(), replace the one in hvf_handle_psci_call.
This could be vaddr, because entry is the start pc for the on-lining
cpu, but we prefer uint64_t because this is what we get in param[]
and pass to arm_set_cpu_on().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260410194227.16357-1-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/tcg/translate.c: replace TCGv with TCGv_va
We know this file is for 32-bit runtime target, so we can set
TCG_ADDRESS_BITS. TCG_TYPE_VA is derived accordingly and is already
passed to translator_loop.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260407222208.271838-16-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
tcg/translator: add parameter to translator_loop for current addr type
With TCG_ADDRESS_BITS mechanism, it's now possible to specify which
variant every source file is written for. Compared to before, it means
that addr_type will now vary per tb translation, where it was constant
for a given target previously.
Thus, we add new a parameter to translator_loop().
This will allow us to convert targets one by one.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20260407222208.271838-15-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This allows to get rid of TARGET_AARCH64, and helps with next patch
which will define at runtime tcg address type, by adding a second entry
point in a different source file.
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20260407222208.271838-14-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/tcg/translate-vfp.c: make compilation unit common
Generated decode files must be duplicated between user and system, as
they are generated in private folders per libs, and can't be included
otherwise, as meson does not give control on output folder.
Indeed, meson generator is a different approach than custom_target, and
this is a limitation by design.
They were already duplicated between arch variants anyway, so nothing
new here. They will now be compiled once for system binaries, and still
per target for user binaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20260407222208.271838-6-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
We need to stub a64_translate_init and gen_a64_update_pc.
At this point, we don't need to do anything for aarch64_translator_ops
since it's just an external symbol.
We can now include target/arm/tcg/translate.h from common code, since
all target specific bits have been removed, or can be specialized with
specific defines.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20260407222208.271838-5-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Include tcg-op-common.h instead, and include target specific tcg-op.h in
files needing it. This intermediate step allows to clean up every file
(TCGv, tcg_gen.*_tl.*) in separate commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-id: 20260407222208.271838-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
include/tcg/tcg-op: extract memory operations to tcg-op-mem.h
This new header defines a new type for target virtual address,
independent from TCGv and is parameterized by a new define
TCG_ADDRESS_BITS (name was suggested by Paolo instead of
TARGET_ADDRESS_BITS).
By default, tcg-op.h include set this define to TARGET_LONG_BITS, but
it's also possible to include only tcg-op-common.h and tcg-op-mem.h and
set TCG_ADDRESS_BITS manually, which is what next commits will do.
We preserve existing MIT license when extracting this new header.
target/arm: Move OMAP CP15 register definitions to cpregs-omap.c
The OMAP CP15 registers are only relevant to system-mode emulation
of OMAP SoCs. Move them out of the monolithic helper.c into a
dedicated file, following the pattern of cpregs-pmu.c and
cpregs-gcs.c. This reduces the size of helper.c and compiles
the OMAP-specific code out of CONFIG_USER_ONLY builds.
Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alessandro Ratti <alessandro@0x65c.net>
Message-id: 20260405180826.729652-1-alessandro@0x65c.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Specify which level (core/cluster/socket) caches found at in the CPU
topology. Updating cache topology to device tree (spec v0.4).
Example:
For example, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have L1d and L1i. However, extending this is not difficult.
The clusters will share a unified L2 level cache, and finally sockets
will share L3. In this patch, threads will share L1 caches by default,
but this can be adjusted if case required.
Only three levels of caches are supported. The patch does not
allow partial declaration of caches. In other words, the topology level
of every cache must be specified if that of any level is.
For instance, following device tree will be generated for a scenario
where we have 2 sockets, 2 clusters, 2 cores and 2 threads, in total 16
PEs. L1i and L1d are private to each thread, and L2 and L3 are shared at
socket level as an example.
Limitation: SMT cores cannot share L1 cache for now. This
problem does not exist in PPTT tables.
Co-developed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20260311160609.358-4-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add two functions one of which finds the lowest cache level defined in
the cache description input, and the other checks if a given cache
topology is defined at a particular cache level
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20260311160609.358-3-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three levels of caches and modifies
the cache description registers accordingly.
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
Message-id: 20260311160609.358-2-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Stefan Hajnoczi [Wed, 22 Apr 2026 18:28:47 +0000 (14:28 -0400)]
Merge tag 'pull-vfio-20260421' of https://github.com/legoater/qemu into staging
vfio queue:
* Refactors vfio code to remove CONFIG_KVM, CONFIG_IOMMU and
CONFIG_VFIO_IGD, enabling vfio files to be common files
* Extracts KVM-specific helpers and SPAPR KVM code into separate files
* Improves iommufd with dirty tracking support for nesting parent
HWPT and variable naming cleanup
* Adds VFIO I/O backend capability flags for feature support
* Enhances vfio-user with DEVICE_FEATURE support and DMA protocol fixes
* tag 'pull-vfio-20260421' of https://github.com/legoater/qemu:
vfio-user: fix DMA write reply
vfio-user: correct protocol for DMA reads/writes
vfio-user: support VFIO_USER_DEVICE_FEATURE
vfio: Add VFIO I/O backend capability flags for feature support
hw/vfio/iommufd: Control dirty tracking for nesting parent HWPT
iommufd: Rename all the idev and idevc variables to hiod and hiodc
hw/vfio: all vfio files can now be common files
hw/vfio/spapr.c: extract vfio_spapr_kvm_attach_tce to hw/vfio/kvm-spapr.c
hw/vfio/ap.c: use full path for target specific header
hw/vfio/pci.c: eradicate CONFIG_KVM
hw/vfio: eradicate CONFIG_IOMMU from sources
hw/vfio/pci-quirks.c: remove CONFIG_VFIO_IGD
hw/vfio/helpers.c: extract kvm helpers in kvm-helpers.c
hw/vfio/listener.c: remove CONFIG_KVM
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
The following patches are going to use it for qemu-vnc.
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
projects / thirdparty / qemu.git / log
