Now that there are dedicated eSDHC device models it is possible to replace
the "vendor" property (which is really a device-specific property) with a
dynamic cast, "fishing" out only the device models which shall have the
quirk applied.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20260112145418.220506-14-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bernhard Beschow [Tue, 13 Aug 2024 17:52:30 +0000 (19:52 +0200)]
hw/sd/sdhci: Remove endianness property
The endianness property was only explicitly set in the e500 machine which
now instantiates TYPE_FSL_ESDHC_BE. The property could also not be used
meaningfully in a hypothetical, common TYPE_FSL_ESDHC device model since
sdhci_common_realize() would fail in that case or it would need to know
all MMIO implementations upfront. Remove the property in favor of dedicated
device models.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20260112145418.220506-12-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bernhard Beschow [Sat, 15 Mar 2025 10:49:35 +0000 (11:49 +0100)]
hw/ppc/e500: Use TYPE_FSL_ESDHC_BE
TYPE_FSL_ESDHC_BE maches real hardware more closely by reusing code of
TYPE_IMX_USDHC. For example, it fixes Linux to flood the guest console with
"mmc0: Internal clock never stabilised" messages in the QEMU advent calendar
2018 day 19 image.
Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20260112145418.220506-10-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bernhard Beschow [Sat, 15 Mar 2025 10:49:35 +0000 (11:49 +0100)]
hw/sd/sdhci: Add TYPE_FSL_ESDHC_BE
For now, TYPE_FSL_ESDHC_BE is basically a big-endian variant of
TYPE_IMX_USDHC. It will be used in the e500 machines in the next step which
prevents Linux to flood the console with "mmc0: Internal clock never
stabilised" messages.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20260112145418.220506-9-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
The next patches will introduce eSDHC device models (big and little endian).
Prepare for that by renaming the functions. Also, this makes the code have
similar conventions as in Linux and U-Boot.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20260112145418.220506-8-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Drop the "IMX_" part of the names since these are actually {E,U}SDHC
specific and apply for PowerPC-based SoCs as well. While at it
consolidate all ESDHC constants into the ESDHC section.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20260112145418.220506-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Unaware that the constants were named after Linux and U-Boot code,
commit 1e76667f7adf ("hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*")
changed the naming to be consistent with the function names. Fix the
constant naming to be consistent with Linux and U-Boot again. In the
next step, the function names will be renamed according to Linux and
U-Boot code as well.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20260112145418.220506-6-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Just like the Freescale MPC8569E SoC the i.MX25 features an eSDHC but
as little-endian variant. According to the datasheet TYPE_FSL_IMX25 requires
the same reset quirk as the e500 machines. The quirk was introduced in d060b2789f71 ("hw/sd/sdhci: Set reset value of interrupt registers") for the
e500 machines, so reuse it now in TYPE_FSL_IMX25.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20260112145418.220506-5-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
hw/sd/sdhci: Fix TYPE_IMX_USDHC to implement sd-spec-version 3 by default
Fixes TYPE_FSL_IMX6UL, TYPE_FSL_IMX7, and TYPE_FSL_IMX8MP to implement
version 3 of the SD specification.
Note that TYPE_FSL_IMX6 already had "sd-spec-version" set accordingly and
that TYPE_FSL_IMX25 correctly sets the same property to version 2 since the
real hardware is an eSDHC which is the uSDHC's predecessor.
Fixes: fd1e5c817964 ("sdhci: Add i.MX specific subtype of SDHCI")
cc: qemu-stable Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20260112145418.220506-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tao Tang [Thu, 25 Sep 2025 15:35:50 +0000 (23:35 +0800)]
tests/qtest: Add SMMUv3 bare-metal test using iommu-testdev
Add a qtest suite that validates ARM SMMUv3 translation without guest
firmware or OS. The tests leverage iommu-testdev to trigger DMA
operations and the qos-smmuv3 library to configure IOMMU translation
structures.
This test suite targets the virt machine and covers:
- Stage 1 only translation (VA -> PA via CD page tables)
- Stage 2 only translation (IPA -> PA via STE S2 tables)
- Nested translation (VA -> IPA -> PA, Stage 1 + Stage 2)
- Design to extended to support multiple security spaces
(Non-Secure, Secure, Root, Realm)
Each test case follows this sequence:
1. Initialize SMMUv3 with appropriate command/event queues
2. Build translation tables (STE/CD/PTE) for the target scenario
3. Configure iommu-testdev with IOVA and DMA attributes via MMIO
4. Trigger DMA and validate successful translation
5. Verify data integrity through a deterministic write-read pattern
This bare-metal approach provides deterministic IOMMU testing with
minimal dependencies, making failures directly attributable to the SMMU
translation path.
Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn> Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260119161112.3841386-9-tangtao1634@phytium.com.cn>
[PMD: Cover tests/qtest/iommu-smmuv3-test.c in MAINTAINERS] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tao Tang [Wed, 26 Nov 2025 12:56:55 +0000 (20:56 +0800)]
tests/qtest/libqos: Add SMMUv3 helper library
Introduce qos-smmuv3, a reusable library for SMMUv3-related qtest
operations. This module encapsulates common tasks like:
- SMMUv3 initialization (enabling, configuring command/event queues)
- Stream Table Entry (STE) and Context Descriptor (CD) setup
- Multi-level page table construction (L0-L3 for 4KB granules)
- Support for Stage 1, Stage 2, and nested translation modes
- Could be easily extended to support multi-space testing infrastructure
(Non-Secure, Secure, Root, Realm)
The library provides high-level abstractions that allow test code to
focus on IOMMU behavior validation rather than low-level register
manipulation and page table encoding. Key features include:
- Provide memory allocation for translation structures with proper
alignment
- Helper functions to build valid STEs/CDs for different translation
scenarios
- Page table walkers that handle address offset calculations per
security space
This infrastructure is designed to be used by iommu-testdev-based tests
and future SMMUv3 test suites, reducing code duplication and improving
test maintainability.
Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de>
Message-ID: <20260119161112.3841386-8-tangtao1634@phytium.com.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tao Tang [Sun, 18 Jan 2026 06:52:14 +0000 (14:52 +0800)]
tests/qtest: Add libqos iommu-testdev helpers
Introduce a libqos helper module for the iommu-testdev
device used by qtests. This module provides some common functions to
all IOMMU test cases using iommu-testdev.
Wire the new sources into tests/qtest/libqos/meson.build so
they are built as part of the qtest support library.
Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
Message-ID: <20260119161112.3841386-7-tangtao1634@phytium.com.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tao Tang [Thu, 25 Sep 2025 15:35:49 +0000 (23:35 +0800)]
hw/misc: Introduce iommu-testdev for bare-metal IOMMU testing
Add a minimal PCI test device designed to exercise IOMMU translation
(such as ARM SMMUv3) without requiring guest firmware or OS. The device
provides MMIO registers to configure and trigger DMA operations with
controllable attributes (security state, address space), enabling
deterministic IOMMU testing.
Key features:
- Bare-metal IOMMU testing via simple MMIO interface
- Configurable DMA attributes for security states and address spaces
- Write-then-read verification pattern with automatic result checking
The device performs a deterministic DMA test pattern: write a known
value (0x12345678) to a configured GVA, read it back, and verify data
integrity. Results are reported through a dedicated result register,
eliminating the need for complex interrupt handling or driver
infrastructure in tests.
This is purely a test device and not intended for production use or
machine realism. It complements existing test infrastructure like
pci-testdev but focuses specifically on IOMMU translation path
validation.
Tao Tang [Sun, 21 Dec 2025 03:25:01 +0000 (11:25 +0800)]
hw/arm/smmuv3: Extract common definitions to smmuv3-common.h
Move register definitions, command enums, and Stream Table Entry (STE) /
Context Descriptor (CD) structure definitions from the internal header
hw/arm/smmuv3-internal.h to a new common header
include/hw/arm/smmuv3-common.h.
This allows other components, such as generic SMMUv3 tests or test devices,
to utilize these definitions without including the specific SMMUv3 device
internal state.
Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-ID: <20260119161112.3841386-2-tangtao1634@phytium.com.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Pierrick Bouvier [Mon, 19 Jan 2026 07:57:38 +0000 (23:57 -0800)]
bsd-user/syscall_defs.h: define STAT_TIME_T_EXT only for 32 bits
Commit 369c1ba2b changed the wrong conditional "#if defined(__i386__)" to
"#if defined(TARGET_I386)".
However, TARGET_I386 is defined for target x86_64 also.
This commit fixes it by identifying correctly 32 bits target.
Found with:
$ ./build/qemu-x86_64 \
-plugin ./build/contrib/plugins/libstoptrigger,icount=1000000 \
-plugin ./build/tests/tcg/plugins/libinsn \
-d plugin \
./build/qemu-system-x86_64 --version
ld-elf.so.1: /lib/libz.so.6: invalid file format
cpu 0 insns: 59746
total insns: 59746
Fixes: 369c1ba2b ("Fix __i386__ test for TARGET_HAS_STAT_TIME_T_EXT") Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This caused a failure with program using openat2, where O_LARGEFILE was
replaced by O_NOFOLLOW.
This issue is only visible when QEMU is compiled with musl libc, where
O_LARGEFILE is different from 0 (vs glibc).
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3262 Cc: qemu-stable@nongnu.org Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Commit 2ff8c9a298 removed support for 32-bit PPC hosts from the build
system. Unfortunately, the patch also removed the 32-bit PPC target for
containerized tests, which leads to an error when trying to run tests,
e.g., with "make check-tcg":
"make[1]: *** No rule to make target 'docker-image-debian-ppc-cross',
needed by 'build-tcg-tests-ppc-linux-user'. Stop."
This patch adds the PPC target back for containerized tests.
Fixes: 2ff8c9a2984b ("buildsys: Remove support for 32-bit PPC hosts") Signed-off-by: Florian Hofhammer <florian.hofhammer@fhofhammer.de> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
[Mjt: specify commit subject in Fixes tag) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Thomas Huth [Fri, 16 Jan 2026 10:11:39 +0000 (11:11 +0100)]
MAINTAINERS: Add docs/system/i386/ to the general x86 architecture section
We've got a section for generic x86 architecture support in our
MAINTAINERS file - this should cover the docs/system/i386/ folder, too.
Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This happens because the sed statements require GNU sed. Let's use
gsed in these spots to get it fixed.
Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Thomas Huth [Wed, 14 Jan 2026 08:33:06 +0000 (09:33 +0100)]
configure: Set $PYTHON in the configuration of the optionroms
pc-bios/optionrom/Makefile uses $(PYTHON) for running a Python script,
but this variable is never initialized here. So the script gets run
via its shebang line - which fails if the "python3" binary is not
available on the system. To fix this, write the PYTHON configuration
to the config.mak file of the optionroms.
Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Julian Ganz [Sat, 27 Dec 2025 08:53:46 +0000 (09:53 +0100)]
tests: fix comment declaring runtime in rv64 interruptedmemory test
The test attempts to trigger a regression for arount 30s. However, a
comment just before the computation of the target wall clock time falsly
declares the run time to be around 60s.
This was the case already when we introduced the test in
Signed-off-by: Julian Ganz <neither@nut.email> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Michael Tokarev [Thu, 18 Dec 2025 07:28:11 +0000 (10:28 +0300)]
qemu-options.hx: use KiB, MiB, GiB for power-of-2 units
Use MiB &Co instead of MB &Co when the talk is about
power-of-two-based sizes, in qemu-options.hx.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3222 Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Michael Tokarev [Thu, 25 Dec 2025 06:18:40 +0000 (09:18 +0300)]
gdbstub: unlink the unix socket before bind()
This is another variant of doing what v9.2.0-1561-gfccb744f41c6
"gdbstub: Try unlinking the unix socket before binding" did, but
that commit introduced dependency on qemu-sockets.c which is
more problematic for statically-linked qemu-user binaries.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit introduced dependency of linux-user on qemu-sockets.c.
The latter includes handling of various socket types, while gdbstub
only needs unix sockets. Including different kinds of sockets
makes it more problematic to build linux-user statically.
The original issue - the need to unlink unix socket before binding -
will be addressed in the next change.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Merge tag 'pull-tcg-20260119' of https://gitlab.com/rth7680/qemu into staging
Remove support for 32-bit hosts.
# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmltWH8dHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/ERwgAjYEp0OOEGoHQG0Tj
# MWymeQXRgtslspQtkhlIC5IiC8vWOeJVXVvb+sWV4fckkv/v4BK2R903IuHrRiYu
# MeJSDMI6tCWDRzP2U2jbeFlxQ0BGAQUjpi7oRkJEZv9qgWxodek6o+2HLM0iqcDM
# 7NciQwWwlMpkizx45qD+rpulvictLWjYczSpQPrkXEvqVT7dut20MKP/06FvqGsa
# E+1WoZAq0UfkT8xbqcLXgX5QyVPFpC0ZIcHBzXiUip6G4rY5rVnBeuiYCKojl2CI
# M0l9UEwG1KP9aaP6Lx2lg0qnXKT6ITukoPIzlEUDoNorGDwdXklYjd/ChmknQv3K
# fG0zWg==
# =LRWj
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 19 Jan 2026 09:02:39 AM AEDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]
* tag 'pull-tcg-20260119' of https://gitlab.com/rth7680/qemu: (54 commits)
include/qemu/atomic: Drop aligned_{u}int64_t
meson: Remove CONFIG_ATOMIC64
include/qemu/atomic: Drop qatomic_{read,set}_[iu]64
util: Remove stats64
block: Drop use of Stat64
migration: Drop use of Stat64
target/s390x: Simplify atomicity check in do_csst
target/s390x: Drop CONFIG_ATOMIC64 tests
target/m68k: Drop CONFIG_ATOMIC64 tests
target/hppa: Drop CONFIG_ATOMIC64 test
target/arm: Drop CONFIG_ATOMIC64 tests
linux-user/hppa: Drop CONFIG_ATOMIC64 test
linux-user/arm: Drop CONFIG_ATOMIC64 test
accel/tcg: Drop CONFIG_ATOMIC64 test from translator.c
accel/tcg: Drop CONFIG_ATOMIC64 checks from ldst_atomicicy.c.inc
tcg: Unconditionally define atomic64 helpers
accel/tcg/runtime: Remove helper_nonatomic_cmpxchgo
accel/tcg/runtime: Remove 64-bit shift helpers
target/riscv: Drop TCG_TARGET_REG_BITS test
target/i386/tcg: Drop TCG_TARGET_REG_BITS test
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
We should have used MO_{32,64} from the start, rather than
raw integer constants. However, now that the CONFIG_ATOMIC64
test has been removed, we can remove the 'max' variable and
simplify the two blocks.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Since we only support 64-bit hosts, there's no real need
to parameterize TCG_TARGET_REG_BITS. It seems worth holding
on to the identifier though, for documentation purposes.
Move one tcg/*/tcg-target-reg-bits.h to tcg/target-reg-bits.h
and remove the others.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Remove instances of __i386__, except from tests and imported headers.
Drop a block containing sanity check and fprintf error message for
i386-on-i386 or x86_64-on-x86_64 emulation. If we really want
something like this, we would do it via some form of compile-time check.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Remove tcg/arm.
Remove instances of __arm__, except from tests and imported headers.
Remove arm from supported_cpus.
Remove linux-user/include/host/arm.
Remove common-user/host/arm.
Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Merge tag 'accel-20260116' of https://github.com/philmd/qemu into staging
Accelerators patches queue
- Enable 64bit WebAssembly guests (TCI)
- Fix migration on HVF
- Remove a signal race with WFI on HVF (Aarch64)
- Correct HVF guest timer frequency (Aarch64)
- Fix NVMM build (x86)
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmlqHhcACgkQ4+MsLN6t
# wN7NEA//cZvw4AdTKgUxenEQL2r+Y8KVT+Wm+F7WqznTm9dqGgb+YHgmDoPA9b6y
# qxenzIwVA1R2ZkgAs7m99z9k9YcZLXHdoKelWYqxoWZd1DFVQJ7by5iRoQbvdtRJ
# LSxQXkdcXCGBIWQ080k0WJP5e7Sw/1+LdSm3jn2naRTD1JF3jn4LwUZMFQSwuhH0
# 0uXFrb207AlFz4itNnZXIjcvugMi6hIKNhHX8ol0JLSlfkS0lVR4y1X21J11ipg3
# VYucsUfA9fzfqcTDkPxGuEAV5mivaP1wy8kHRh5p8vgq7dbLivdIpjYIZynzb1LF
# 10WaeJaYHHYeWqLSKcZPUd66eKc2ZOeGn+zcE8oM8Zsm2NQUJ+rIkWw7/O978PfS
# RsXmIYTkM8gXfx7gUtW95/JmX5FH4xsvrwRjv1FdOPwYNe3kMtc1xslq9dkqsXMG
# P79n+NVXRr62ph93lSjLdLgqFW6eEXo0nVO4maD+9pBolK9S8TIrzLxRwXyHY/lx
# FD9nRHP/U1QjrrwpCcFT3PmTfJ/CsMlP0biUG9+uf6XKkxlOIyNoMSDdTC5xjUTx
# iCC71XluRIBKAIpwIN9QHtTTrKvm2wMFlTHpQxMD/kldc+0whHBtfU/24vemCCMQ
# dpnJxr0lVng942YHhT/n2Y6CZbzURF022I89p7EJ6d/1Els0j/c=
# =khzj
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 16 Jan 2026 10:16:39 PM AEDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'accel-20260116' of https://github.com/philmd/qemu: (30 commits)
tests/functional: Require TCG to run reverse debugging tests
target/i386/nvmm: Include missing ramlist.h header
accel/nvmm: Fix 'cpu' typo in nvmm_init_vcpu()
hmp-commands-info.hx: Move definition of "info accel"
target/arm: Only allow disabling NEON when using TCG
target/arm/hvf: Really set Generic Timer counter frequency
target/arm: Create GTimers *after* features finalized / accel realized
accel/hvf: Add hvf_arch_cpu_realize() stubs
accel: Introduce AccelOpsClass::cpu_target_realize() hook
accel/hvf: Have PSCI CPU_SUSPEND halt the vCPU
accel/hvf: Implement WFI without using pselect()
accel/hvf: Skip WFI if CPU has work to do
target/arm/hvf: Implement dirty page tracking
accel/hvf: Remove mac_slots
accel/hvf: Drop hvf_slot and hvf_find_overlap_slot
accel/hvf: Simplify hvf_set_phys_mem
accel/hvf: Move hvf_log_sync to hvf_log_clear
accel/hvf: Simplify hvf_log_*
target/i386/hvf: Use address_space_translate in ept_emulation_fault
target/i386/hvf: Use hvf_unprotect_dirty_range
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
tests/functional: Require TCG to run reverse debugging tests
Record/replay is specific to TCG. Require it to avoid failure
when using a HVF-only build on Darwin:
qemu-system-aarch64: -icount shift=7,rr=record,rrfile=/scratch/replay.bin,rrsnapshot=init: cannot configure icount, TCG support not available
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-ID: <20260115161029.24116-1-philmd@linaro.org>
target/i386/nvmm/nvmm-all.c: In function 'nvmm_init_vcpu':
target/i386/nvmm/nvmm-all.c:988:9: error: 'AccelCPUState' has no member named 'vcpu_dirty'
988 | qcpu->vcpu_dirty = true;
| ^~
Cc: qemu-stable@nongnu.org Reported-by: Thomas Huth <thuth@redhat.com> Fixes: 2098164a6be ("accel/nvmm: Replace @dirty field by generic CPUState::vcpu_dirty field") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260113203924.81560-1-philmd@linaro.org>
hmp-commands-info.hx: Move definition of "info accel"
Commit c10eb740108 (accel/system: Add 'info accel' on human monitor)
inserted "info accel" in the middle of "info sync-profile". Move it
behind "info sync-profile".
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260116005050.376616-2-dave@treblig.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
target/arm: Only allow disabling NEON when using TCG
Only allow disabling NEON when using TCG.
This avoids confusing user experience:
$ qemu-system-aarch64 -M virt -accel hvf \
-cpu host,neon=off,vfp=off,vfp-d32=off
qemu-system-aarch64: AArch64 CPUs must have both VFP and Neon or neither
$ qemu-system-aarch64 -M virt -accel hvf \
-cpu host,neon=off,vfp=off,vfp-d32=off
qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither
$ qemu-system-aarch64 -M virt -accel hvf \
-cpu host,neon=off,vfp=off,vfp-d32=off
qemu-system-aarch64: can't apply global host-arm-cpu.vfp-d32=off: Property 'host-arm-cpu.vfp-d32' not found
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Message-ID: <20260112103034.65310-20-philmd@linaro.org>
projects / thirdparty / qemu.git / log
