hw/vfio/migration: Check base architecture at runtime
Inline vfio_arch_wants_loading_config_after_iter() and
replace the compile time check of the TARGET_ARM definition
by a runtime call to target_base_arm().
Merge tag 'single-binary-20260112' of https://github.com/philmd/qemu into staging
Various patches related to single binary effort:
- Endianness cleanups in memory core subsystem and for various targets
- Few cleanups around target_ulong type
- Build various compilation units as common
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmlleisACgkQ4+MsLN6t
# wN40yw/+NYK6Q+v8YHclH0g6YkPsXYsCVOLWhYaUQ9Smc3Vk8js02LRMxomGiyjc
# lRhatftrH4dCuiWavyhlK/z+tu3b2WOgjjcIocg7ztZEwzyvDPEKidBNM4Wrv27d
# 6WNdtCn1rOOYQBcCs/MEHnrxIl3qfl5Kqt4hzejcK4E1DFa1m5ashAEVJwMlqYWp
# qkBT3fw0jfHojM+eTAbvKI1fi27GVMXbQXSM3V3vG3njxmx4JQT0p9QjyDYWZwgh
# xAJvy5neoNv3T7TBELCfqSWzGA5WHrW/eAkuRuO0JVa69IOn/mh2aGKboJMT7KQF
# ufyxceHMj8TLJr6c9BrvaWX7+p7xyvbX3ud+qXOV9P2FBVm+hf2lHnw0pJJ6A51g
# qv3u8zUVwhmx6oF95ibQtaWKdLNhGCKtVKJu59Xxj/7Bp00BS1Jnj6E/g34To8Vm
# 18g3cPJ+CEhdTFSkcHusiVI4GdHb8JEGUd5kyWza3gEgYb/J1Ps/a807n6C6NQcq
# MRkt2zNKS+sJeZzvl+BGH8WewMVGWm1f8IoP28ZvgyxFVutkgFcj+UQZp3J7mkpV
# ja0B7+1NMK9oMeq/+YM4gUgEF0ydThlqa+qTzxVYu8qpzWT9+cqqWeQHAteE3g/v
# rqqu/sBUSbh5xi+82zRbgwd7Hj31ST5XkepQN0vUTT4P3zCijy8=
# =P+9/
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 13 Jan 2026 09:48:11 AM AEDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'single-binary-20260112' of https://github.com/philmd/qemu: (61 commits)
target/arm/gdbstub: make compilation unit common
target/arm/gdbstub: extract aarch64_cpu_register_gdb_regs_for_features
gdbstub/helpers.h: allow header to be called from common code
accel/tcg: Un-inline WatchPoint API user-emulation stubs
target/tricore: Build system units in common source set
target/tricore: Inline translator_lduw()
target/tricore: Use little-endian variant of cpu_ld/st_data*()
target/sparc: Inline cpu_ldl_code() call in cpu_do_interrupt()
target/sparc: Inline translator_ldl()
target/sparc: Use explicit big-endian LD/ST API
hw/sparc: Use explicit big-endian LD/ST API
hw/sparc: Mark SPARC-specific peripherals as big-endian
target/sh4: drop cpu_reset from realizefn
target/sh4: Build system units in common source set
target/rx: Build system units in common source set
target/rx: Inline translator_lduw() and translator_ldl()
target/rx: Use explicit little-endian LD/ST API
target/rx: Use little-endian variant of cpu_ld/st_data*()
target/openrisc: Build system units in common source set
target/openrisc: Avoid target-specific migration headers in machine.c
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
accel/tcg: Un-inline WatchPoint API user-emulation stubs
Currently we can not build files including "exec/watchpoint.h"
as meson common objects because the CONFIG_USER_ONLY definition
is poisoned. We can easily fix that by un-inlining the
user-emulation stubs.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260106231908.16756-5-philmd@linaro.org>
target/tricore: Build system units in common source set
Since commit range 809b460f305..cd08bcaa36b we remove all
uses of the target_ulong type in target/rx/. Use the meson
target_common_system_arch[] source set to prevent further
uses of target-specific types.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-4-philmd@linaro.org>
target/tricore: Use little-endian variant of cpu_ld/st_data*()
We only build the TriCore target using little endianness order,
therefore the cpu_ld/st_data*() definitions expand to the little
endian declarations. Use the explicit little-endian variants.
Mechanical change running:
$ tgt=tricore; \
end=le; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Then adapting spaces style manually to pass checkpatch.pl.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-ID: <20251126202200.23100-6-philmd@linaro.org>
hw/sparc: Mark SPARC-specific peripherals as big-endian
These devices are only used by the SPARC target, which is
only built as big-endian. Therefore the DEVICE_NATIVE_ENDIAN
definition expand to DEVICE_BIG_ENDIAN (besides, the
DEVICE_LITTLE_ENDIAN case isn't tested). Simplify directly
using DEVICE_BIG_ENDIAN.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251224162642.90857-2-philmd@linaro.org>
Alex Bennée [Thu, 8 Jan 2026 14:34:12 +0000 (14:34 +0000)]
target/sh4: drop cpu_reset from realizefn
Shuffle things around to ensure that gdb register creation was
done after dependant peripherals had created their cpu interfaces.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260108143423.1378674-2-alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
target/sh4: Build system units in common source set
Since commit range 42c90609b8f..82a1e739010 we remove all
uses of the target_ulong type in target/rx/. Use the meson
target_common_system_arch[] source set to prevent further
uses of target-specific types.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-3-philmd@linaro.org>
target/rx: Build system units in common source set
Since commit range 2982b948a9f..86114e43ffd we remove all
uses of the target_ulong type in target/rx/. Use the meson
target_common_system_arch[] source set to prevent further
uses of target-specific types.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-2-philmd@linaro.org>
The RX architecture uses little endianness. Directly use
the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|st)t?u?[wlq]_p' target/rx/); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251224163304.91384-3-philmd@linaro.org>
target/rx: Use little-endian variant of cpu_ld/st_data*()
We only build the RX target using little endianness order,
therefore the cpu_ld/st_data*() definitions expand to the little
endian declarations. Use the explicit little-endian variants.
Mechanical change running:
$ tgt=rx; \
end=le; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-ID: <20251126202200.23100-5-philmd@linaro.org>
target/openrisc: Build system units in common source set
Since previous 2 commits and range 2795bc52af4..5b67dbf1dc3 we
remove all uses of the target_ulong type in target/rx/. Use the
meson target_common_system_arch[] source set to prevent further
uses of target-specific types.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-7-philmd@linaro.org>
target/openrisc: Avoid target-specific migration headers in machine.c
machine.c doesn't use any target-specific macro defined by
the "migration/cpu.h" header. Use the minimum header required:
"migration/qemu-file-types.h" and "migration/vmstate.h", which
are not target-specific.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Prasad Pandit <pjp@fedoraproject.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-6-philmd@linaro.org>
target/openrisc: Remove unused 'gdbstub/helpers.h' header in helper.c
"gdbstub/helpers.h" uses target-specific symbols, but we don't
need it, so remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-5-philmd@linaro.org>
hw/intc: Mark OpenRISC-specific peripheral as big-endian
The Open Multi-Processor Interrupt Controller (ompic) is only
used by the OpenRISC target, which is only built as big-endian.
Therefore the DEVICE_NATIVE_ENDIAN definition expand to
DEVICE_BIG_ENDIAN (besides, the DEVICE_LITTLE_ENDIAN case isn't
tested). Simplify directly using DEVICE_BIG_ENDIAN.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251224161804.90064-2-philmd@linaro.org>
target/microblaze: Avoid target-specific migration headers in machine.c
machine.c doesn't use any target-specific macro defined by
the "migration/cpu.h" header. Use the minimum header requiered:
"migration/qemu-file-types.h" and "migration/vmstate.h", which
are not target-specific.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260106235333.22752-4-philmd@linaro.org>
target/microblaze: Directly check endianness via CPUConfig::endi flag
The MicroBlazeCPUConfig::endi flag reports whether the CPU is
configure in little endianness. Directly use this knowledge
instead of evaluating MemOp from mo_endian().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260106235333.22752-3-philmd@linaro.org>
target/m68k: Replace MD_TLONG -> MD_I32 in monitor.c
m68k's monitor_defs[] array implicitly uses type=MD_TLONG for
all its entries. Since we only build this target as 32-bit,
use the explicit MD_I32 type to avoid an indirect target_long
use.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-10-philmd@linaro.org>
Directly use the inlined form, expanding MO_TE -> MO_LE
since LoongArch use little-endian order.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20251224161456.89707-8-philmd@linaro.org>
target/loongarch: Use explicit little-endian LD/ST API
The LoongArch architecture uses little endianness. Directly
use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|st)t?u?[wlq]_p' target/loongarch/); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20251224161456.89707-1-philmd@linaro.org>
target/loongarch: Inline cpu_ldl_code() call in cpu_do_interrupt()
In preparation of removing the cpu_ldl_code wrapper, inline it.
Since LoongArch instructions are always stored in little-endian
order, replace MO_TE -> MO_LE.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-Id: <20251224161456.89707-6-philmd@linaro.org>
We only build the LoongArch target using little endianness
order, therefore the MO_TE definitions expand to the little
endian one. Use the latter which is more explicit.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20251224161456.89707-5-philmd@linaro.org>
target/loongarch: Use hwaddr type for physical addresses
Replace variables used with get_physical_address(), which
expect a physical addresses, by the 'hwaddr' type, instead
of the 'target_ulong' one.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20251224161456.89707-4-philmd@linaro.org>
target/loongarch: Replace target_ulong -> uint64_t for DMW and TLBRBADV
The Direct Mapping Configuration Window and Bad Virtual
Address CSR registers are declared as uint64_t since their
introduction in commit 398cecb9c3e ("target/loongarch: Add
CSRs definition"):
Use the proper uint64_t type instead of target_ulong
(which would otherwise be truncated on 32-bit builds).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-Id: <20251224161456.89707-3-philmd@linaro.org>
hw/loongarch: Use explicit little-endian LD/ST API
The LoongArch architecture uses little endianness. Directly
use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|st)t?u?[wlq]_p' hw/loongarch/); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20251224161456.89707-2-philmd@linaro.org>
target/hppa: Remove target_ulong use in disas_log() handler
Since commit 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase
virtual addresses") the DisasContextBase::pc_first field is a vaddr
type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-9-philmd@linaro.org>
target/hppa: Avoid target-specific migration headers in machine.c
machine.c doesn't use any target-specific macro defined by
the "migration/cpu.h" header. Use the minimum header required:
"migration/qemu-file-types.h" and "migration/vmstate.h", which
are not target-specific.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Prasad Pandit <pjp@fedoraproject.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260107200702.54582-8-philmd@linaro.org>
The HPPA architecture uses big endianness. Directly use
the big-endian LD/ST API.
Mechanical change using:
$ end=be; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|st)t?u?[wlq]_p' target/hppa/); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251229225517.45078-4-philmd@linaro.org>
target/hppa: Remove unnecessary @cpu variable by using cpu_env()
Partly revert changes introduced by commit b2c2d00f48c ("target/hppa:
add 64 bit support to gdbstub"), restoring the cpu_env() call and
removing the unused @cpu argument.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251229225517.45078-3-philmd@linaro.org>
target/hppa: Use big-endian variant of cpu_ld/st_data*()
We only build the HPPA target using big endianness order,
therefore the cpu_ld/st_data*() definitions expand to the big
endian declarations. Use the explicit big-endian variants.
Mechanical change running:
$ tgt=hppa; \
end=be; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251229225517.45078-2-philmd@linaro.org>
target/hexagon: Use little-endian variant of cpu_ld/st_data*()
We only build the Hexagon target using little endianness order,
therefore the cpu_ld/st_data*() definitions expand to the little
endian declarations. Use the explicit little-endian variants.
Mechanical change running:
$ tgt=hexagon; \
end=le; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251219185025.97318-3-philmd@linaro.org>
In preparation for dropping TARGET_PHYS_ADDR_SPACE_BITS, add a
a runtime function to correctly represent the size of the physical
address space for EV4-6 based on the current CPU version.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-ID: <20260112-phys_addr-v3-1-5f90fdb4015f@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260106155755.53646-5-philmd@linaro.org>
target/alpha: Inline cpu_ldl_code() call in do_unaligned_access()
In preparation of removing the cpu_ldl_code wrapper, inline it.
Use the return address argument.
Since Alpha instructions are always stored in little-endian
order, replace MO_TE -> MO_LE.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260106155755.53646-4-philmd@linaro.org>
meson: Allow system binaries to not have target-specific units
As we are moving toward a single binary, targets might end
without any target-specific objects (all objects being in
the 'common' source set). Allow this by checking the
target_system_arch[] dictionary contains the target key
before using it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20260106235333.22752-2-philmd@linaro.org>
system/ioport: Do not open-code address_space_ld/st_le() methods
When a variable size is known, prefer the address_space_ld/st()
API. Keep address_space_read/write() for blobs.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260109165058.59144-23-philmd@linaro.org>
system/ioport: Declare x86-specific I/O port in little-endian order
X86 in/out port (related to ISA bus) uses little endianness:
- enforce little endianness in x86 cpu_in/out() accessors,
- serialize QTest in/out port accesses as little-endian.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260109165058.59144-22-philmd@linaro.org>
system/memory: Split MemoryRegionCache API to 'memory_cached.h'
We have 115 direct inclusions of "system/memory.h", and 91 headers
in include/ use it: hundreds of files have to process it.
However only one single header really uses the MemoryRegionCache
API: "hw/virtio/virtio-access.h". Split it out to a new header,
avoiding processing unused inlined functions hundreds of times.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260109165058.59144-6-philmd@linaro.org>
leul_to_cpu() is only used within physmem.c: inline it
and remove.
Since @bitmap is of 'unsigned long' type, use its size
with ldn_le_p() instead of using HOST_LONG_BITS.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260109165058.59144-4-philmd@linaro.org>
Since these headers use some __builtin_bswap*(), use it
consistently in all the cases, allowing to remove the
"qemu/bswap.h" inclusion (which only defines bswap* to
the builtin equivalent).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260109164742.58041-5-philmd@linaro.org>
meson.build:1:0: ERROR: prefix value '/qemu' must be an absolute path
This is https://github.com/mesonbuild/meson/issues/14303. Remove the
prefix='/qemu' line in configs/meson/windows.txt, since commit d17f305a264
("configure: use a platform-neutral prefix", 2020-09-30) says that the
NSIS installer doesn't care.
Cc: qemu-stable@nongnu.org Cc: Thomas Huth <thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260112160736.1028280-1-pbonzini@redhat.com>
Merge tag 'pull-request-2026-01-12' of https://gitlab.com/thuth/qemu into staging
* Check functional tests with pylint
* update copyright year to 2026
* Some more universal-binary work for the s390x code done by Philippe
* Fix reverse debugging for s390x and add a functional test for it
# -----BEGIN PGP SIGNATURE-----
#
# iQJFBAABCgAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmlk81cRHHRodXRoQHJl
# ZGhhdC5jb20ACgkQLtnXdP5wLbWxhxAAlvaTwC7trSsFY3sTMwenG0GHfg0M840H
# vYXHm69uHigT4IyC2pXOjCN0Yq9zujCymtUIWOKY8l+Hx/x5tgi5fKhOXqqZBhJP
# KyBKZqJx3cVZC54qlNWF0vxSYCi32wi6xQmVlMYtbBZPfbMfY1Vi55PAknpXCWjv
# YfBB72LQhS3uPBLOi2Dg3mkGq9+cqHoAVCDVguOBx0N4SdkotvbKrG4XOhFfzjVu
# VrLgwF2LBLQzlU2JZ/b2u1IOSju67c0qW29dx86p5n6JZdLqNhsOjQ81ToHpQML2
# S/X2Nv0uyZTSzjdriBvkyOnM6L35wpZ2qyPrRekfnwzUNKEyHN9b+WTqAZdvCrm1
# eKrs87HQ7u3XUu3lR43fFCVlAgpstsF2I9UyyiMMEqGlKAjllDzgy7U3SYaP04Zm
# pgv7cLt1jgh5GoLB7TC/XRdy1P7Ya1cZ76tL2Uj93CF4w7E2vtHtVzCA6YQk9kVJ
# jn9pxjYXw/qsoQgM2Ze7UI/d5MYqVHVPK83T5natq1sXf9ardmf2OGQWLrp1JaUl
# O8xeVpMR08tElxPlcEL+3zd5YAw4QrNJ9D7GhfJQWKOgnOkT/4Kslcyqp8wLP4/D
# oeNVrv/aEXA8Lf+ozHyIEejmmWJnmgHlAnfL+wi9KV1JzWAsskg5ClR8G3ZzAa69
# CUnS7mOSnsw=
# =N/we
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 13 Jan 2026 12:12:55 AM AEDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [unknown]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [unknown]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2026-01-12' of https://gitlab.com/thuth/qemu:
tests/functional/s390x: Add reverse debugging test for s390x
target/s390x: Fix infinite loop during replay
target/s390x: Un-inline s390_is_pv()
target/s390x: Simplify S390_ADAPTER_SUPPRESSIBLE definition
target/s390x: Remove unused 'gdbstub/helpers.h' header in helper.c
target/s390x: Replace target_ulong -> uint64_t in gdb_write_register()
target/s390x: Use vaddr for $pc in get_next_pc()
target/s390x: Restrict WatchPoint API to TCG
docs: update copyright year to 2026
tests/functional: Add a generic test that checks the files with pylint
tests/functional/aarch64/test_smmu: Silence warning from pylint
tests/functional/aarch64/test_virt_gpu: Fix style issues
tests/functional/ppc64/test_hv: Silence warnings reported by pylint
tests/functional/mips/test_malta: Silence warnings reported by pylint
tests/functional: Add a pylintrc file
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Merge tag 'pull-ppc-for-11.0-20260112' of https://gitlab.com/harshpb/qemu into staging
First PPC PR for 11.0
- Snapshot support for several ppc devices
- Migration fix and OS level migration test for pseries
- Minor code cleanups
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEa4EM1tK+EPOIPSFCRUTplPnWj7sFAmlky2YACgkQRUTplPnW
# j7vXUg/8Dx/nsygeDspmhlmvqEWjyXm3fjIGnyCtSZWSkDkhh1x+uc0khFLuG8in
# 1Ep2D4qkGDBrdv079WzDKJDhgH21gTApA92xUsJFof2LLgN+MZOgi2Im6wR+Prtr
# EddB7jJ062fDDyMQWBdg+9jkl0+xuj+JE5JXPbXV0Fqu+t3rVJvn7c1b3uRXRrC9
# hgiss0xgTpXdVGnVjsQYLr3+iJ5Qcd7+6UhtRzTgv7S02IJRjpVoHSayBnKmzG9r
# eLqQMykyqU8drmQUruTk1nM2PRbaGTuRO+Swcld7SgqxOxxYIXD72f89B94kZKqM
# qZKv/C03EP30wS7/zJMwWsIEuXKM/oUwXl4i5C5eRUIa637VjcFEhuj0fCd8qxmz
# mUp6tVTYaGESpWUJA9TLZOkvLO9c4gumbTWa5valYeRWCLdXFQZgDg0wrwu7SL5M
# vdzKdnTMozkkKIY0W2Gk5j6E6aHpcGvNxREGrtI1BEUGKtGVzPjMHZmYDormSLIz
# lvgZj7JEncjkGv6uIYKMv1tT7Cbo2YxoGRWbx59PWpK9Ekl8307BMi2OtPYqZm7N
# CKS0lK+OM8CUP7Ao4nwxzH+T6X+C88Ivjt31sS25ixdUK6+Wy8tCEK2XCwA8gxjH
# QuBMDYMoAWgZ+mQITNy+HrqM1TBI8a4PiF9DjX2xj3sdyBd67F8=
# =2zBL
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 12 Jan 2026 09:22:30 PM AEDT
# gpg: using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB
# gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [undefined]
# gpg: aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D 2142 4544 E994 F9D6 8FBB
* tag 'pull-ppc-for-11.0-20260112' of https://gitlab.com/harshpb/qemu:
tests/functional: Add a OS level migration test for pseries
target/ppc: Fix env->quiesced migration
hw/ppc: Add VMSTATE information to PnvPsi
hw/ppc: pnv_chiptod.c add vmstate support
hw/ppc: pnv_core.c add vmstate support
hw/ppc: pnv_adu.c added vmstate support
hw/ppc: Add pnv_i2c vmstate support
hw/ppc: Add pnv_spi vmstate support
hw/ppc: Add VMSTATE information for LPC model
target/ppc/kvm : Use macro names instead of hardcoded constants as return values
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Merge tag 'pull-loongarch-20260112' of https://github.com/bibo-mao/qemu into staging
loongarch queue
# -----BEGIN PGP SIGNATURE-----
#
# iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCaWSdwgAKCRAfewwSUazn
# 0cwwAQC4xgK0x98Z10yoMfuIz5FfDq1onrFC7rd5k0K7pLgsywEA1NrLtW/lSy6Z
# xlgaus/3reiDz+zEOeBQPLibVIVQSA0=
# =8ksY
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 12 Jan 2026 06:07:46 PM AEDT
# gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C
# Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1
* tag 'pull-loongarch-20260112' of https://github.com/bibo-mao/qemu:
hw/loongarch/virt: Add property highmem-mmio-size with virt machine
hw/loongarch/virt: Add high MMIO support with GPEX host
hw/loongarch/virt: Add property highmem_mmio with virt machine
hw/loongarch/virt: Get PCI info from gpex config info
hw/loongarch/virt: Get irq number from gpex config info
hw/loongarch/virt: Add field gpex in LoongArchVirtMachineState
hw/loongarch/virt: Add field ram_end in LoongArchVirtMachineState
target/loongarch: Add PMU register dump support in KVM
target/loongarch: Call function loongarch_la464_init_csr() after realized
target/loongarch: Add PMU migration support in KVM mode
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
William Hooper [Mon, 22 Dec 2025 00:26:34 +0000 (16:26 -0800)]
target/m68k: Improve CHK and CHK2; implement CMP2
Some CHK2 (Check Register Against Bounds) instructions, such as opcode
02FA, cause spurious illegal instruction exceptions, despite being valid
on Motorola MC68020 and later processors and used in existing software.
With this patch, QEMU:
- Translates CHK2 and CMP2 (Compare Register Against Bounds)
instructions [1] having any valid size or effective address. CHK2 and
CMP2 use the same opcodes but differ in bit 11 of the extension word.
(BITREV or BYTEREV instructions for ColdFire family processors [2],
which use similar opcodes, are not captured, however.)
- Implements CMP2, which "is identical to CHK2 except that it sets
condition codes rather than taking an exception" [1].
- Populates the correct "logical address of the instruction following
the instruction that caused the trap" [3] in the exception stack frame
for CHK and CHK2 exceptions, according to the number of words in the
instruction, including extension words, rather than default lengths.
An existing test for CHK2 is enabled, and tests are added for CHK, CHK2,
and CMP2.
References:
[1] Motorola M68000 Family Programmer's Reference Manual (M68000PM/AD),
Rev. 1, 1992, pages 4-72 to 4-73 and 4-82 to 4-83.
[2] Freescale Semiconductor, ColdFire Family Programmer's Reference Manual
(CFPRM), Rev. 3, 2005, pages 4-19 and 4-26.
[3] Motorola M68040 User's Manual (M68040UM/AD), 1993, page 8-8.
Laurent Vivier [Fri, 26 Dec 2025 21:37:07 +0000 (22:37 +0100)]
m68k: fix CAS2 writeback when Dc1==Dc2
According to Programmer's Reference Manual, if Dc1 and Dc2 specify the
same data register and the comparison fails, memory operand 1 is stored
in the data register.
The current helpers wrote Dc1 then Dc2, leaving operand 2 in the shared
register.
Swap the writeback order for cas2w/cas2l so memory operand 1 wins.
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251226213707.331741-1-laurent@vivier.eu>
Replaying even trivial s390x kernels hangs, because:
- cpu_post_load() fires the TOD timer immediately.
- s390_tod_load() schedules work for firing the TOD timer.
- If rr loop sees work and then timer, we get one timer expiration.
- If rr loop sees timer and then work, we get two timer expirations.
- Record and replay may diverge due to this race.
- In this particular case divergence makes replay loop spin: it sees that
TOD timer has expired, but cannot invoke its callback, because there
is no recorded CHECKPOINT_CLOCK_VIRTUAL.
- The order in which rr loop sees work and timer depends on whether
and when rr loop wakes up during load_snapshot().
- rr loop may wake up after the main thread kicks the CPU and drops
the BQL, which may happen if it calls, e.g., qemu_cond_wait_bql().
Firing TOD timer twice is duplicate work, but it was introduced
intentionally in commit 7c12f710bad6 ("s390x/tcg: rearm the CKC timer
during migration") in order to avoid dependency on migration order.
The key culprits here are timers that are armed ready expired. They
break the ordering between timers and CPU work, because they are not
constrained by instruction execution, thus introducing non-determinism
and record-replay divergence.
Fix by converting such timer callbacks to CPU work. Also add TOD clock
updates to the save path, mirroring the load path, in order to have the
same CHECKPOINT_CLOCK_VIRTUAL during recording and replaying.
Commit 1497c160661 ("s390x: add flags field for registering I/O
adapter") defined S390_ADAPTER_SUPPRESSIBLE twice, one when
KVM is available and another when it isn't. However both
definitions expand to the same value. Unify them, adding an
extra safety check in KVM-specific file.
This allows removing the target-specific 'CONFIG_KVM'
definition in "cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260107130807.69870-15-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
target/s390x: Remove unused 'gdbstub/helpers.h' header in helper.c
"gdbstub/helpers.h" uses target-specific symbols, but we don't
need it, so remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260107130807.69870-6-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
target/s390x: Replace target_ulong -> uint64_t in gdb_write_register()
On s390x target_ulong expands to uint64_t. Besides,
ldq_be_p() returns a uint64_t type. Use that instead.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260107130807.69870-5-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
DisasContextBase::pc_next is of vaddr type.
Since translator_lduw_end() returns a uint16_t,
also use that type for clarity.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260107130807.69870-4-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
By inverting the 'tcg_enabled()' check in s390_cpu_set_psw()
we can let the compiler elide the s390_cpu_recompute_watchpoints()
call when TCG is not available. Move this function -- along with
s390x_cpu_debug_excp_handler() which was introduced in the same
commit 311918b979c ("target-s390x: PER storage-alteration event
support") -- to a TCG specific file to avoid compiling dead code
on KVM. This restricts the WatchPoint API calls to TCG.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260107130807.69870-2-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Mon, 27 Oct 2025 13:22:59 +0000 (14:22 +0100)]
tests/functional: Add a generic test that checks the files with pylint
To avoid that new pylint-related warnings get committed, let's check
the files with pylint during each run (similar to what we are doing
for the iotests already).
Message-Id: <20251119082636.43286-16-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Thu, 13 Nov 2025 12:47:14 +0000 (13:47 +0100)]
tests/functional/aarch64/test_smmu: Silence warning from pylint
Pylint thinks that the accel variable might be used here without
being set first, since it does not know that skipTest() never
returns. Thus initialize "accel = None" here to make it happy.
Message-Id: <20251119082636.43286-14-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Reshuffle the import statements according to the suggestions from pylint,
use lowercase letters for variable names, and drop some spaces that flake8
did not like.
Message-Id: <20251119082636.43286-12-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Wed, 29 Oct 2025 15:49:54 +0000 (16:49 +0100)]
tests/functional/ppc64/test_hv: Silence warnings reported by pylint
To make pylint happy here, remove unused variables, switch to f-string,
use "check=True" when calling subprocess.run() and split a line that was
too long.
Message-Id: <20251119082636.43286-7-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Tue, 28 Oct 2025 10:56:41 +0000 (11:56 +0100)]
tests/functional/mips/test_malta: Silence warnings reported by pylint
Pylint complains about too many positional arguments for the
mips_check_wheezy() function. Add a "*" to enforce that the later
ones are passed with an argument name (all calling sites are doing
this already).
Also turn some old-school format strings into proper f-strings now.
Message-Id: <20251119082636.43286-6-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Fri, 24 Oct 2025 12:14:40 +0000 (14:14 +0200)]
tests/functional: Add a pylintrc file
Add a pylintrc file that can be used for checking the python code of
the functional tests. For the beginning, we use some rather lax settings.
We still can refine them later if we think that there's a need for it.
Message-Id: <20251119082636.43286-2-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Fabiano Rosas [Fri, 9 Jan 2026 12:35:19 +0000 (09:35 -0300)]
tests/functional: Add a OS level migration test for pseries
There's currently no OS level test for ppc64le. Add one such test by
reusing the boot level tests that are already present.
The test boots the source machine, waits for it to reach a mid-boot
message, migrates and checks that the destination has reached the
final boot message (VFS error due to no disk).
Fabiano Rosas [Fri, 9 Jan 2026 12:35:18 +0000 (09:35 -0300)]
target/ppc: Fix env->quiesced migration
The commit referenced (from QEMU 10.0) has changed the way the pseries
machine marks a cpu as quiesced. Previously, the cpu->halted value
from QEMU common cpu code was (incorrectly) used. With the fix, the
env->quiesced variable starts being used, which improves on the
original situation, but also causes a side effect after migration:
The env->quiesced is set at reset and never migrated, which causes the
destination QEMU to stop delivering interrupts and hang the machine.
To fix the issue from this point on, start migrating the env->quiesced
value.
For QEMU versions < 10.0, sending the new element on the stream would
cause migration to be aborted, so add the appropriate compatibility
property to omit the new subsection.
Independently of this patch, all migrations from QEMU versions < 10.0
would result in a hang since the older QEMU never migrates
env->quiesced. This is bad because it leaves machines already running
on the old QEMU without a migration path into newer versions.
As a workaround, use a few heuristics to infer the new value of
env->quiesced based on cpu->halted, LPCR and PSSCR bits that are
usually set/cleared along with quiesced.
Note that this was tested with -cpu power9 and -machine ic-mode=xive
due to another bug affecting migration of XICS guests. Tested both
forward and backward migration and savevm/loadvm from 9.2 and 10.0.
Also tested loadvm of a savevm image that contains a mix of cpus both
halted and not halted.
Bibo Mao [Mon, 12 Jan 2026 06:58:01 +0000 (14:58 +0800)]
hw/loongarch/virt: Add property highmem-mmio-size with virt machine
The default high mmio size of GPEX PCIE host controller is 64G bytes on
virt machine. If it does not meet requirements with some pass-throught HW
devices in future, it can be adjust dynamically, here adds property
highmem-mmio-size to set high mmio size.
Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
Bibo Mao [Fri, 17 Oct 2025 06:45:21 +0000 (14:45 +0800)]
hw/loongarch/virt: Add property highmem_mmio with virt machine
On LoongArch Virt Machine, MMIO region with GPEX host bridge is
0x40000000 -- 0x7FFFFFFF. The total size is 1G bytes and it is enough
for emulated virtio devices basically.
However on some conditions such as hostmem is added with virtio-gpu
device, the command line is -device virtio-gpu-gl,hostmem=4G. The
PCIE MMIO region is not enough, 64-bit high MMIO region is required.
Here add property highmem_mmio with virt machine, however it brings
out incompatible issue. Here the default value is false.
Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
Bibo Mao [Fri, 17 Oct 2025 06:45:18 +0000 (14:45 +0800)]
hw/loongarch/virt: Add field gpex in LoongArchVirtMachineState
Add field gpex in structure LoongArchVirtMachineState, type of field gpex
is structure GPEXConfig and it is to record configuration information
about GPEX host bridge. And remove field pci_bus in structure
LoongArchVirtMachineState since the information is in field gpex already.
Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
Bibo Mao [Fri, 17 Oct 2025 06:45:17 +0000 (14:45 +0800)]
hw/loongarch/virt: Add field ram_end in LoongArchVirtMachineState
DRAM region is dynamically set and the last valid physical address region
with LoongArch Virt Machine. To record the last valid physical address,
field ram_end is added in structure LoongArchVirtMachineState. In future
end address of DRAM cannot exceed base addres of PCIE 64-bit MMIO region.
Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
Bibo Mao [Thu, 30 Oct 2025 08:17:23 +0000 (16:17 +0800)]
target/loongarch: Call function loongarch_la464_init_csr() after realized
When CPU is realized, it will check capability of host and set guest
features, such as PMU CSR register number used by VM etc. Here move
function call with loongarch_la464_init_csr() after CPU is realized.
Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
Caleb Schlossin [Mon, 5 Jan 2026 16:01:38 +0000 (10:01 -0600)]
hw/ppc: Add VMSTATE information to PnvPsi
PnvPsi needs to be able to save/load snapshots. Add VMSTATE information
to the device class and a post_load() method to restore dynamic data items and
memory region mappings.
Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Aditya Gupta <adityag@linux.ibm.com> Reviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20260105160138.3242709-8-calebs@linux.ibm.com Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
projects / thirdparty / qemu.git / log
