Jamin Lin [Fri, 2 Jan 2026 09:07:45 +0000 (17:07 +0800)]
hw/i2c/aspeed: Fix wrong I2CC_DMA_LEN when I2CM_DMA_TX/RX_ADDR set first
In the previous design, the I2C model would update I2CC_DMA_LEN (0x54) based on
the value of I2CM_DMA_LEN (0x1C) when the firmware set either I2CM_DMA_TX_ADDR
(0x30) or I2CM_DMA_RX_ADDR (0x34). However, this only worked correctly if the
firmware set I2CM_DMA_LEN before setting I2CM_DMA_TX_ADDR or I2CM_DMA_RX_ADDR.
If the firmware instead set I2CM_DMA_TX_ADDR or I2CM_DMA_RX_ADDR before setting
I2CM_DMA_LEN, the value written to I2CC_DMA_LEN would be incorrect.
To fix this issue, the model should be updated to set I2CC_DMA_LEN when the
firmware writes to the I2CM_DMA_LEN register, rather than when it writes to the
I2CM_DMA_RX_ADDR and I2CM_DMA_TX_ADDR registers.
Jamin Lin [Fri, 2 Jan 2026 09:07:44 +0000 (17:07 +0800)]
hw/intc/aspeed: Remove TSP 128 - 138
The SSP interrupts 128 - 138 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Jamin Lin [Fri, 2 Jan 2026 09:07:43 +0000 (17:07 +0800)]
hw/intc/aspeed: Remove SSP 128 - 138
The SSP interrupts 128 - 138 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Jamin Lin [Mon, 1 Sep 2025 04:08:07 +0000 (12:08 +0800)]
docs/specs/aspeed-intc: Remove GIC 128 - 136
The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Jamin Lin [Mon, 1 Sep 2025 04:08:06 +0000 (12:08 +0800)]
hw/intc/aspeed: Remove GIC 128 - 136
The GIC interrupts 128 - 136 were only used by the AST2700 A0 SoC.
Since the AST2700 A0 has been deprecated, these interrupt
definitions are no longer needed. This commit removes them to
clean up the codebase.
Jamin Lin [Mon, 1 Sep 2025 04:08:05 +0000 (12:08 +0800)]
hw/arm/aspeed_ast27x0: Remove ast2700-a0 SOC
The ast2700-a1 SOC represented the first revision of the AST2700 and
was intended as an early engineering sample rather than a production
platform. A newer revision, A1, is now supported, and the ast2700-a1
SOC should replace the older A0 version.
Jamin Lin [Mon, 1 Sep 2025 04:08:04 +0000 (12:08 +0800)]
hw/arm: Remove ast2700a0-evb machine
The ast2700a0-evb machine represents the first revision of the AST2700 and
serves as the initial engineering sample rather than a production version.
A newer revision, A1, is now supported, and the ast2700a1-evb should replace
the older A0 version.
Yubin Zou [Fri, 19 Dec 2025 07:04:19 +0000 (07:04 +0000)]
test/qtest: Add Unit test for Aspeed SGPIO
This commit introduces a new qtest for the Aspeed SGPIO controller
The test covers the following:
- Setting and clearing SGPIO output pins and verifying the pin state.
- Setting and clearing SGPIO input pins and verifying the pin state.
- Verifying that level-high interrupts are correctly triggered and cleared.
Yubin Zou [Fri, 19 Dec 2025 07:04:17 +0000 (07:04 +0000)]
hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers
This commit updates the Aspeed SoC model to support two SGPIO
controllers, reflecting the hardware capabilities of the AST2700
The memory map and interrupt map are updated to include entries for
two SGPIO controllers (SGPIOM0 and SGPIOM1). This change is a
prerequisite for the full implementation of the SGPIO device model.
The SGPIO controller can generate interrupts based on various pin state
changes, such as rising/falling edges or high/low levels. This change
adds the necessary logic to detect these events, update the interrupt
status registers, and signal the interrupt to the SoC.
Yubin Zou [Fri, 19 Dec 2025 07:04:15 +0000 (07:04 +0000)]
hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins
The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are
implemented to get and set the level of individual SGPIO pins. These
are then exposed as boolean properties on the SGPIO device object.
Yubin Zou [Fri, 19 Dec 2025 07:04:14 +0000 (07:04 +0000)]
hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO
This initial implementation includes the basic device structure,
memory-mapped register definitions, and read/write handlers for the
SGPIO control registers.
Use ipmitool/frugen tool to generate a Cable Cart image based on a
sanitized set of data from a real device EEPROM. The EEPROM
bus/address did not match device tree for one of the EEPROMs so move
it from bus 13 / 55 to bus 12 / 54.
Jamin Lin [Wed, 12 Nov 2025 03:05:49 +0000 (11:05 +0800)]
docs/system/arm/aspeed: Update Aspeed MiniBMC section to include AST1060 processor
Added details describing AST1060 as a Platform Root of Trust processor board alongside
AST1030 MiniBMC, and extended the list of missing devices to include
SMBus Filter and QSPI Monitor controllers.
Jamin Lin [Wed, 12 Nov 2025 03:05:48 +0000 (11:05 +0800)]
docs/system/arm/aspeed: Update Aspeed and 2700 family boards list
Remove the ast2700-evb entry from the Aspeed family boards list in
the documentation. The AST2700 platform now belongs to the new Aspeed
2700 family group, which has its own dedicated documentation section
and board definitions.
Update the Aspeed 2700 family boards list in the documentation to include
the new ast2700fc board entry.
Jamin Lin [Wed, 12 Nov 2025 03:05:47 +0000 (11:05 +0800)]
tests/functional/arm/test_aspeed_ast1060: Add functional tests for Aspeed AST1060 SoC
Add functional tests for the Aspeed AST1060 SoC and its evaluation board.
The new test test_aspeed_ast1060.py validates booting the AST1060 EVB
machine using the Zephyr OS and ASPEED PROT application (ast1060_prot_v03.02.tgz)
and ensures basic console functionality.
Jamin Lin [Wed, 12 Nov 2025 03:05:46 +0000 (11:05 +0800)]
hw/arm/aspeed_ast10x0_evb: Add AST1060 EVB machine support
Add a new machine definition ast1060-evb to support the Aspeed AST1060
evaluation board. The new EVB reuses the same MiniBMC framework used by
AST1030, as both SoCs share the same core peripherals and controller
designs.
The AST1060 EVB machine initializes the ast1060-a2 SoC and sets the
FMC and SPI flash models (w25q80bl and w25q02jvm) for simulation.
This enables QEMU to boot and emulate firmware images for AST1060-based
platforms.
Jamin Lin [Wed, 12 Nov 2025 03:05:45 +0000 (11:05 +0800)]
hw/arm/aspeed_ast10x0: Add AST1060 SoC support
Add initial support for the Aspeed AST1060 SoC. The AST1060 reuses most
of the AST1030 peripheral device models, as the two SoCs share nearly
the same controllers including WDT, SCU, TIMER, HACE, ADC, I2C, FMC,
and SPI.
A new common initialization and realization framework (ast10x0_init
and ast10x0_realize) is leveraged so AST1060 can instantiate the
existing AST1030 models without redefining duplicate device types.
Jamin Lin [Wed, 12 Nov 2025 03:05:44 +0000 (11:05 +0800)]
hw/arm/aspeed_ast10x0: Pass SoC name to common init for AST10x0 family reuse
Refactor the AST10x0 common initialization to accept a socname
parameter.
The AST1030 model can be reused by AST1060 since they share most of the
same controllers. This approach allows AST1060 to leverage the existing
AST1030 initialization flow while keeping separate SoC-specific init
functions for components that differ.
This prepares the framework for AST1060 support, allowing it to reuse
AST1030 device models and initialization flow without code duplication.
Jamin Lin [Wed, 12 Nov 2025 03:05:43 +0000 (11:05 +0800)]
hw/arm/aspeed_ast10x0: Add common realize function for AST10x0 SoCs
Introduce a new common realize function aspeed_soc_ast10x0_realize()
for AST10x0 series SoCs. The shared initialization and realization logic
is now placed in this common function to improve code reuse and reduce
duplication between different SoCs in the same family.
The AST1030 realization function aspeed_soc_ast1030_realize() is
updated to call the new common routine and then perform realization of
its own specific devices such as LPC and PECI, which are not present on
future SoCs like AST1060.
This refactor simplifies maintenance and prepares the framework for
adding AST1060 support.
Jamin Lin [Wed, 12 Nov 2025 03:05:42 +0000 (11:05 +0800)]
hw/arm/aspeed_ast10x0: Add common init function for AST10x0 SoCs
Introduce a new common initialization function
aspeed_soc_ast10x0_init() for AST10x0 series SoCs. This separates the
shared initialization logic from the AST1030-specific part, allowing
reuse by future SoCs such as AST1060.
The AST1060 does not include the LPC and PECI models, so the common
initializer is used for all shared modules, while
aspeed_soc_ast1030_init() adds initialization of LPC and PECI, which
are unique to AST1030.
This refactor improves code reuse and prepares the codebase for
supporting the AST1060 platform.
Add a new silicon revision constant AST1060_A2_SILICON_REV for the
AST1060 SoC. This allows the SCU model and related SoC layers to
identify and handle AST1060 A2 revision properly in the same way as
other Aspeed SoC families.
Jamin Lin [Wed, 12 Nov 2025 03:05:40 +0000 (11:05 +0800)]
hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2600 and AST1030
According to the design of the AST2600, it has a Silicon Revision ID
Register, specifically SCU004 and SCU014, to set the Revision ID for the
AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is
set to 0x05030303.
In the "aspeed_ast2600_scu_reset" function, the hardcoded value
"AST2600_A3_SILICON_REV" was used for SCU004, while "s->silicon_rev" was
used for SCU014. The value of "s->silicon_rev" is set by the SoC layer
via the "silicon-rev" property. This patch aligns both SCU004 and SCU014
to use "s->silicon_rev" for consistency and flexibility.
Similarly, the "aspeed_ast1030_scu_reset" function also used a fixed
revision constant ("AST1030_A1_SILICON_REV"). This change updates it to
use the same "s->silicon_rev" property, ensuring that both SoCs follow
a consistent and configurable revision handling mechanism.
Jamin Lin [Wed, 12 Nov 2025 03:05:39 +0000 (11:05 +0800)]
hw/block/m25p80: Add SFDP table for Winbond W25Q02JVM flash
Add the SFDP data table for Winbond W25Q02JVM flash device. The table
was generated under Linux kernel by dumping the SFDP content using
the following command:
Taylor Simpson [Fri, 14 Nov 2025 23:00:13 +0000 (16:00 -0700)]
Hexagon (target/hexagon) s/log_write/gen_write
These functions don't "log" anything, they just generate the write
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Note there are two functions impacted
gen_log_vreg_write -> gen_vreg_write
gen_log_vreg_write_pair -> gen_vreg_write_pair
These functions don't "log" anything, they just generate the write
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
The function doesn't "log" anything, it just generates the write
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Taylor Simpson [Fri, 14 Nov 2025 23:00:10 +0000 (16:00 -0700)]
Hexagon (target/hexagon) Remove gen_log_reg_write
The gen_log_reg_write function is a memnant of the original Hexagon
target design. With the addition of gen_analyze_funcs.py and the
ability to short-circuit a packet commit, this function can be
removed.
Note that the implementation of gen_log_reg_write contains a check
of the register mutability mask. This is only needed for control
registers, so we move it to gen_write_ctrl_reg.
We do need the gen_log_reg_write_pair function, but the name is
now misleading, so we change the name go gen_write_reg_pair.
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Taylor Simpson [Tue, 25 Mar 2025 02:14:40 +0000 (20:14 -0600)]
Hexagon (target/hexagon) analyze all reads before writes
I noticed that analyze_packet is marking the implicit pred reads after
marking all the writes. However, the semantics of the instrucion and
packet are to do all the reads, then do the operation, then do all the
writes.
Here is the old code
static void analyze_packet(DisasContext *ctx)
{
Packet *pkt = ctx->pkt;
ctx->read_after_write = false;
ctx->has_hvx_overlap = false;
for (int i = 0; i < pkt->num_insns; i++) {
Insn *insn = &pkt->insn[i];
ctx->insn = insn;
if (opcode_analyze[insn->opcode]) {
opcode_analyze[insn->opcode](ctx);
}
mark_implicit_reg_writes(ctx);
mark_implicit_pred_writes(ctx);
mark_implicit_pred_reads(ctx);
}
ctx->need_commit = need_commit(ctx);
}
Recall that opcode_analyze[insn->opcode](ctx) will mark all the
explicit reads then all the explicit writes.
To properly handle the semantics, we'll create two new functions
mark_implicit_reads
mark_implicit_writes
Then we change gen_analyze_funcs.py to add a call to the former
after all the explicit reads and a call to the latter after all
the explicit_writes.
The reason this is an RFC patch is I can't find any instructions
where this distinction makes a difference in ctx->need_commit which
determines if the packet commit can be short-circuited. However, this
could change in the future if the architecture introduces an
instruction with an implicit read of a register that is also written
(either implicit or explicit). Then, anlayze_packet would detect
a read-after-write, and the packet would not short-circuit. The
execution would be correct, but the performance would not be optimal.
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Tested-by: Brian Cain <brian.cain@oss.qualcomm.com>
Message-Id: <20250325021440.81386-1-ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Taylor Simpson [Wed, 5 Nov 2025 21:25:54 +0000 (14:25 -0700)]
Hexagon (tests/tcg/hexagon) Add test for USR changes in packet
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Taylor Simpson [Wed, 5 Nov 2025 21:25:53 +0000 (14:25 -0700)]
Hexagon (target/hexagon) Implicit writes to USR don't force packet commit
Implicit writes to USR are only to specific fields of USR to indicate
side effects (e.g., saturation overflow, floating point status).
In these cases, we don't force a packet commit. This will allow more
packets to be short-circuited (avoid writing the results to temporaries).
When there is a packet commit with an implicit write to USR, we initialize
new_value_usr during gen_start_packet and write to USR in gen_reg_writes.
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Taylor Simpson [Wed, 5 Nov 2025 21:25:52 +0000 (14:25 -0700)]
Hexagon (target/hexagon) Add pkt_need_commit argument to arch_fpop_end
The arch_fpop_end function converts the softfloat fp_status flags to
bits set in Hexagon USR. It is hard-coded that the packet must need
a commit. We add an argument to the function and update all the helper
call sites.
In a subsequent commit, we will change the code that forces a commit
when the packet contains an floating point instruction.
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
This can easily be done in C with opcodes_def_generated.h.inc
Note that gen_tcg_func_table.py has some logic to skip instructions.
However, there aren't any instructions currently in the code that would
be skipped by this logic. So, it is safe to base the table on the
complete opcodes table.
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Tested-by: Brian Cain <brian.cain@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Merge tag 'hw-misc-20251230' of https://github.com/philmd/qemu into staging
Misc HW patches
- Remove few target_ulong uses
- Make human monitor non-target specific
- Better name for TrustZone Peripheral Protection Controller memory regions
- Do not expose DEVICE_NATIVE_ENDIAN on Rust
- Remove address_space_stl_notdirty() and stl_phys_notdirty()
- Allow to restrict targets to legacy ldst_phys() API
- Fix MinGW-w64 link failure due to ConvertStringToBSTR()
- Header cleanups
- MAINTAINERS updates
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# gpg: Signature made Wed 31 Dec 2025 08:06:25 AM AEDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'hw-misc-20251230' of https://github.com/philmd/qemu: (34 commits)
MAINTAINERS: Change email and status of TriCore
MAINTAINERS: remove old email for Bandan Das
meson: Optimize summary_info about directories
hw/i2c/imx: Fix trace func name error
util: Move qemu_ftruncate64 from block/file-win32.c to oslib-win32.c
qga/vss-win32: Fix ConvertStringToBSTR redefinition with newer MinGW
configs/targets: Mark targets not using legacy ldst_phys() API
hw/virtio: Reduce virtio_lduw/stw_phys_cached() scope
hw/virtio: Remove unused ldst_phys() helpers
configs/targets: Mark targets not using legacy ldst_phys() API
system/memory: Allow restricting legacy ldst_phys() API usage
system/memory: Remove address_space_stl_notdirty and stl_phys_notdirty
hw/arm: Avoid address_space_stl_notdirty() when generating bootloader
target/sparc: Update MMU page table using stl_phys()
target/i386: Remove x86_stl_phys_notdirty() leftover
target/hexagon: Include missing 'cpu.h' header in 'internal.h'
rust/system: Stop exposing bogus DEVICE_NATIVE_ENDIAN symbol
hw/char/pl011: Mark implementation as being little-endian
hw/timer/hpet: Mark implementation as being little-endian
hw/misc/pvpanic: Expose MMIO interface as little-endian
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
I'm no longer employed at the university of Paderborn. This also means
my time available for QEMU has reduced significantly. Thus, I'm dropping
the status to odd fixes.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251227132135.4886-1-kbastian@mail.uni-paderborn.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Stefan Hajnoczi [Fri, 26 Dec 2025 08:32:06 +0000 (09:32 +0100)]
MAINTAINERS: remove old email for Bandan Das
Bandan recently left Red Hat and emails to his old address now result in
bounce messages. I contacted Bandan and he asked me to remove his old
address on his behalf.
Reported-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251226083207.506850-1-stefanha@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bin Guo [Fri, 19 Dec 2025 23:04:55 +0000 (07:04 +0800)]
meson: Optimize summary_info about directories
Clear summary_info first, otherwise there will be redundant output
about build environment.
Signed-off-by: Bin Guo <guobin@linux.alibaba.com> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251219230456.37178-1-guobin@linux.alibaba.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
util: Move qemu_ftruncate64 from block/file-win32.c to oslib-win32.c
qemu_ftruncate64() is a general-purpose utility function that may be
used outside of the block layer. Move it to util/oslib-win32.c where
other Windows-specific utility functions reside.
Signed-off-by: Nguyen Dinh Phi <phind.uet@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20251218085446.462827-3-phind.uet@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
qga/vss-win32: Fix ConvertStringToBSTR redefinition with newer MinGW
Newer versions of MinGW-w64 provide ConvertStringToBSTR() in the
_com_util namespace via <comutil.h>. This causes a redefinition
error when building qemu-ga on Windows with these toolchains.
Add a meson check to detect whether ConvertStringToBSTR is already
available, and conditionally compile our fallback implementation
only when the system does not provide one.
configs/targets: Mark targets not using legacy ldst_phys() API
Luckily these targets don't use the legacy ldst_phys() API at
all. Set the TARGET_NOT_USING_LEGACY_LDST_PHYS_API variable to
hide the API to them, avoiding further API uses to creep in.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251224151351.86733-7-philmd@linaro.org>
system/memory: Allow restricting legacy ldst_phys() API usage
Commit 500131154d6 ("exec.c: Add new address_space_ld*/st*
functions") added a new API to fix a shortcoming of the
ld/st*_phys() API, which does blind bus access, not reporting
failure (and it also allow to provide transaction attributes).
Later commit 42874d3a8c6 ("Switch non-CPU callers from ld/st*_phys
to address_space_ld/st*") automatically converted the legacy uses
to the new API, not precising transaction attributes
(MEMTXATTRS_UNSPECIFIED) and ignoring the transation result (passing
NULL pointer as MemTxResult).
While this is a faithful replacement, without any logical change,
we later realized better is to not use MEMTXATTRS_UNSPECIFIED or
NULL MemTxResult, and adapt each call site on a pair basis, looking
at the device model datasheet to do the correct behavior (which is
unlikely to ignore transaction failures).
Since this is quite some work, we defer that to device model
maintainers. Meanwhile we introduce a definition, to allow a
target which removed all legacy API call to prohibit further
legacy API uses, named "TARGET_NOT_USING_LEGACY_LDST_PHYS_API".
Since all targets should be able to check this definition, we
take care to not poison it.
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251224151351.86733-6-philmd@linaro.org>
system/memory: Remove address_space_stl_notdirty and stl_phys_notdirty
stl_phys_notdirty() was added in commit 8df1cd076cc ("physical memory
access functions") as a (premature?) optimisation for the CODE path.
Meanwhile 20 years passed, we might never have understood / used it
properly; the code evolved and now the recommended way to access the
CODE path is via the cpu_ld/st_mmu*() API.
Remove both address_space_stl_notdirty() and stl_phys_notdirty()
leftovers.
Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251224151351.86733-5-philmd@linaro.org>
hw/arm: Avoid address_space_stl_notdirty() when generating bootloader
When using the '-kernel' command line option, a bootloader is
emitted, calling address_space_stl_notdirty().
The _notdirty() variant is supposed to /not/ mark the updated
CODE page as dirty, to not re-translate it. However this code
is only used with the '-kernel' CLI option after the machine
is created and /before/ the vCPUs run, and *only* during the
first (cold) reset; not during following (hot) resets. The
optimisation is totally not justified, since we haven't
translated any guest code yet.
Replace by the normal address_space_stl() helper.
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251224151351.86733-4-philmd@linaro.org>
target/sparc: Update MMU page table using stl_phys()
stl_phys_notdirty() is supposed to do an optimized CODE
path store. Here we update the page table via the DATA
path, so can use the normal stl_phys() helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251224151351.86733-3-philmd@linaro.org>
target/hexagon: Include missing 'cpu.h' header in 'internal.h'
Both CPUHexagonState and TOTAL_PER_THREAD_REGS are defined
in "cpu.h" which is luckily indirectly included. However when
refactoring unrelated files we get:
In file included from target/hexagon/helper.h:18,
from include/exec/helper-proto.h.inc:56,
from include/exec/helper-proto.h:13,
from target/hexagon/op_helper.c:22:
target/hexagon/internal.h: At top level:
target/hexagon/internal.h:29:25: error: unknown type name ‘CPUHexagonState’; did you mean ‘CPUPluginState’?
29 | void hexagon_debug_vreg(CPUHexagonState *env, int regnum);
| ^~~~~~~~~~~~~~~
| CPUPluginState
target/hexagon/internal.h:30:25: error: unknown type name ‘CPUHexagonState’; did you mean ‘CPUPluginState’?
30 | void hexagon_debug_qreg(CPUHexagonState *env, int regnum);
| ^~~~~~~~~~~~~~~
| CPUPluginState
target/hexagon/internal.h:31:20: error: unknown type name ‘CPUHexagonState’; did you mean ‘CPUPluginState’?
31 | void hexagon_debug(CPUHexagonState *env);
| ^~~~~~~~~~~~~~~
| CPUPluginState
target/hexagon/internal.h:33:44: error: ‘TOTAL_PER_THREAD_REGS’ undeclared here (not in a function)
33 | extern const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS];
| ^~~~~~~~~~~~~~~~~~~~~
Fix that by including the missing header.
We don't need the "qemu/log.h" since commit 0cb73cb5a02 ("target/hexagon:
Remove HEX_DEBUG/HEX_DEBUG_LOG"): remove it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Message-Id: <20251224134644.85582-9-philmd@linaro.org>
rust/system: Stop exposing bogus DEVICE_NATIVE_ENDIAN symbol
We want to remove the bogus DEVICE_NATIVE_ENDIAN definition
(by only having it explicit, either big or little one). Stop
exposing it to rust devices to avoid it spreading further.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20251224134644.85582-8-philmd@linaro.org>
hw/char/pl011: Mark implementation as being little-endian
The PL011 component is only built / used by ARM targets, which
are only built in little endianness. Thus we only ever built
as little endian, never testing the big-endian possibility of
the DEVICE_NATIVE_ENDIAN definition. Simplify by only keeping
the little endian variant.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20251224134644.85582-7-philmd@linaro.org>
hw/timer/hpet: Mark implementation as being little-endian
The HPET component is only built / used by X86 targets, which
are only built in little endianness. Thus we only ever built
as little endian, never testing the big-endian possibility of
the DEVICE_NATIVE_ENDIAN definition. Simplify by only keeping
the little endian variant.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20251224134644.85582-6-philmd@linaro.org>
hw/char/serial: Let compiler pick serial_mm_ops[] array length
No need to enforce the MemoryRegionOps array length.
We index by device_endian enum, the compiler will easily
pick the correct length. Besides, this allow further
adjustments in the device_endian enum itself.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251224134644.85582-4-philmd@linaro.org>
This is a 32-bit implementation. Make that explicit in the
MemoryRegionOps structure (this doesn't change the maximum
access size, which -- being unset -- is 64-bit).
Move the structure just after the handlers to ease code review.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251224134644.85582-3-philmd@linaro.org>
hw/arm/Kconfig: Have FSL_IMX6UL SoC select IMX_USBPHY
Since commit 17372bd812d, the SoC used by the mcimx6ul-evk
machine requires the IMX USB PHY component.
As this component is only used by 2 machines, do not select
it by default (it will be automatically selected when
necessary).
Fixes: 17372bd812d ("hw/arm/fsl-imx6ul: Wire up USB controllers") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251224134644.85582-2-philmd@linaro.org>
monitor/hmp: Fix coding style in hmp-cmds-target.c
Previous to moving code contained in hmp-cmds-target.c,
fix the coding style. Otherwise the checkpatch.pl script
would report:
ERROR: space required before the open parenthesis '('
#134: FILE: monitor/hmp-cmds-target.c:152:
+ switch(format) {
ERROR: braces {} are necessary for all arms of this statement
#154: FILE: monitor/hmp-cmds-target.c:172:
+ if (l > line_size)
[...]
ERROR: space required before the open parenthesis '('
#172: FILE: monitor/hmp-cmds-target.c:190:
+ switch(wsize) {
ERROR: space required before the open parenthesis '('
#188: FILE: monitor/hmp-cmds-target.c:206:
+ switch(format) {
ERROR: Don't use '#' flag of printf format ('%#') in format strings, use '0x' prefix instead
#190: FILE: monitor/hmp-cmds-target.c:208:
+ monitor_printf(mon, "%#*" PRIo64, max_digits, v);
WARNING: line over 80 characters
#240: FILE: monitor/hmp-cmds-target.c:258:
+ error_setg(errp, "No memory is mapped at address 0x%" HWADDR_PRIx, addr);
WARNING: line over 80 characters
#245: FILE: monitor/hmp-cmds-target.c:263:
+ error_setg(errp, "Memory at address 0x%" HWADDR_PRIx " is not RAM", addr);
ERROR: Don't use '#' flag of printf format ('%#') in format strings, use '0x' prefix instead
#297: FILE: monitor/hmp-cmds-target.c:315:
+ monitor_printf(mon, "gpa: %#" HWADDR_PRIx "\n",
WARNING: line over 80 characters
#329: FILE: monitor/hmp-cmds-target.c:347:
+ ret = ((pinfo & 0x007fffffffffffffull) * pagesize) | (addr & (pagesize - 1));
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org>
Message-Id: <20251229231546.50604-7-philmd@linaro.org>
monitor/hmp: Use plain uint64_t @addr argument in memory_dump()
memory_dump() takes either hwaddr or vaddr type, depending
on the @is_physical argument. Simply use uint64_t type which
is common to both.
Pad address using field width formatting, removing the need
for the target_ulong type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org>
Message-Id: <20251229231546.50604-4-philmd@linaro.org>
monitor/hmp: Make memory_dump() @is_physical argument a boolean
Suggested-by: Dr. David Alan Gilbert <dave@treblig.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id: <20251229231546.50604-3-philmd@linaro.org>
monitor/hmp: Replace target_ulong -> vaddr in hmp_gva2gpa()
cpu_get_phys_page_debug() takes a vaddr type since commit 00b941e581b ("cpu: Turn cpu_get_phys_page_debug() into a CPUClass
hook").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dave@treblig.org>
Message-Id: <20251229231546.50604-2-philmd@linaro.org>
Alex Bennée [Mon, 15 Dec 2025 17:05:48 +0000 (17:05 +0000)]
hw/misc: make the tz-ppc-port names more useful
The TrustZone peripheral protection controller (tz-ppc) sits between
peripherals and the main system. However this results in "info mtree"
looking at bit confusing, especially as the sequence numbers can
overlap and miss steps:
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Jim MacArthur <jim.macarthur@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251215170548.2594651-1-alex.bennee@linaro.org>
[PMD: Wrap long line to avoid checkpatch.pl warning] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Anton Johansson [Wed, 10 Dec 2025 13:21:30 +0000 (14:21 +0100)]
hw/riscv: Treat kernel_start_addr as vaddr
Changes kernel_start_addr from target_ulong to vaddr. Logically, the
argument represents a virtual address at which to load the kernel image,
which gets treated as a hwaddr as a fallback if elf and uimage loading
fails.
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251210132130.14465-1-anjo@rev.ng> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bin Meng [Mon, 10 Nov 2025 10:43:11 +0000 (18:43 +0800)]
hw/sd: Remove unused header includes in ssi-sd.c
Remove these header files which are not used by ssi-sd.c
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251110104311.1640772-1-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* cleanup include/hw headers
* cleanup memory headers
* rust: preludes
* rust: support for dtrace
* rust/hpet: first part of reorganization
* meson: small cleanups
* target/i386: Diamond Rapids CPU model including CET, APX, AVX10.2
# -----BEGIN PGP SIGNATURE-----
#
# iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmlPov8UHHBib256aW5p
# QHJlZGhhdC5jb20ACgkQv/vSX3jHroPN1wf9HCceQ1273g7HbNeamay2bSaqypyM
# sEUBk4ipwO0dp7AYaaX5MeJ8NxeYcK82oFgm35WLY1tMOv0BZG5ez02dLoh5C4fb
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# ERJ2xo+D6a38w/uJ88KuqUV1BqYxNNwKmvOwVBU2xFB9o9bm20TNOJZ3+D+Ki8Aj
# idv+rU0XY1bWseo4USuozsqxfkjLJ5lj2YYUkSVO/I1wJmuO7Bq6xzrCxg==
# =/nIt
# -----END PGP SIGNATURE-----
# gpg: Signature made Sat 27 Dec 2025 08:12:31 PM AEDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [unknown]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (152 commits)
block: rename block/aio-wait.h to qemu/aio-wait.h
block: rename block/aio.h to qemu/aio.h
block: reduce files included by block/aio.h
block: extract include/qemu/aiocb.h out of include/block/aio.h
hw: add missing includes hidden by block/aio.h
qmp: Fix thread race
thread-pool: Fix thread race
dosc/cpu-models-x86: Add documentation for DiamondRapids
i386/cpu: Add CPU model for Diamond Rapids
i386/cpu: Define dependency for VMX_VM_ENTRY_LOAD_IA32_FRED
i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f
i386/cpu: Allow cache to be shared at thread level
i386/cpu: Allow unsupported avx10_version with x-force-features
i386/cpu: Add a helper to get host avx10 version
i386/cpu: Support AVX10.2 with AVX10 feature models
i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration
i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions
i386/cpu: Add support for MOVRS in CPUID enumeration
run: introduce a script for running devel commands
gitlab-ci: enable rust for msys2-64bit
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Paolo Bonzini [Wed, 3 Dec 2025 11:33:13 +0000 (12:33 +0100)]
block: rename block/aio.h to qemu/aio.h
AioContexts are used as a generic event loop even outside the block
layer; move the header file out of block/ just like the implementation
is in util/.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Wed, 3 Dec 2025 11:09:49 +0000 (12:09 +0100)]
block: reduce files included by block/aio.h
Avoid including all of qdev everywhere (the hw/core/qdev.h header in fact
brings in a lot more headers too), instead declare a couple structs for
which only a pointer type is needed.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Wed, 3 Dec 2025 11:39:24 +0000 (12:39 +0100)]
hw: add missing includes hidden by block/aio.h
hw/qdev/core.h being included by core headers means that it was quite
easy to forget including it, or anything that hw/qdev/core.h included.
Add the missing inclusions.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Zhao Liu [Mon, 15 Dec 2025 07:37:43 +0000 (15:37 +0800)]
dosc/cpu-models-x86: Add documentation for DiamondRapids
Current DiamondRapids hasn't supported cache model. Instead, document
its special CPU & cache topology to allow user emulate with "-smp" &
"-machine smp-cache".
Zhao Liu [Mon, 15 Dec 2025 07:37:42 +0000 (15:37 +0800)]
i386/cpu: Add CPU model for Diamond Rapids
According to table 1-2 in Intel Architecture Instruction Set Extensions
and Future Features (rev 059), Diamond Rapids has the following new
features which have already been supported for guest:
* SM4 (EVEX)
* Intel Advanced Vector Extensions 10 Version 2 (Intel AVX10.2)
* MOVRS and the PREFETCHRST2 instruction
* AMX-MOVRS, AMX-AVX512, AMX-FP8, AMX-TF32
* Intel Advanced Performance Extensions
And FRED - Flexible Return and Event Delivery (FRED) and the LKGS
instruction (introduced since Clearwater Forest & Diamond Rapids) - is
included in Diamond Rapids CPU model.
In addition, the following features are added into Diamond Rapids CPU
model:
* CET: Control-flow Enforcement Technology (introduced since Sapphire
Rapids & Sierra Forest).
Zhao Liu [Mon, 15 Dec 2025 07:37:40 +0000 (15:37 +0800)]
i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f
Many Intel CPUs enable CPUID 0x1f by default to encode CPU topology
information.
Add the "cpuid_0x1f" option to X86CPUDefinition to allow named CPU
models to configure CPUID 0x1f from the start, thereby forcing 0x1f
to be present for guest.
With this option, there's no need to explicitly add v1 model to an
unversioned CPU model for explicitly enabling the x-force-cpuid-0x1f
property.
Zhao Liu [Mon, 15 Dec 2025 07:37:39 +0000 (15:37 +0800)]
i386/cpu: Allow cache to be shared at thread level
In CPUID 0x4 leaf, it's possible to make the cache privated at thread
level when there's no HT within the core. In this case, while cache per
thread and cache per core are essentially identical, their topology
information differs in CPUID 0x4.
Diamond Rapids assigns the L1 i/d cache at the thread level. To allow
accurate emulation of DMR cache topology, remove the cache-per-thread
restriction in max_thread_ids_for_cache(), which enables CPUID 0x4 to
support cache per thread topology.
Given that after adding thread-level support, the topology offset
information required by max_thread_ids_for_cache() can be sufficiently
provided by apicid_offset_by_topo_level(), so it's straightforward to
re-implement max_thread_ids_for_cache() based on
apicid_offset_by_topo_level() to reduce redundant duplicate codes.
Zhao Liu [Mon, 15 Dec 2025 07:37:38 +0000 (15:37 +0800)]
i386/cpu: Allow unsupported avx10_version with x-force-features
The "force_features" ("x-force-features" property) forces setting
feature even if host doesn't support, but also reports the warning.
Given its function, it's useful for debug, so even if the AVX10
version is unsupported by host, force to set this AVX10 version if
x-force-features=on.
Zhao Liu [Mon, 15 Dec 2025 07:37:36 +0000 (15:37 +0800)]
i386/cpu: Support AVX10.2 with AVX10 feature models
Intel AVX10 Version 2 (Intel AVX10.2) includes a suite of new
instructions delivering new AI features and performance, accelerated
media processing, expanded Web Assembly, and Cryptography support, along
with enhancements to existing legacy instructions for completeness and
efficiency, and it is enumerated as version 2 in CPUID 0x24.0x0.EBX[bits
0-7] [*].
Considerring "Intel CPUs which support Intel AVX10.2 will include an
enumeration for AVX10_VNNI_INT (CPUID.24H.01H:ECX.AVX10_VNNI_INT[2])"
[*] and EVEX VPDP* instructions for INT8/INT16 (AVX10_VNNI_INT) are
detected by either AVX10.2 OR AVX10_VNNI_INT, AVX10_VNNI_INT is part of
AVX10.2, so any Intel AVX10.2 implementation lacking the AVX10_VNNI_INT
enumeration should be considered buggy hardware.
Therefore, it's necessary to set AVX10_VNNI_INT enumeration for Guest
when the user specifies AVX10 version 2. For this, introduce AVX10
models to explicitly define the feature bits included in different AVX10
versions.
Zhao Liu [Mon, 15 Dec 2025 07:37:35 +0000 (15:37 +0800)]
i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration
AVX10_VNNI_INT (0x24.0x1.ECX[bit 2]) is a discrete feature bit
introduced on Intel Diamond Rapids, which enumerates the support for
EVEX VPDP* instructions for INT8/INT16 [*].
Although Intel AVX10.2 has already included new VPDP* INT8/INT16 VNNI
instructions, a bit - AVX10_VNNI_INT - is still be separated. Relevant
new instructions can be checked by either CPUID AVX10.2 OR
AVX10_VNNI_INT (e.g., VPDPBSSD).
Support CPUID 0x24.0x1 subleaf with AVX10_VNNI_INT enumeration for
Guest.
Zhao Liu [Mon, 15 Dec 2025 07:37:34 +0000 (15:37 +0800)]
i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions
Intel Diamond Rapids adds new AMX instructions to support new formats
and memory operations [*]. And it introduces the CPUID subleaf 0x1E.0x1
to centralize the discrete AMX feature bits within EAX.
For new feature bits (CPUID 0x1E.0x1.EAX[bits 4,6-8]), it's
straightforward to add their enurmeration support.
In addition to the new features, CPUID 0x1E.0x1.EAX[bits 0-3] are
mirrored positions of existing AMX feature bits distributing across
the 0x7 leaves. It's not flexible to make these mirror bits have the
same names as existing ones, because QEMU would try to set both original
bit and mirror bit which would cause warning if host doesn't support
0x1E.0x1 subleaf. Thus, name these mirror bits with "*-mirror" suffix.
[*]: Intel Architecture Instruction Set Extensions and Future Features
(rev.059).
Zhao Liu [Mon, 15 Dec 2025 07:37:33 +0000 (15:37 +0800)]
i386/cpu: Add support for MOVRS in CPUID enumeration
MOVRS is a new set of instructions introduced in the Intel platform
Diamond Rapids, to load instructions that carry a read-shared hint.
Functionally, MOVRS family is equivalent to existing load instructions,
but its read-shared hint indicates the source memory location is likely
to become read-shared by multiple processors, i.e., read in the future
by at least one other processor before it is written (assuming it is
ever written in the future). It could optimize the behavior of the
caches, especially shared caches, for this data for future reads by
multiple processors. Additionally, MOVRS family also includes a software
prefetch instruction, PREFETCHRST2, that carries the same read-shared
hint. [*]
MOVRS family is enumerated by CPUID single-bit (0x7.0x1.EAX[bit 31]).
Add its enumeration support.
[*]: Intel Architecture Instruction Set Extensions and Future Features
(rev.059).
projects / thirdparty / qemu.git / log
