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13 months agoi386/tdx: Set kvm_readonly_mem_enabled to false for TDX VM
Xiaoyao Li [Thu, 8 May 2025 14:59:41 +0000 (10:59 -0400)] 
i386/tdx: Set kvm_readonly_mem_enabled to false for TDX VM

TDX only supports readonly for shared memory but not for private memory.

In the view of QEMU, it has no idea whether a memslot is used as shared
memory of private. Thus just mark kvm_readonly_mem_enabled to false to
TDX VM for simplicity.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-36-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Force exposing CPUID 0x1f
Xiaoyao Li [Thu, 8 May 2025 14:59:40 +0000 (10:59 -0400)] 
i386/tdx: Force exposing CPUID 0x1f

TDX uses CPUID 0x1f to configure TD guest's CPU topology. So set
enable_cpuid_0x1f for TDs.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-35-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f
Xiaoyao Li [Thu, 8 May 2025 14:59:39 +0000 (10:59 -0400)] 
i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f

Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e.,
when topology level that cannot be enumerated by leaf 0xB, e.g., die or
module level, are configured for the guest, e.g., -smp xx,dies=2.

However, TDX architecture forces to require CPUID 0x1f to configure CPU
topology.

Introduce a bool flag, enable_cpuid_0x1f, in CPU for the case that
requires CPUID leaf 0x1f to be exposed to guest.

Introduce a new function x86_has_cpuid_0x1f(), which is the wrapper of
cpu->enable_cpuid_0x1f and x86_has_extended_topo() to check if it needs
to enable cpuid leaf 0x1f for the guest.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-34-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: implement tdx_cpu_instance_init()
Xiaoyao Li [Thu, 8 May 2025 14:59:38 +0000 (10:59 -0400)] 
i386/tdx: implement tdx_cpu_instance_init()

Currently, pmu is not supported for TDX by KVM.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-33-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/cpu: introduce x86_confidential_guest_cpu_instance_init()
Xiaoyao Li [Thu, 8 May 2025 14:59:37 +0000 (10:59 -0400)] 
i386/cpu: introduce x86_confidential_guest_cpu_instance_init()

To allow execute confidential guest specific cpu init operations.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-32-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agokvm: Check KVM_CAP_MAX_VCPUS at vm level
Xiaoyao Li [Thu, 8 May 2025 14:59:36 +0000 (10:59 -0400)] 
kvm: Check KVM_CAP_MAX_VCPUS at vm level

KVM with TDX support starts to report different KVM_CAP_MAX_VCPUS per
different VM types. So switch to check the KVM_CAP_MAX_VCPUS at vm level.

KVM still returns the global KVM_CAP_MAX_VCPUS when the KVM is old that
doesn't report different value at vm level.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-31-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Wire TDX_REPORT_FATAL_ERROR with GuestPanic facility
Xiaoyao Li [Thu, 8 May 2025 14:59:35 +0000 (10:59 -0400)] 
i386/tdx: Wire TDX_REPORT_FATAL_ERROR with GuestPanic facility

Integrate TDX's TDX_REPORT_FATAL_ERROR into QEMU GuestPanic facility

Originated-from: Isaku Yamahata <isaku.yamahata@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-30-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Handle KVM_SYSTEM_EVENT_TDX_FATAL
Xiaoyao Li [Thu, 8 May 2025 14:59:34 +0000 (10:59 -0400)] 
i386/tdx: Handle KVM_SYSTEM_EVENT_TDX_FATAL

TD guest can use TDG.VP.VMCALL<REPORT_FATAL_ERROR> to request
termination. KVM translates such request into KVM_EXIT_SYSTEM_EVENT with
type of KVM_SYSTEM_EVENT_TDX_FATAL.

Add hanlder for such exit. Parse and print the error message, and
terminate the TD guest in the handler.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-29-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Enable user exit on KVM_HC_MAP_GPA_RANGE
Xiaoyao Li [Thu, 8 May 2025 14:59:33 +0000 (10:59 -0400)] 
i386/tdx: Enable user exit on KVM_HC_MAP_GPA_RANGE

KVM translates TDG.VP.VMCALL<MapGPA> to KVM_HC_MAP_GPA_RANGE, and QEMU
needs to enable user exit on KVM_HC_MAP_GPA_RANGE in order to handle the
memory conversion requested by TD guest.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-28-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Finalize TDX VM
Xiaoyao Li [Thu, 8 May 2025 14:59:32 +0000 (10:59 -0400)] 
i386/tdx: Finalize TDX VM

Invoke KVM_TDX_FINALIZE_VM to finalize the TD's measurement and make
the TD vCPUs runnable once machine initialization is complete.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-27-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Call KVM_TDX_INIT_VCPU to initialize TDX vcpu
Xiaoyao Li [Thu, 8 May 2025 14:59:31 +0000 (10:59 -0400)] 
i386/tdx: Call KVM_TDX_INIT_VCPU to initialize TDX vcpu

TDX vcpu needs to be initialized by SEAMCALL(TDH.VP.INIT) and KVM
provides vcpu level IOCTL KVM_TDX_INIT_VCPU for it.

KVM_TDX_INIT_VCPU needs the address of the HOB as input. Invoke it for
each vcpu after HOB list is created.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-26-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Add TDVF memory via KVM_TDX_INIT_MEM_REGION
Isaku Yamahata [Thu, 8 May 2025 14:59:30 +0000 (10:59 -0400)] 
i386/tdx: Add TDVF memory via KVM_TDX_INIT_MEM_REGION

TDVF firmware (CODE and VARS) needs to be copied to TD's private
memory via KVM_TDX_INIT_MEM_REGION, as well as TD HOB and TEMP memory.

If the TDVF section has TDVF_SECTION_ATTRIBUTES_MR_EXTEND set in the
flag, calling KVM_TDX_EXTEND_MEMORY to extend the measurement.

After populating the TDVF memory, the original image located in shared
ramblock can be discarded.

Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-25-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Setup the TD HOB list
Xiaoyao Li [Thu, 8 May 2025 14:59:29 +0000 (10:59 -0400)] 
i386/tdx: Setup the TD HOB list

The TD HOB list is used to pass the information from VMM to TDVF. The TD
HOB must include PHIT HOB and Resource Descriptor HOB. More details can
be found in TDVF specification and PI specification.

Build the TD HOB in TDX's machine_init_done callback.

Co-developed-by: Isaku Yamahata <isaku.yamahata@intel.com>
Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-24-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoheaders: Add definitions from UEFI spec for volumes, resources, etc...
Xiaoyao Li [Thu, 8 May 2025 14:59:28 +0000 (10:59 -0400)] 
headers: Add definitions from UEFI spec for volumes, resources, etc...

Add UEFI definitions for literals, enums, structs, GUIDs, etc... that
will be used by TDX to build the UEFI Hand-Off Block (HOB) that is passed
to the Trusted Domain Virtual Firmware (TDVF).

All values come from the UEFI specification [1], PI spec [2] and TDVF
design guide[3].

[1] UEFI Specification v2.1.0 https://uefi.org/sites/default/files/resources/UEFI_Spec_2_10_Aug29.pdf
[2] UEFI PI spec v1.8 https://uefi.org/sites/default/files/resources/UEFI_PI_Spec_1_8_March3.pdf
[3] https://software.intel.com/content/dam/develop/external/us/en/documents/tdx-virtual-firmware-design-guide-rev-1.pdf

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-23-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Track RAM entries for TDX VM
Xiaoyao Li [Thu, 8 May 2025 14:59:27 +0000 (10:59 -0400)] 
i386/tdx: Track RAM entries for TDX VM

The RAM of TDX VM can be classified into two types:

 - TDX_RAM_UNACCEPTED: default type of TDX memory, which needs to be
   accepted by TDX guest before it can be used and will be all-zeros
   after being accepted.

 - TDX_RAM_ADDED: the RAM that is ADD'ed to TD guest before running, and
   can be used directly. E.g., TD HOB and TEMP MEM that needed by TDVF.

Maintain TdxRamEntries[] which grabs the initial RAM info from e820 table
and mark each RAM range as default type TDX_RAM_UNACCEPTED.

Then turn the range of TD HOB and TEMP MEM to TDX_RAM_ADDED since these
ranges will be ADD'ed before TD runs and no need to be accepted runtime.

The TdxRamEntries[] are later used to setup the memory TD resource HOB
that passes memory info from QEMU to TDVF.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-22-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Track mem_ptr for each firmware entry of TDVF
Xiaoyao Li [Thu, 8 May 2025 14:59:26 +0000 (10:59 -0400)] 
i386/tdx: Track mem_ptr for each firmware entry of TDVF

For each TDVF sections, QEMU needs to copy the content to guest
private memory via KVM API (KVM_TDX_INIT_MEM_REGION).

Introduce a field @mem_ptr for TdxFirmwareEntry to track the memory
pointer of each TDVF sections. So that QEMU can add/copy them to guest
private memory later.

TDVF sections can be classified into two groups:
 - Firmware itself, e.g., TDVF BFV and CFV, that located separately from
   guest RAM. Its memory pointer is the bios pointer.

 - Sections located at guest RAM, e.g., TEMP_MEM and TD_HOB.
   mmap a new memory range for them.

Register a machine_init_done callback to do the stuff.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-21-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Don't initialize pc.rom for TDX VMs
Xiaoyao Li [Thu, 8 May 2025 14:59:25 +0000 (10:59 -0400)] 
i386/tdx: Don't initialize pc.rom for TDX VMs

For TDX, the address below 1MB are entirely general RAM. No need to
initialize pc.rom memory region for TDs.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-20-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Parse TDVF metadata for TDX VM
Xiaoyao Li [Thu, 8 May 2025 14:59:24 +0000 (10:59 -0400)] 
i386/tdx: Parse TDVF metadata for TDX VM

After TDVF is loaded to bios MemoryRegion, it needs parse TDVF metadata.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-19-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdvf: Introduce function to parse TDVF metadata
Isaku Yamahata [Thu, 8 May 2025 14:59:23 +0000 (10:59 -0400)] 
i386/tdvf: Introduce function to parse TDVF metadata

TDX VM needs to boot with its specialized firmware, Trusted Domain
Virtual Firmware (TDVF). QEMU needs to parse TDVF and map it in TD
guest memory prior to running the TDX VM.

A TDVF Metadata in TDVF image describes the structure of firmware.
QEMU refers to it to setup memory for TDVF. Introduce function
tdvf_parse_metadata() to parse the metadata from TDVF image and store
the info of each TDVF section.

TDX metadata is located by a TDX metadata offset block, which is a
GUID-ed structure. The data portion of the GUID structure contains
only an 4-byte field that is the offset of TDX metadata to the end
of firmware file.

Select X86_FW_OVMF when TDX is enable to leverage existing functions
to parse and search OVMF's GUID-ed structures.

Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
Co-developed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-18-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: load TDVF for TD guest
Chao Peng [Thu, 8 May 2025 14:59:22 +0000 (10:59 -0400)] 
i386/tdx: load TDVF for TD guest

TDVF(OVMF) needs to run at private memory for TD guest. TDX cannot
support pflash device since it doesn't support read-only private memory.
Thus load TDVF(OVMF) with -bios option for TDs.

Use memory_region_init_ram_guest_memfd() to allocate the MemoryRegion
for TDVF because it needs to be located at private memory.

Also store the MemoryRegion pointer of TDVF since the shared ramblock of
it can be discared after it gets copied to private ramblock.

Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Co-developed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-17-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Implement user specified tsc frequency
Xiaoyao Li [Thu, 8 May 2025 14:59:21 +0000 (10:59 -0400)] 
i386/tdx: Implement user specified tsc frequency

Reuse "-cpu,tsc-frequency=" to get user wanted tsc frequency and call VM
scope VM_SET_TSC_KHZ to set the tsc frequency of TD before KVM_TDX_INIT_VM.

Besides, sanity check the tsc frequency to be in the legal range and
legal granularity (required by TDX module).

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-16-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Set APIC bus rate to match with what TDX module enforces
Xiaoyao Li [Thu, 8 May 2025 14:59:20 +0000 (10:59 -0400)] 
i386/tdx: Set APIC bus rate to match with what TDX module enforces

TDX advertises core crystal clock with cpuid[0x15] as 25MHz for TD
guests and it's unchangeable from VMM. As a result, TDX guest reads
the APIC timer at the same frequency, 25MHz.

While KVM's default emulated frequency for APIC bus is 1GHz, set the
APIC bus rate to match with TDX explicitly to ensure KVM provide correct
emulated APIC timer for TD guest.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-15-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Support user configurable mrconfigid/mrowner/mrownerconfig
Isaku Yamahata [Thu, 8 May 2025 14:59:19 +0000 (10:59 -0400)] 
i386/tdx: Support user configurable mrconfigid/mrowner/mrownerconfig

Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
can be provided for TDX attestation. Detailed meaning of them can be
found: https://lore.kernel.org/qemu-devel/31d6dbc1-f453-4cef-ab08-4813f4e0ff92@intel.com/

Allow user to specify those values via property mrconfigid, mrowner and
mrownerconfig. They are all in base64 format.

example
-object tdx-guest, \
  mrconfigid=ASNFZ4mrze8BI0VniavN7wEjRWeJq83vASNFZ4mrze8BI0VniavN7wEjRWeJq83v,\
  mrowner=ASNFZ4mrze8BI0VniavN7wEjRWeJq83vASNFZ4mrze8BI0VniavN7wEjRWeJq83v,\
  mrownerconfig=ASNFZ4mrze8BI0VniavN7wEjRWeJq83vASNFZ4mrze8BI0VniavN7wEjRWeJq83v

Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
Co-developed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-14-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Validate TD attributes
Xiaoyao Li [Thu, 8 May 2025 14:59:18 +0000 (10:59 -0400)] 
i386/tdx: Validate TD attributes

Validate TD attributes with tdx_caps that only supported bits are
allowed by KVM.

Besides, sanity check the attribute bits that have not been supported by
QEMU yet. e.g., debug bit, it will be allowed in the future when debug
TD support lands in QEMU.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Link: https://lore.kernel.org/r/20250508150002.689633-13-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Wire CPU features up with attributes of TD guest
Xiaoyao Li [Thu, 8 May 2025 14:59:17 +0000 (10:59 -0400)] 
i386/tdx: Wire CPU features up with attributes of TD guest

For QEMU VMs,
  - PKS is configured via CPUID_7_0_ECX_PKS, e.g., -cpu xxx,+pks  and
  - PMU is configured by x86cpu->enable_pmu, e.g., -cpu xxx,pmu=on

While the bit 30 (PKS) and bit 63 (PERFMON) of TD's attributes are also
used to configure the PKS and PERFMON/PMU of TD, reuse the existing
configuration interfaces of 'cpu' for TD's attributes.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-12-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Make sept_ve_disable set by default
Isaku Yamahata [Thu, 8 May 2025 14:59:16 +0000 (10:59 -0400)] 
i386/tdx: Make sept_ve_disable set by default

For TDX KVM use case, Linux guest is the most major one.  It requires
sept_ve_disable set.  Make it default for the main use case.  For other use
case, it can be enabled/disabled via qemu command line.

Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-11-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Add property sept-ve-disable for tdx-guest object
Xiaoyao Li [Thu, 8 May 2025 14:59:15 +0000 (10:59 -0400)] 
i386/tdx: Add property sept-ve-disable for tdx-guest object

Bit 28 of TD attribute, named SEPT_VE_DISABLE. When set to 1, it disables
EPT violation conversion to #VE on guest TD access of PENDING pages.

Some guest OS (e.g., Linux TD guest) may require this bit as 1.
Otherwise refuse to boot.

Add sept-ve-disable property for tdx-guest object, for user to configure
this bit.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-10-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Initialize TDX before creating TD vcpus
Xiaoyao Li [Thu, 8 May 2025 14:59:14 +0000 (10:59 -0400)] 
i386/tdx: Initialize TDX before creating TD vcpus

Invoke KVM_TDX_INIT_VM in kvm_arch_pre_create_vcpu() that
KVM_TDX_INIT_VM configures global TD configurations, e.g. the canonical
CPUID config, and must be executed prior to creating vCPUs.

Use kvm_x86_arch_cpuid() to setup the CPUID settings for TDX VM.

Note, this doesn't address the fact that QEMU may change the CPUID
configuration when creating vCPUs, i.e. punts on refactoring QEMU to
provide a stable CPUID config prior to kvm_arch_init().

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-9-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agokvm: Introduce kvm_arch_pre_create_vcpu()
Xiaoyao Li [Thu, 8 May 2025 14:59:13 +0000 (10:59 -0400)] 
kvm: Introduce kvm_arch_pre_create_vcpu()

Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent
work prior to create any vcpu. This is for i386 TDX because it needs
call TDX_INIT_VM before creating any vcpu.

The specific implementation for i386 will be added in the future patch.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-8-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Introduce is_tdx_vm() helper and cache tdx_guest object
Xiaoyao Li [Thu, 8 May 2025 14:59:12 +0000 (10:59 -0400)] 
i386/tdx: Introduce is_tdx_vm() helper and cache tdx_guest object

It will need special handling for TDX VMs all around the QEMU.
Introduce is_tdx_vm() helper to query if it's a TDX VM.

Cache tdx_guest object thus no need to cast from ms->cgs every time.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Isaku Yamahata <isaku.yamahata@intel.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-7-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Get tdx_capabilities via KVM_TDX_CAPABILITIES
Xiaoyao Li [Thu, 8 May 2025 14:59:11 +0000 (10:59 -0400)] 
i386/tdx: Get tdx_capabilities via KVM_TDX_CAPABILITIES

KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of
IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capabilities when initializing
TDX context. It will be used to validate user's setting later.

Since there is no interface reporting how many cpuid configs contains in
KVM_TDX_CAPABILITIES, QEMU chooses to try starting with a known number
and abort when it exceeds KVM_MAX_CPUID_ENTRIES.

Besides, introduce the interfaces to invoke TDX "ioctls" at VCPU scope
in preparation.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-6-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Implement tdx_kvm_init() to initialize TDX VM context
Xiaoyao Li [Thu, 8 May 2025 14:59:10 +0000 (10:59 -0400)] 
i386/tdx: Implement tdx_kvm_init() to initialize TDX VM context

Implement TDX specific ConfidentialGuestSupportClass::kvm_init()
callback, tdx_kvm_init().

Mark guest state is proctected for TDX VM.  More TDX specific
initialization will be added later.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-5-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386/tdx: Implement tdx_kvm_type() for TDX
Xiaoyao Li [Thu, 8 May 2025 14:59:09 +0000 (10:59 -0400)] 
i386/tdx: Implement tdx_kvm_type() for TDX

TDX VM requires VM type to be KVM_X86_TDX_VM. Implement tdx_kvm_type()
as X86ConfidentialGuestClass->kvm_type.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-4-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoi386: Introduce tdx-guest object
Xiaoyao Li [Thu, 8 May 2025 14:59:08 +0000 (10:59 -0400)] 
i386: Introduce tdx-guest object

Introduce tdx-guest object which inherits X86_CONFIDENTIAL_GUEST,
and will be used to create TDX VMs (TDs) by

  qemu -machine ...,confidential-guest-support=tdx0 \
       -object tdx-guest,id=tdx0

It has one QAPI member 'attributes' defined, which allows user to set
TD's attributes directly.

Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250508150002.689633-3-xiaoyao.li@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agorocker: do not pollute the namespace
Paolo Bonzini [Wed, 28 May 2025 09:20:13 +0000 (11:20 +0200)] 
rocker: do not pollute the namespace

Do not leave the __le* macros defined, in fact do not use them at all.  Fixes a
build failure on Alpine with the TDX patches:

In file included from ../hw/net/rocker/rocker_of_dpa.c:25:
../hw/net/rocker/rocker_hw.h:14:16: error: conflicting types for 'uint64_t'; have '__u64' {aka 'long long unsigned int'}
   14 | #define __le64 uint64_t
      |                ^~~~~~~~
In file included from /usr/include/stdint.h:20,
                 from ../include/qemu/osdep.h:111,
                 from ../hw/net/rocker/rocker_of_dpa.c:17:
/usr/include/bits/alltypes.h:136:25: note: previous declaration of 'uint64_t' with type 'uint64_t' {aka 'long unsigned int'}
  136 | typedef unsigned _Int64 uint64_t;
      |                         ^~~~~~~~

because the Linux headers include a typedef of __leNN.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoqapi: use imperative style in documentation
Pierrick Bouvier [Thu, 22 May 2025 19:05:40 +0000 (12:05 -0700)] 
qapi: use imperative style in documentation

As requested by Markus:
> We prefer imperative mood "Return" over "Returns".

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-14-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Change several more]

13 months agoqapi: make all generated files common
Pierrick Bouvier [Thu, 22 May 2025 19:05:39 +0000 (12:05 -0700)] 
qapi: make all generated files common

Monolithic files (qapi_nonmodule_outputs) can now be compiled just
once, so we can remove qapi_util_outputs logic.
This removes the need for any specific_ss file.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-13-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
13 months agoqapi: remove qapi_specific_outputs from meson.build
Pierrick Bouvier [Thu, 22 May 2025 19:05:38 +0000 (12:05 -0700)] 
qapi: remove qapi_specific_outputs from meson.build

There is no more QAPI files that need to be compiled per target, so we
can remove this. qapi_specific_outputs is now empty, so we can remove
the associated logic in meson.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-12-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
13 months agoqapi: make s390x specific CPU commands unconditionally available
Daniel P. Berrangé [Thu, 22 May 2025 19:05:37 +0000 (12:05 -0700)] 
qapi: make s390x specific CPU commands unconditionally available

This removes the TARGET_S390X and CONFIG_KVM conditions from the
CPU commands that are conceptually specific to s390x. Top level
stubs are provided to cope with non-s390x targets, or builds
without KVM.

The removal of CONFIG_KVM is justified by the fact there is no
conceptual difference between running 'qemu-system-s390x -accel tcg'
on a build with and without KVM built-in, so apps only using TCG
can't rely on the CONFIG_KVM in the schema.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-11-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
13 months agoqapi: make most CPU commands unconditionally available
Daniel P. Berrangé [Thu, 22 May 2025 19:05:36 +0000 (12:05 -0700)] 
qapi: make most CPU commands unconditionally available

This removes the TARGET_* conditions from all the CPU commands
that are conceptually target independent. Top level stubs are
provided to cope with targets which do not currently implement
all of the commands. Adjust the doc comments accordingly.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-10-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
13 months agoqapi: Make CpuModelExpansionInfo::deprecated-props optional and generic
Philippe Mathieu-Daudé [Thu, 22 May 2025 19:05:35 +0000 (12:05 -0700)] 
qapi: Make CpuModelExpansionInfo::deprecated-props optional and generic

We'd like to have some unified QAPI schema. Having a structure field
conditional to a target being built in is not very practical.

While @deprecated-props is only used by s390x target, it is generic
enough and could be used by other targets (assuming we expand
CpuModelExpansionType enum values).

Let's always include this field, regardless of the target, but make it
optional. This is not a compatibility break only because the field
remains present always on S390x.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-9-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
13 months agoqapi: remove the misc-target.json file
Daniel P. Berrangé [Thu, 22 May 2025 19:05:34 +0000 (12:05 -0700)] 
qapi: remove the misc-target.json file

This file is now empty and can thus be removed.

Observe the pre-existing bug with s390-skeys.c and target/i386/monitor.c
both including qapi-commands-misc-target.h despite not requiring it.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-8-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
13 months agoqapi: make Xen event commands unconditionally available
Daniel P. Berrangé [Thu, 22 May 2025 19:05:33 +0000 (12:05 -0700)] 
qapi: make Xen event commands unconditionally available

This removes the TARGET_I386 condition from the Xen event channel
commands, moving them to the recently introduced misc-i386.json
QAPI file, given they are inherantly i386 specific commands.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Acked-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-7-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
13 months agoqapi: make SGX commands unconditionally available
Daniel P. Berrangé [Thu, 22 May 2025 19:05:32 +0000 (12:05 -0700)] 
qapi: make SGX commands unconditionally available

This removes the TARGET_I386 condition from the SGX confidential
virtualization commands, moving them to the recently introduced
misc-i386.json QAPI file, given they are inherantly i386 specific
commands.

Observe a pre-existing bug that the "SGXEPCSection" struct lacked
a TARGET_I386 condition, despite its only usage being behind a
TARGET_I386 condition.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-6-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
13 months agoqapi: expose query-gic-capability command unconditionally
Daniel P. Berrangé [Thu, 22 May 2025 19:05:31 +0000 (12:05 -0700)] 
qapi: expose query-gic-capability command unconditionally

This removes the TARGET_ARM condition from the query-gic-capability
command. This requires providing a QMP command stub for non-ARM targets.
This in turn requires moving the command out of misc-target.json, since
that will trigger symbol poisoning errors when built from target
independent code.

Following the earlier precedent, this creates a misc-arm.json file to
hold this ARM specific command.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-5-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
13 months agoqapi: make SEV commands unconditionally available
Daniel P. Berrangé [Thu, 22 May 2025 19:05:30 +0000 (12:05 -0700)] 
qapi: make SEV commands unconditionally available

This removes the TARGET_I386 condition from the SEV confidential
virtualization commands, moving them to the recently introduced
misc-i386.json QAPI file, given they are inherantly i386 specific
commands.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-4-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
13 months agoqapi: expand docs for SEV commands
Daniel P. Berrangé [Thu, 22 May 2025 19:05:29 +0000 (12:05 -0700)] 
qapi: expand docs for SEV commands

This gives some more context about the behaviour of the commands in
unsupported guest configuration or platform scenarios.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-3-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Tweak query-sev doc, turn error descriptions into Errors sections,
delate a stray #, normalize whitespace, wrap lines]

13 months agoqapi: expose rtc-reset-reinjection command unconditionally
Daniel P. Berrangé [Thu, 22 May 2025 19:05:28 +0000 (12:05 -0700)] 
qapi: expose rtc-reset-reinjection command unconditionally

This removes the TARGET_I386 condition from the rtc-reset-reinjection
command. This requires providing a QMP command stub for non-i386 target.
This in turn requires moving the command out of misc-target.json, since
that will trigger symbol poisoning errors when built from target
independent code.

Rather than putting the command into misc.json, it is proposed to create
misc-$TARGET.json files to hold commands whose impl is conceptually
only applicable to a single target. This gives an obvious docs hint to
consumers that the command is only useful in relation a specific target,
while misc.json is for commands applicable to 2 or more targets.

The current impl of qmp_rtc_reset_reinject() is a no-op if the i386
RTC is disabled in Kconfig, or if the running machine type lack any
RTC device.

The stub impl for non-i386 targets retains this no-op behaviour.
However, it is now reporting an Error mentioning this command is not
available for current target.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-ID: <20250522190542.588267-2-pierrick.bouvier@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
13 months agoaccel/tcg: Assert TCGCPUOps.pointer_wrap is set
Richard Henderson [Sun, 4 May 2025 18:19:17 +0000 (11:19 -0700)] 
accel/tcg: Assert TCGCPUOps.pointer_wrap is set

All targets now provide the function, so we can
make the call unconditional.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/sparc: Fill in TCGCPUOps.pointer_wrap
Richard Henderson [Sun, 4 May 2025 18:14:01 +0000 (11:14 -0700)] 
target/sparc: Fill in TCGCPUOps.pointer_wrap

Check address masking state for sparc64.

Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/s390x: Fill in TCGCPUOps.pointer_wrap
Richard Henderson [Sun, 4 May 2025 18:04:55 +0000 (11:04 -0700)] 
target/s390x: Fill in TCGCPUOps.pointer_wrap

Use the existing wrap_address function.

Cc: qemu-s390x@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/riscv: Fill in TCGCPUOps.pointer_wrap
Richard Henderson [Sun, 4 May 2025 17:59:39 +0000 (10:59 -0700)] 
target/riscv: Fill in TCGCPUOps.pointer_wrap

Check 32 vs 64-bit and pointer masking state.

Cc: qemu-riscv@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/ppc: Fill in TCGCPUOps.pointer_wrap
Richard Henderson [Sun, 4 May 2025 17:20:02 +0000 (10:20 -0700)] 
target/ppc: Fill in TCGCPUOps.pointer_wrap

Check 32 vs 64-bit state.

Cc: qemu-ppc@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/mips: Fill in TCGCPUOps.pointer_wrap
Richard Henderson [Sun, 4 May 2025 16:59:29 +0000 (09:59 -0700)] 
target/mips: Fill in TCGCPUOps.pointer_wrap

Check 32 vs 64-bit addressing state.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/loongarch: Fill in TCGCPUOps.pointer_wrap
Richard Henderson [Sun, 4 May 2025 16:50:08 +0000 (09:50 -0700)] 
target/loongarch: Fill in TCGCPUOps.pointer_wrap

Check va32 state.

Reviewed-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/i386: Fill in TCGCPUOps.pointer_wrap
Richard Henderson [Sun, 4 May 2025 16:46:28 +0000 (09:46 -0700)] 
target/i386: Fill in TCGCPUOps.pointer_wrap

Check 32 vs 64-bit state.

Cc: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/arm: Fill in TCGCPUOps.pointer_wrap
Richard Henderson [Sun, 4 May 2025 16:27:42 +0000 (09:27 -0700)] 
target/arm: Fill in TCGCPUOps.pointer_wrap

For a-profile, check A32 vs A64 state.
For m-profile, use cpu_pointer_wrap_uint32.

Cc: qemu-arm@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget: Use cpu_pointer_wrap_uint32 for 32-bit targets
Richard Henderson [Sat, 3 May 2025 21:23:41 +0000 (14:23 -0700)] 
target: Use cpu_pointer_wrap_uint32 for 32-bit targets

M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are
all 32-bit targets.  AVR is more complicated, but using
a 32-bit wrap preserves current behaviour.

Cc: Michael Rolnik <mrolnik@gmail.com>
Cc: Laurent Vivier <laurent@vivier.eu>
Cc: Stafford Horne <shorne@gmail.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Tested-by Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore)
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget: Use cpu_pointer_wrap_notreached for strict align targets
Richard Henderson [Sat, 3 May 2025 20:45:26 +0000 (13:45 -0700)] 
target: Use cpu_pointer_wrap_notreached for strict align targets

Alpha, HPPA, and SH4 always use aligned addresses,
and therefore never produce accesses that cross pages.

Cc: Helge Deller <deller@gmx.de>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agoaccel/tcg: Add TCGCPUOps.pointer_wrap
Richard Henderson [Sat, 3 May 2025 20:17:17 +0000 (13:17 -0700)] 
accel/tcg: Add TCGCPUOps.pointer_wrap

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/sh4: Use MO_ALIGN for system UNALIGN()
Richard Henderson [Sat, 3 May 2025 20:40:26 +0000 (13:40 -0700)] 
target/sh4: Use MO_ALIGN for system UNALIGN()

This should have been done before removing TARGET_ALIGNED_ONLY,
as we did for hppa and alpha.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Fixes: 8244189419f9 ("target/sh4: Remove TARGET_ALIGNED_ONLY")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotcg: Drop TCGContext.page_{mask,bits}
Richard Henderson [Thu, 1 May 2025 18:38:03 +0000 (11:38 -0700)] 
tcg: Drop TCGContext.page_{mask,bits}

Use exec/target_page.h instead of independent variables.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotcg: Drop TCGContext.tlb_dyn_max_bits
Richard Henderson [Thu, 1 May 2025 18:16:31 +0000 (11:16 -0700)] 
tcg: Drop TCGContext.tlb_dyn_max_bits

This was an extremely minor optimization for aarch64
and x86_64, to use a 32-bit AND instruction when the
guest softmmu tlb maximum was sufficiently small.
Both hosts can simply use a 64-bit AND insn instead.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/microblaze: Simplify compute_ldst_addr_type{a,b}
Richard Henderson [Wed, 12 Feb 2025 21:56:32 +0000 (13:56 -0800)] 
target/microblaze: Simplify compute_ldst_addr_type{a,b}

Require TCGv_i32 and TCGv be identical, so drop
the extensions.  Return constants when possible
instead of a mov into a temporary.  Return register
inputs unchanged when possible.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/microblaze: Drop DisasContext.r0
Richard Henderson [Wed, 12 Feb 2025 21:54:18 +0000 (13:54 -0800)] 
target/microblaze: Drop DisasContext.r0

Return a constant 0 from reg_for_read, and a new
temporary from reg_for_write.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/microblaze: Use TARGET_LONG_BITS == 32 for system mode
Richard Henderson [Wed, 12 Feb 2025 21:37:39 +0000 (13:37 -0800)] 
target/microblaze: Use TARGET_LONG_BITS == 32 for system mode

Now that the extended address instructions are handled separately
from virtual addresses, we can narrow the emulation to 32-bit.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/microblaze: Fix printf format in mmu_translate
Richard Henderson [Wed, 12 Feb 2025 21:34:52 +0000 (13:34 -0800)] 
target/microblaze: Fix printf format in mmu_translate

Use TARGET_FMT_lx to match the target_ulong type of vaddr.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/microblaze: Use TCGv_i64 for compute_ldst_addr_ea
Richard Henderson [Wed, 12 Feb 2025 21:28:18 +0000 (13:28 -0800)] 
target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea

Use an explicit 64-bit type for extended addresses.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/microblaze: Use uint64_t for CPUMBState.ear
Richard Henderson [Wed, 12 Feb 2025 21:24:08 +0000 (13:24 -0800)] 
target/microblaze: Use uint64_t for CPUMBState.ear

Use an explicit 64-bit type for EAR.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/microblaze: Implement extended address load/store out of line
Richard Henderson [Wed, 12 Feb 2025 21:20:58 +0000 (13:20 -0800)] 
target/microblaze: Implement extended address load/store out of line

Use helpers and address_space_ld/st instead of inline
loads and stores.  This allows us to perform operations
on physical addresses wider than virtual addresses.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/microblaze: Split out mb_transaction_failed_internal
Richard Henderson [Wed, 12 Feb 2025 20:46:17 +0000 (12:46 -0800)] 
target/microblaze: Split out mb_transaction_failed_internal

Use an explicit 64-bit type for the address to store in EAR.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/microblaze: Introduce helper_unaligned_access
Richard Henderson [Sun, 25 May 2025 15:10:03 +0000 (16:10 +0100)] 
target/microblaze: Introduce helper_unaligned_access

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/microblaze: Split out mb_unaligned_access_internal
Richard Henderson [Wed, 12 Feb 2025 20:30:21 +0000 (12:30 -0800)] 
target/microblaze: Split out mb_unaligned_access_internal

Use an explicit 64-bit type for the address to store in EAR.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agolinux-user: implement pgid field of /proc/self/stat
Andreas Schwab [Tue, 20 May 2025 14:07:37 +0000 (16:07 +0200)] 
linux-user: implement pgid field of /proc/self/stat

Signed-off-by: Andreas Schwab <schwab@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <mvmfrgzcr4m.fsf@suse.de>

13 months agosystem/main: comment lock rationale
Pierrick Bouvier [Thu, 15 May 2025 17:46:41 +0000 (10:46 -0700)] 
system/main: comment lock rationale

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250515174641.4000309-1-pierrick.bouvier@linaro.org>

13 months agoaccel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW
Richard Henderson [Sat, 24 May 2025 14:40:12 +0000 (15:40 +0100)] 
accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW

When we moved TLB_MMIO and TLB_DISCARD_WRITE to TLB_SLOW_FLAGS_MASK,
we failed to update atomic_mmu_lookup to properly reconstruct flags.

Fixes: 24b5e0fdb543 ("include/exec: Move TLB_MMIO, TLB_DISCARD_WRITE to slow flags")
Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agodocs/about/removed-features: Move removal notes to tidy up order
Markus Armbruster [Wed, 21 May 2025 06:37:11 +0000 (08:37 +0200)] 
docs/about/removed-features: Move removal notes to tidy up order

The removal notes within a section are mostly in version order.  Move
the few that aren't so they are.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20250521063711.29840-5-armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
13 months agodocs/about/deprecated: Move deprecation notes to tidy up order
Markus Armbruster [Wed, 21 May 2025 06:37:10 +0000 (08:37 +0200)] 
docs/about/deprecated: Move deprecation notes to tidy up order

The deprecation notes within a section are mostly in version order.
Move the few that aren't so they are.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20250521063711.29840-4-armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
13 months agoqapi/migration: Deprecate migrate argument @detach
Markus Armbruster [Wed, 21 May 2025 06:37:09 +0000 (08:37 +0200)] 
qapi/migration: Deprecate migrate argument @detach

Argument @detach has always been ignored.  Start the clock to get rid
of it.

Cc: Peter Xu <peterx@redhat.com>
Cc: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20250521063711.29840-3-armbru@redhat.com>
ACKed-by: Peter Krempa <pkrempa@redhat.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Peter Xu <peterx@redhat.com>
13 months agodocs/about: Belatedly document tightening of QMP device_add checking
Markus Armbruster [Wed, 21 May 2025 06:37:08 +0000 (08:37 +0200)] 
docs/about: Belatedly document tightening of QMP device_add checking

Commit 4d8b0f0a9536 (v6.2.0) deprecated incorrectly typed device_add
arguments.  Commit be93fd53723c (qdev-monitor: avoid QemuOpts in QMP
device_add) fixed them for v9.2.0, but neglected to update
documentation.  Do that now.

Cc: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20250521063711.29840-2-armbru@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
[Commit message typo corrected]

13 months agotarget/sparc: don't set FSR_NVA when comparing unordered floats
Clément Chigot [Fri, 25 Apr 2025 09:35:13 +0000 (11:35 +0200)] 
target/sparc: don't set FSR_NVA when comparing unordered floats

FSR_NVA should be set when one of the operands is a signaling NaN or
when using FCMPEx instructions. But those cases are already handled
within check_ieee_exception or floatxx_compare functions.
Otherwise, it should be left untouched.

FTR, this was detected by inf-compare-[5678] tests within gcc
testsuites.

Signed-off-by: Clément Chigot <chigot@adacore.com>
Message-Id: <20250425093513.863289-1-chigot@adacore.com>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
13 months agotarget/i386/emulate: more lflags cleanups
Paolo Bonzini [Tue, 20 May 2025 12:53:29 +0000 (14:53 +0200)] 
target/i386/emulate: more lflags cleanups

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agorust: hpet: rename hpet module to "device"
Paolo Bonzini [Tue, 13 May 2025 10:18:12 +0000 (12:18 +0200)] 
rust: hpet: rename hpet module to "device"

Follow a similar convention as pl011.

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agorust: Fix the typos in doc
Zhao Liu [Tue, 20 May 2025 15:27:50 +0000 (23:27 +0800)] 
rust: Fix the typos in doc

These typos are found by "cargo spellcheck". Though it outputs a lot of
noise and false positives, there still are some real typos.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250520152750.2542612-6-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agorust: Fix Zhao's email address
Zhao Liu [Tue, 20 May 2025 15:27:49 +0000 (23:27 +0800)] 
rust: Fix Zhao's email address

No one could find Zhao Liu via zhai1.liu@intel.com.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250520152750.2542612-5-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agohw/timer/hpet: Reorganize register decoding
Zhao Liu [Tue, 20 May 2025 15:27:46 +0000 (23:27 +0800)] 
hw/timer/hpet: Reorganize register decoding

For Rust HPET, since the commit 519088b7cf6d ("rust: hpet: decode HPET
registers into enums"), it decodes register address by checking if the
register belongs to global register space. And for C HPET, it checks
timer register space first.

While both approaches are fine, it's best to be as consistent as
possible.

Synchronize changes from the rust side to C side.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250520152750.2542612-2-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agomeson: merge hw_common_arch in target_common_system_arch
Pierrick Bouvier [Wed, 21 May 2025 22:34:14 +0000 (15:34 -0700)] 
meson: merge hw_common_arch in target_common_system_arch

No need to keep two different libraries, as both are compiled with exact
same flags. As well, rename target common libraries to common_{arch} and
system_{arch}, to follow what exists for common and system libraries.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20250521223414.248276-8-pierrick.bouvier@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agomeson: remove lib{system, user}_ss aliases
Pierrick Bouvier [Wed, 21 May 2025 22:34:13 +0000 (15:34 -0700)] 
meson: remove lib{system, user}_ss aliases

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20250521223414.248276-7-pierrick.bouvier@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agomeson: merge lib{system, user}_ss with {system, user}_ss
Pierrick Bouvier [Wed, 21 May 2025 22:34:12 +0000 (15:34 -0700)] 
meson: merge lib{system, user}_ss with {system, user}_ss

Now that target configuration can be applied to lib{system, user}_ss,
there is no reason to keep that separate from the existing {system,
user}_ss.
The only difference is that we'll now compile those files with
-DCOMPILING_SYSTEM_VS_USER, which removes poison for
CONFIG_USER_ONLY and CONFIG_SOFTMMU, without any other side effect.

We extract existing system/user code common common libraries to
lib{system, user}.

To not break existing meson files, we alias libsystem_ss to system_ss
and libuser_ss to user_ss, so we can do the cleanup in next commit.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20250521223414.248276-6-pierrick.bouvier@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agomeson: apply target config for picking files from lib{system, user}
Pierrick Bouvier [Wed, 21 May 2025 22:34:11 +0000 (15:34 -0700)] 
meson: apply target config for picking files from lib{system, user}

semihosting code needs to be included only if CONFIG_SEMIHOSTING is set.
However, this is a target configuration, so we need to apply it to the
lib{system, user}_ss.

As well, this prepares merging lib{system, user}_ss with
{system, user}_ss.

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20250521223414.248276-5-pierrick.bouvier@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agotarget/arm: remove explicit dependencies listed
Pierrick Bouvier [Wed, 21 May 2025 22:34:10 +0000 (15:34 -0700)] 
target/arm: remove explicit dependencies listed

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20250521223414.248276-4-pierrick.bouvier@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agohw/arm: remove explicit dependencies listed
Pierrick Bouvier [Wed, 21 May 2025 22:34:09 +0000 (15:34 -0700)] 
hw/arm: remove explicit dependencies listed

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20250521223414.248276-3-pierrick.bouvier@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agomeson: build target libraries with common dependencies
Pierrick Bouvier [Wed, 21 May 2025 22:34:08 +0000 (15:34 -0700)] 
meson: build target libraries with common dependencies

As mentioned in [1], dependencies
were missing when compiling per target libraries, thus breaking
compilation on certain host systems.

We now explicitly add common dependencies to those libraries, so it
solves the problem.

[1] https://lore.kernel.org/qemu-devel/20250513115637.184940-1-thuth@redhat.com/

Tested-by: Thomas Huth <thuth@redhat.com>
Fixes: 6f4e8a92bbd ("hw/arm: make most of the compilation units common")
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20250521223414.248276-2-pierrick.bouvier@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
13 months agoMerge tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu into staging
Stefan Hajnoczi [Mon, 26 May 2025 14:16:59 +0000 (10:16 -0400)] 
Merge tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu into staging

aspeed queue:

* Fixed memory leaks in qtest tests
* Reworked and fixed HACE (crypto) model for AST2700 SoC
* Extended HACE qtest tests
* Fixed RAM size detection on BE hosts
* Added network backends to ast2700fc machine
* Mapped main SoC memory into system memory on multi SoC machines

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# gpg: Signature made Mon 26 May 2025 04:04:38 EDT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg:                 aka "Cédric Le Goater <clg@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu: (39 commits)
  docs: Remove ast2700fc from Aspeed family boards
  hw/arm/fby35: Map BMC memory into system memory
  hw/arm/aspeed_ast27x0-fc: Map ca35 memory into system memory
  hw/arm/aspeed_ast27x0: Fix unimplemented region overlap with vbootrom
  hw/arm/aspeed_ast2700-fc: Reduce ca35 ram size to align with ast2700a1
  hw/arm/aspeed_ast2700-fc: Add network support
  hw/arm/aspeed_ast27x0: Fix RAM size detection failure on BE hosts
  hw/intc/aspeed Fix coding style
  hw/intc/aspeed: Set impl.min_access_size to 4
  test/qtest/hace: Add tests for AST2700
  test/qtest/hace: Support to validate 64-bit hmac key buffer addresses
  test/qtest/hace: Support to test upper 32 bits of digest and source addresses
  test/qtest/hace: Support 64-bit source and digest addresses for AST2700
  test/qtest/hace: Update source data and digest data type to 64-bit
  test/qtest/hace: Add tests for AST1030
  test/qtest/hace: Add SHA-384 tests for AST2600
  test/qtest/hace: Add SHA-384 test cases for ASPEED HACE model
  test/qtest/hace: Adjust test address range for AST1030 due to SRAM limitations
  test/qtest/hace: Specify explicit array sizes for test vectors and hash results
  test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
13 months agodocs: Remove ast2700fc from Aspeed family boards
Steven Lee [Fri, 23 May 2025 09:31:43 +0000 (17:31 +0800)] 
docs: Remove ast2700fc from Aspeed family boards

The ast2700fc machine is now covered in the dedicated ast2700-evb
section. Listing it in the general Aspeed board family list is
redundant.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250523093144.991408-7-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
13 months agohw/arm/fby35: Map BMC memory into system memory
Steven Lee [Fri, 23 May 2025 09:31:42 +0000 (17:31 +0800)] 
hw/arm/fby35: Map BMC memory into system memory

Add the BMC memory region as a subregion of system_memory so that
modules relying on system memory can operate correctly.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250523093144.991408-6-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
13 months agohw/arm/aspeed_ast27x0-fc: Map ca35 memory into system memory
Steven Lee [Fri, 23 May 2025 09:31:41 +0000 (17:31 +0800)] 
hw/arm/aspeed_ast27x0-fc: Map ca35 memory into system memory

Map the CA35 memory region as a subregion of system_memory to ensure
a valid FlatView. This prevents failures in APIs that rely on the
global memory view, such as rom_check_and_register_reset().

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250523093144.991408-5-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
13 months agohw/arm/aspeed_ast27x0: Fix unimplemented region overlap with vbootrom
Steven Lee [Fri, 23 May 2025 09:31:40 +0000 (17:31 +0800)] 
hw/arm/aspeed_ast27x0: Fix unimplemented region overlap with vbootrom

The unimplemented memory region overlaps with the VBootROM address
range, causing incorrect memory layout.

This patch adjusts the size and start address of the unimplemented
region to avoid collision. The IO memory region (ASPEED_DEV_IOMEM) is
now moved to 0x20000 to reserve space for VBootROM at 0x0.

Although the memory range 0x20000 - 0x10000000 is undefined in the
datasheet and should not be required, further testing shows OP-TEE
or U-Boot may access 0x400000 during early boot.
Removing the unimplemented region causes firmware hangs.

To prevent unexpected accesses, retain the region as a safeguard.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250523093144.991408-4-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
13 months agohw/arm/aspeed_ast2700-fc: Reduce ca35 ram size to align with ast2700a1
Steven Lee [Fri, 23 May 2025 09:31:39 +0000 (17:31 +0800)] 
hw/arm/aspeed_ast2700-fc: Reduce ca35 ram size to align with ast2700a1

Reduce ca35 ram size from 2GiB to 1GiB to align with ast2700a1-evb,
where the ram-container is defined as 1GiB in its class.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250523093144.991408-3-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
13 months agohw/arm/aspeed_ast2700-fc: Add network support
Steven Lee [Fri, 23 May 2025 09:31:38 +0000 (17:31 +0800)] 
hw/arm/aspeed_ast2700-fc: Add network support

This patch adds network support to the ast2700fc machine by initializing
the NIC device in the ca35.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250523093144.991408-2-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>