For android vendor boot image version 4 bootconfig is mandatory.[1]
In the android_image_get_ramdisk function, after copying both vendor and
boot ramdisks, we extract all androidboot.* entries from the kernel
command line. These entries are added to the bootconfig section.
We then update the sizes of the ramdisk and bootconfig.
Finally, all androidboot.* entries are removed from the kernel command
line.
Use map_to_sysmem() to convert header pointers to physical addresses
in parse_hdr functions, and add proper map_sysmem()/unmap_sysmem()
calls in android_image_get_data() for sandbox compatibility.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Guillaume La Roque (TI.com) <glaroque@baylibre.com> Link: https://lore.kernel.org/r/20260112-bootconfig-v5-2-79b242159ac7@baylibre.com Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Markus Niebel [Tue, 2 Dec 2025 08:13:43 +0000 (09:13 +0100)]
net: phy: micrel_ksz90x1: support forced GIGE master for KSZ9031
The micrel KSZ9031 phy has a optional clock pin (CLK125_NDO) which can be
used as reference clock for the MAC unit. The clock signal must meet the
RGMII requirements to ensure the correct data transmission between the
MAC and the PHY. The KSZ9031 phy does not fulfill the duty cycle
requirement if the phy is configured as slave. For a complete
describtion look at the errata sheets: DS80000691D or DS80000692D.
The errata sheet recommends to force the phy into master mode whenever
there is a 1000Base-T link-up as work around. Only set the
"micrel,force-master" property if you use the phy reference clock provided
by CLK125_NDO pin as MAC reference clock in your application.
Attention: this workaround is only usable if the link partner can
be configured to slave mode for 1000Base-T.
This follows linux implementation in commit e1b505a60366 ("net: phy: micrel: add 125MHz reference clock workaround")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
Markus Niebel [Tue, 2 Dec 2025 08:13:42 +0000 (09:13 +0100)]
net: phy: micrel_ksz90x1: disable asymmetric pause for KSZ9031 and KSZ9021
Disable the support due to chip errata and call genphy_config_aneg
instead of genphy_config. For a complete describtion look at the
KSZ9031 errata sheets: DS80000691D or DS80000692D.
Micrel KSZ9021 has no errata, but has the same issue with Asymmetric Pause.
This patch apply the same workaround as the one for KSZ9031.
This follows linux implementation in commits 3aed3e2a143c ("net: phy: micrel: add Asym Pause workaround") 407d8098cb1a ("net: phy: micrel: add Asym Pause workaround for KSZ9021")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
Replace PHY interface mode bitmap handling with comparison test to match
U-Boot PHY subsystem behavior. U-Boot currently implements only single PHY
interface mode for each PHY. Linux currently uses bitmap of PHY interface
modes for each PHY.
The reason why in Linux uses bitmap of supported interface modes is so
that Linux can select the best serdes mode switching behavior for the PHY.
For example if the host only supports 10gbase-r serdes mode, then the PHY
must always talk to the host in 10gbase-r mode, even if the RJ-45 copper
speed was autonegotiated to lower speed (i.e. 1Gbps).
If the host supports both 10gbase-r and sgmii serdes modes, we want the
PHY to switch to sgmii if the RJ-45 speed is 1000/100/10, and to switch
to 10gbase-r if the RJ-45 speed is 10000.
U-Boot does not implement this functionality yet, therefore remove modes
which cannot be currently supported and switch mv_test_bit() to plain
mode comparison.
Fixes: b6fcab0728cb ("net: phy: marvell10g: Adapt Marvell 10G PHY driver from Linux") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tom Rini [Thu, 25 Dec 2025 15:37:21 +0000 (09:37 -0600)]
net: tftpput: Rework to exclude code from xPL phases
Given how the support for CONFIG_CMD_TFTPPUT is woven through the
support for the tftp protocol we currently end up including "put"
support in xPL phases, if enabled. This in turn can lead to size
overflow on those platforms as xPL tends to be constrained. To resolve
this, use "CMD_TFTPPUT" in the code to check for both CONFIG_CMD_TFTPPUT
being true and not being in an xPL build phase.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jerome Forissier <jerome@forissier.org>
Andrew Goodbody [Fri, 12 Dec 2025 11:32:25 +0000 (11:32 +0000)]
net: Move some variables to net-common files
Make some variables available to be used by either the legacy network
code or lwIP by moving them into the net-common files. This also allowed
removing a small number of duplicated variables from the lwIP code.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Andrew Goodbody [Fri, 12 Dec 2025 11:32:24 +0000 (11:32 +0000)]
net: move net_state to net-common
Move the net_state variable into common code so that it can be used by
either the legacy network code or lwIP. This is needed for porting
across the NFS support code for use with lwIP.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Sean Anderson [Tue, 6 Jan 2026 22:22:11 +0000 (17:22 -0500)]
dfu: Report error codes
A lot of things can go wrong while parsing dfu_alt_info. Make sure to
pass the real error codes all the way up instead of replacing them with
an unhelpful -1.
clk: qcom: sa8775p: Fix USB clock configuration and add resets
Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.
clk: qcom: sa8775p: Add QUP serial engine clock support
Add clock gate definitions and entries for QUP (Qualcomm Universal
Peripheral) serial engine clocks across all four wrappers on SA8775P.
This enables proper clock management for I2C, SPI, and UART
peripherals connected to the QUP blocks.
This resolves the "unknown clock ID 133" error for UART10 and
provides complete QUP clock infrastructure for the platform.
configs: Add google-pixel fragment config for Pixel 3, 3 XL, 5
Introduce a fragment config for the Pixel 3, Pixel 3 XL, Pixel 5.
On these devices, U-Boot is chainloaded via fastboot. However, due to
additional requirements added by Google, the image header must have
a specific value for the text offset.
This is solved by setting CONFIG_TEXT_BASE to 0x80080000 in U-Boot.
Currently we don't properly map between the regulator mode ID enum and
the appropriate register values in the mode map, as a result we always
unintentionally vote for retention mode if we actually attempt to set
it. In the set_mode path we did find the appropriate entry in the mode
map but we wrote the id instead of the register values. Clean this up
and properly map id -> mode and vice versa.
Casey Connolly [Thu, 8 Jan 2026 20:28:47 +0000 (21:28 +0100)]
power: regulator: qcom-rpmh: read votes from rpmh
Make use of the new RPMh read support to fetch regulator values that may
have been voted on by a previous bootloader stage. This allows commands
like "regulator status" to report the actual votes programmed into
hardware (though not necessarily the actual states of the regulators
once the votes have been aggregated).
Casey Connolly [Thu, 8 Jan 2026 20:28:45 +0000 (21:28 +0100)]
soc/qcom: rpmh: correctly wait for TCS flush
Several bugs were discovered in the rpmh-rsc driver which collectively
meant we were never actually waiting for the TCS to flush, these were
likely missed because U-Boot runs single threaded and the RPMh had
typically processed the single command we sent by the time we went
to send the next one. However a future patch will implement rpmh read
support which requires us to properly wait for the RPMh command response
so we can return the value.
Fix these issues so we correctly ensure the TCS is done before
returning.
Neil Armstrong [Thu, 8 Jan 2026 20:28:43 +0000 (21:28 +0100)]
soc: qcom: rpmh-rsc: reclaim the TCS to avoid spurious irq in Linux
If we don't reclaim and clear the IRQ bits, we might get a spurious
interrupt from this TCS in Linux:
WARNING: CPU: 0 PID: 0 at drivers/soc/qcom/rpmh-rsc.c:451 tcs_tx_done+0x98/0x270
...
Call trace:
tcs_tx_done+0x98/0x270 (P)
__handle_irq_event_percpu+0x60/0x220
handle_irq_event+0x54/0xc0
handle_fasteoi_irq+0xa8/0x1c0
handle_irq_desc+0x3c/0x68
generic_handle_domain_irq+0x24/0x40
gic_handle_irq+0x5c/0xd0
...
Casey Connolly [Thu, 8 Jan 2026 19:52:55 +0000 (20:52 +0100)]
i2c: geni: bail when clocks can't be enabled
Failing to enable clocks will lead to bus hangs and the board crashing
in some cases, let's actually deal with this error and fail probe rather than hoping the clocks are already enabled.
configs: Fix fastboot buffer address for QCS615 and QCM6490 boards
The default value of CONFIG_FASTBOOT_BUF_ADDR is 0, which causes
NULL pointer dereference during fastboot commands when users dont
provide "-l" option in fastboot usb command.
Set it to safe and sufficiently large region in RAM
of the QCS615 and QCM6490 boards, to prevent crashes.
Aswin Murugan [Wed, 7 Jan 2026 15:35:04 +0000 (21:05 +0530)]
spmi: msm: refine handling of multiple APID mappings
PMIC Arbiter may expose multiple owned and non-owned APIDs per SID/PID.
- Keep current mapping if it is OWNED and a NON-OWNED appears.
- Always update when a NEW OWNED APID appears (make writable).
- If current is NON-OWNED and a new NON-OWNED appears, update to it
(remain read-only).
This avoids write-access violations when not using the newly discovered
owned channels.
Casey Connolly [Wed, 14 Jan 2026 13:57:32 +0000 (14:57 +0100)]
mach-snapdragon: of_fixup: support new flat dwc3 node
Qualcomm DTs are being updated to use a new format where the dwc3 glue
node and controller are combined into a single DT node. Update the fixup
code to handle this case.
Sumit Garg [Wed, 10 Dec 2025 15:54:54 +0000 (16:54 +0100)]
mmc: msm_sdhci: Add DLL control hook to disable DLL below 100 MHz
Introduce an SDHCI ops hook (config_dll) for MSM SDHCI and implement a
minimal DLL control routine that ensures the core DLL is disabled when
the bus clock is at or below 100 MHz. This approach mirrors the Linux
MSM SDHCI driver.
Loic Poulain [Wed, 10 Dec 2025 15:54:53 +0000 (16:54 +0100)]
clk/qcom: qcm2290: Add SDCC1 apps clock frequency table
Add support for configuring the SDCC1 apps clock on QCM2290 by introducing
a frequency table and enabling dynamic rate setting. Previously, the clock
was assumed to be fixed at 384 MHz by firmware, which limited flexibility
and correctness when selecting optimal rates for SD/MMC operations.
Loic Poulain [Wed, 10 Dec 2025 15:54:52 +0000 (16:54 +0100)]
mmc: msm_sdhci: Fix incorrect divider calculation for SDCLK
When 'max-clk' is not specified, the SDHCI core retrieves the base clock
from the SDHCI_CAPABILITIES register (bits [15:8]). However, this field
is unreliable on MSM SDHCI controllers, as noted by the Linux driver
using the SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN flag. In addition, the field
is only 8 bits wide and cannot represent base clocks above 255 MHz.
On platforms like Agatti/QCM2290, the firmware sets the SDHCI clock to
384 MHz, but the capabilities register reports 200 MHz. As a result,
the core calculates a divider of 4, producing a 96 MHz SDCLK instead of
the intended ~52 MHz. This overclocking can cause sporadic CRC errors
with certain eMMC.
To fix this, use the actual clock rate reported by the SDHCI core clock
instead of relying on the capabilities register for divider calculation.
Biswapriyo Nath [Sun, 7 Dec 2025 18:49:19 +0000 (18:49 +0000)]
phy: Add MSM8996 support to Qualcomm QUSB2 phy
This change is imported from Linux driver and tested with SM6125 SoC.
Note, the msm8996_phy_cfg struct is same as sdm660_phy_cfg but
qusb2_phy_cfg::se_clk_scheme_default differs only.
configs: qcom_qcs615: Correct debug UART clock frequency
Adjust the debug UART clock frequency from 14745600 Hz to 7372800 Hz
for the QCS615 platform. This correction ensures proper UART
communication timing and resolves baud rate miscalculations
that affects early boot console output.
Tom Rini [Wed, 19 Nov 2025 14:55:23 +0000 (08:55 -0600)]
dragonboard820c: Stop disabling device tree relocation
Remove setting of fdt_high to ~0, which disables device tree relocation,
from the default environment. Doing so prevents U-Boot from correcting
problems such as having an unaligned device tree and leads to various
failure modes in the OS.
Aswin Murugan [Wed, 12 Nov 2025 16:58:51 +0000 (22:28 +0530)]
smem: msm: Fix memory-region lookup, direct <reg> mapping and update SMEM host count
The SMEM driver was failing to resolve memory regions on some boards
because `dev_of_offset()` + `fdtdec_lookup_phandle()` did not yield a
valid DT node. Modernize the code to use driver-model/ofnode accessors
and make the probe robust for both DT styles (direct `reg` vs
`memory-region` phandle).
- qcom_smem_map_memory():
* Drop fdtdec path; use dev_read_phandle_with_args() +
ofnode_read_resource().
* Use dev_read_phandle_with_args() +
fnode_read_resource().
- qcom_smem_probe():
* Try dev_read_addr_size() first (map via <reg>), else fall back to
qcom_smem_map_memory() with "memory-region".
* Check "qcom,rpm-msg-ram" presence to add second region.
- Additionally, SMEM_HOST_COUNT is increased to support newer SMEM
versions that include more remote processors. This avoids failures
during processor ID checks.
Enable PINCTRL_QCOM_GENERIC config
The pinctrl drivers are now automatically enabled via Kconfig
defaults based on PINCTRL_QCOM_GENERIC, so explicit selection in the
defconfig is no longer needed.
Aswin Murugan [Wed, 7 Jan 2026 15:47:44 +0000 (21:17 +0530)]
pinctrl: qcom: add PINCTRL_QCOM_GENERIC to enable all drivers by default
Introduce a new Kconfig option PINCTRL_QCOM_GENERIC that, when selected,
enables all Qualcomm pinctrl drivers by default. This simplifies defconfigs
for platforms supporting multiple SoCs and avoids manual driver selection.
Individual drivers can still be disabled if required.
Aswin Murugan [Wed, 12 Nov 2025 16:42:04 +0000 (22:12 +0530)]
regulator: qcom-rpmh-regulator: add support for PM8150 PM8350 PM7325
Add the PM8150, PM8350, and PM7325 regulator data found on Qualcomm
platforms. These regulator tables are imported from the Linux driver
to enable support for these PMICs in U-Boot.
mach-snapdragon: capsule_update: Fix eMMC detection for non-UFS devices
Currently (since 2026.01-rc) on all SDM630/660 based devices this is
printed, after observing long boot delay (several seconds) before
executing preboot commands:
QCOM-FMP: Failed to find boot partition
find_target_partition() function incorrectly assumes that eMMC is always
at number 0. In general you can't rely on device numbering to determine if
particular block device is eMMC or SD-card, because it depends on how
aliases are defined in device tree "chosen" node. Some SoCs have MMC
numbers starting at 1, not 0; so mmc1 is eMMC, mmc2 is SD-card.
Make eMMC detection reliable by using IS_SD() macro from mmc.h header.
Using this method target boot partition can be found successfully.
With debug prints enabled, this is printed:
configs: Rename qcs9100_defconfig to qcom_qcs9100_defconfig
To align with the naming convention used for Qualcomm platforms in
U-Boot, renamed the defconfig file from qcs9100_defconfig to
qcom_qcs9100_defconfig.
usb: dwc3: qcom: Add delays in UTMI clock selection for Qscratch
Added delays before and after setting the PIPE_UTMI_CLK_SEL and
PIPE3_PHYSTATUS_SW bits in the Qscratch GENERAL_CFG register
during UTMI clock selection for DWC3 on Qualcomm platforms.
These delays help ensure proper timing and stability of the UTMI
clock switching sequence, potentially avoiding race conditions or
unstable PHY behavior during initialization.
Tested on platforms using Qscratch-based DWC3 PHY configuration.
This change is taken from this Linux kernel implementation:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/usb/dwc3/dwc3-qcom.c?id=a4333c3a6ba9ca9cff50a3c1d1bf193dc5489e1c
Gopinath Sekar [Wed, 25 Jun 2025 09:46:07 +0000 (15:16 +0530)]
watchdog: qcom: Add max timeout check to prevent overflow
Added a check to ensure the requested timeout does not exceed the
hardware's maximum supported value. This prevents register overflow
and ensures watchdog reliability.
So, added a check in qcom_wdt_start() to ensure the requested timeout
does not exceed the hardware-supported maximum value. If the requested
value exceeds the maximum value, then the timeout is clamped
at maximum value.
The timeout is first converted to watchdog ticks and then compared
against QCOM_WDT_MAX_TIMEOUT. This helps prevent misconfiguration
and potential watchdog misbehavior due to overflow.
QCOM_WDT_MAX_TIMEOUT is set to 0xFFFFF, as Qualcomm SoCs typically
use 20 bits to store bark/bite timeout values.
This work builds upon the previous submission:
https://lore.kernel.org/u-boot/20250527124926.128413-1-balaji.selvanathan@oss.qualcomm.com/
Tom Rini [Tue, 13 Jan 2026 20:18:05 +0000 (14:18 -0600)]
Revert "doc: board: starfive: update jh7110 common description"
This patch is not as E Shattow authored it, but contains non-trivial
changes from Heinrich Schuchardt as well. The original author has
requested that this commit be reverted until the changes can be
committed showing which parts were authored by E Shattow and which by
Heinrich Schuchardt.
Marek Vasut [Sat, 3 Jan 2026 00:17:31 +0000 (01:17 +0100)]
misc: Add fixed-layout support
The "fixed-layout" nvmem controller subnode used to be optional wrapper
around nvmem controller cells subnodes. The "fixed-layout" node is now
mandatory in most cases, but in order to support both recent and legacy
DTs, both variants have to be supported.
Implement support for the "fixed-layout" node in the most trivial manner,
check whether the nvmem cell supernode is compatible with "fixed-layout"
and if it is, proceed one level above it to find the nvmem controller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
J. Neuschäfer [Thu, 1 Jan 2026 16:41:55 +0000 (17:41 +0100)]
powerpc: mpc83xx: Check the size of peripheral structs
Peripheral registers on MPC83xx-series chips are declared in
immap_83xx.h as a set of structs that ultimately fill the entire MMIO
space of 1 MiB. This patch introduces a compile-time check of the size
of each peripheral struct. The purpose of these checks is two-fold:
1. To quickly tell readers of the code the total size of each struct
2. To verify that the size does not change when a struct is edited
If the size of a peripheral struct were to change by a few bytes due
to an editing error, the result would be mayhem for all following
peripherals, because all offsets would shift by the amount of the error.
Tom Rini [Tue, 13 Jan 2026 01:32:11 +0000 (19:32 -0600)]
gardena-smart-gateway-mt7688: Disable CMD_LICENSE
This platform is unfortunately frequently very close to the binary
size limit. Currently it is so close that generic bug fixes can trigger
build failure. Remove the license command from the image as that frees
up nearly 7KiB of space.
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Stefan Roese <stefan.roese@mailbox.org> Signed-off-by: Tom Rini <trini@konsulko.com>
Beleswar Padhi [Mon, 29 Dec 2025 05:11:13 +0000 (10:41 +0530)]
configs: am57xx_hs_evm_defconfig: Reserve EMIF memory used by PPA
The AM571x SoC has 1 GB DDR space. As part of normal re-location process
U-Boot copies itself to the top of DDR bank. However, on HS devices, the
top 37 MB is used by PPA and is firewalled. This results in an exception
and the boot fails. Set CONFIG_SYS_MEM_TOP_HIDE to reserve the top 38 MB
memory (aligned to 2MB as per page size for ARM32) to fix the boot.
Note: This limitation does not exist for other AM57x devices, but this
config is applied in the common defconfig since adding a separate
defconfig only for AM571x is not justified. Losing 38MB of memory at the
bootloader stage on other devices is acceptable.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com> Reviewed-by: Andrew Davis <afd@ti.com>
David Lechner [Mon, 5 Jan 2026 16:49:15 +0000 (10:49 -0600)]
pylibfdt: add requirements.txt for setuptools
Add a requirements.txt file to the pylibfdt script directory to specify
setuptools as a dependency. This follows the pattern of each tool in
U-Boot having its own requirements.txt file. The version is set to
78.1.1 to avoid conflict with the same in tools/patman/requirements.txt.
Reviewed-by: Simon Glass <simon.glass@canonical.com> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # sandbox Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Mon, 5 Jan 2026 16:49:14 +0000 (10:49 -0600)]
doc: pytest: mention additional requirements for venv
Add a paragraph explaining that in addition to the requirements.txt
for test/py/test.py itself, users may need to install additional python
packages depending on the U-Boot configuration being built.
Reviewed-by: Simon Glass <simon.glass@canonical.com> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # sandbox Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Mon, 5 Jan 2026 16:49:13 +0000 (10:49 -0600)]
test.py: check ubconfig exists before using it
Set ubconfig to None and add a check in the show_timings() function of
test/py/test.py to ensure that the global ubconfig variable was actually
initialized before access attributes.
If tests fail early, e.g. because --build failed, ubconfig may not have
been initialized yet and results in an exception in an atexit handler.
Adding this check avoids unnecessary noise in the output.
Exception ignored in atexit callback: <function cleanup at 0x7de475ea6b60>
Traceback (most recent call last):
File "u-boot/test/py/conftest.py", line 669, in cleanup
show_timings()
File "u-boot/test/py/conftest.py", line 616, in show_timings
if ubconfig.timing:
^^^^^^^^
NameError: name 'ubconfig' is not defined
Tom Rini [Mon, 12 Jan 2026 19:41:54 +0000 (13:41 -0600)]
Merge patch series "pinctl: mediatek: add mt8365 support"
David Lechner <dlechner@baylibre.com> says:
MT8365 has different pinctrl register layout compared to other SoCs in
the family, so needs its own driver.
This is also the first SoC in this family supported in U-Boot using an
upstream devicetree that has the mediatek,pctl-regmap property, so we
need to add support for that to the common mediatek pinctrl code first.
David Lechner [Tue, 6 Jan 2026 22:05:19 +0000 (16:05 -0600)]
pinctrl: mediatek: support mediatek,pctl-regmap property
Add support for the mediatek,pctl-regmap devicetree property to the
common MediaTek pinctrl driver.
In upstream devicetrees from Linux, the pinctrl nodes may be on the
interrupt controller register address space rather than the pinctrl
register address space. In this case, there is a syscon node linking to
the actual pinctrl registers. This uses a common property name of
mediatek,pctl-regmap for the phandle to the syscon node.
The logic here is that if this property is present, we look up the
syscon node and use it's address as the base address of the pinctrl
registers and ignore the pinctrl node's own reg property. (Support
for interrupts could be added later if needed.)
There is also at least one SoC in Linux that has two syscon phandles
in this property. This implementation support parsing this, but doesn't
do anything with the second syscon yet (the 2nd syscon is for interrupts
which we are saving for later).
Signed-off-by: David Lechner <dlechner@baylibre.com>
Tom Rini [Mon, 12 Jan 2026 19:24:38 +0000 (13:24 -0600)]
Merge patch series "clk: mediatek: mt8365: fix clocks"
David Lechner <dlechner@baylibre.com> says:
There were a number of bugs in the clock definitions for the mt8365
clock drivers. This series aims to fix the obvious issues.
This builds on [1] that implements the clk dump command to inspect the
clock trees at runtime. Using that revealed quite a few mistakes in
the clock definitions.
Additionally, the topckgen-cg hack is removed for mt8365 since it would
require an extra devicetree node using the same address space as the
topckgen node. This would not be accepted upstream in Linux, so we
shouldn't do it in U-Boot either. mt85{12,16,18} also have this hack.
I didn't attempt to remove it from those platforms since I don't have
hardware to test on.
Patches have been runtime tested on mt8365_evk hardware and compile-
tested on other platforms using:
./tools/buildman/buildman --boards=mt7986a_bpir3_sd,mt7620_rfb,mt7986_rfb,mt7987_emmc_rfb,mt7987_rfb,mt7622_rfb,mt7987_sd_rfb,mt7623a_unielec_u7623_02,mt7988_rfb,mt7623n_bpir2,mt7988_sd_rfb,mt7628_rfb,mt8183_pumpkin,mt7629_rfb,mt8365_evk,mt7981_emmc_rfb,mt8512_bm1_emmc,mt7981_rfb,mt8516_pumpkin,mt7981_sd_rfb,mt8518_ap1_emmc -b HEAD -c 9
David Lechner [Wed, 7 Jan 2026 16:21:14 +0000 (10:21 -0600)]
clk: mediatek: mt8365: remove separate topckgen-cg driver
Remove the separate topckgen-cg driver for handling clock gates in the
topckgen address space. The devicetree bindings for this were not
acceptable upstream because it was creating a separate clock controller
using the same address space as the main topckgen clock controller. The
gates are moved to the topckgen tree instead.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Wed, 7 Jan 2026 16:21:13 +0000 (10:21 -0600)]
clk: mediatek: allow gates in topckgen drivers
Add handling for gates in the topckgen clk drivers. This avoids the need
to have separate topckgen-cg drivers and devicetree nodes for the same
address space and clock ID range.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Wed, 7 Jan 2026 16:21:12 +0000 (10:21 -0600)]
clk: mediatek: mt8365: split struct mtk_clk_tree
Split the struct mtk_clk_tree for MT8365 into separate structures for
the apmixedsys, topckgen and infracfg clock controllers. This is needed
to support moving the topckgen gates into the struct mtk_clk_tree. Since
apmixedsys can also have gates, we need separate structures.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Wed, 7 Jan 2026 16:21:10 +0000 (10:21 -0600)]
clk: mediatek: fix fixed clock parents
Add a flags field to struct mtk_fixed_clk to allow properly resolving
the parent clock. All chip-specific clocks are updated to populate this
field correctly.
The parent is currently only used for printing debug information, so
there are no functional bugs being fixed.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Wed, 7 Jan 2026 16:21:09 +0000 (10:21 -0600)]
clk: mediatek: add separate gates_offs for cg gates
Add a gates_offs field to struct mtk_cg_priv and use that instead of
struct mtk_clk_tree.gates_offs.
Prior to this change, struct mtk_clk_tree.gates_offs could be the offset
of struct mtk_clk_tree.gates or struct mtk_cg_priv.gates depending on
the context. This was confusing and error-prone. For example, in mt8365
there is one set of gates that needs an offset and one that does not
that share the same struct mtk_clk_tree. This is fixed in this patch by
giving the correct offset for each gate separately.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Wed, 7 Jan 2026 16:21:08 +0000 (10:21 -0600)]
clk: mediatek: mt8365: fix missing and out of order clocks
Fix a few missing clocks and even more clocks in the incorrect order.
Since the clocks are looked up by index, having them out of order or
skipping an ID will lead to incorrect clocks being used.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Tom Rini [Mon, 12 Jan 2026 19:17:00 +0000 (13:17 -0600)]
Merge patch series "clk: mediatek: implement of_xlate and dump"
David Lechner <dlechner@baylibre.com> says:
I started looking into fixing some bugs in the mt8365 clock driver and
realized that there was no way to inspect or debug the clock trees.
I set out to implement the dump function to help with this. The driver
architecture didn't make this easy since there was no way to know the
number of elements in each of the clock arrays. The first few patches
in this series are adding fields to the data structures to hold this
information.
Once that was fixed, I was still getting crashes due to other bugs. To
work around this, I implemented the of_xlate function to validate clk
IDs as early as possible and return errors instead of crashing when
requested IDs are invalid. This also makes use of the new size fields
to prevent out of bounds array accesses. There are a couple of drivers
that remap IDs, so there are a few extra patches to handle that as well.
Then finally, I was able to implement the dump function to print out the
clock tree information without crashing. In the v1 cover letter, there
is an example of the output (it is quite long and doesn't need to be
repeated here).
David Lechner [Wed, 7 Jan 2026 15:50:18 +0000 (09:50 -0600)]
clk: mediatek: implement dump callbacks
Implement dump callbacks for Mediatek clocks. On these platforms, there
are 100s of clocks, so it can be easy to miss mistakes. The dump
callbacks will be useful for debugging and verifying clock configs.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Wed, 7 Jan 2026 15:50:17 +0000 (09:50 -0600)]
clk: mediatek: mt7623: set unmapped IDs to -1
Add range initializers to the id_offs_map arrays in the mt7623 clk
driver to set unmapped IDs to -1. This prevents accidental usage of
unmapped IDs that would otherwise map to 0.
mtk_common_clk_of_xlate() checks these values for < 0 and returns
-ENOENT in that case.
A range initializer covering the entire array is used since it is less
error-prone than manually looking up the value of each macro in the
existing initializers and checking for gaps. It is placed first so that
the specific initializers override it.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Wed, 7 Jan 2026 15:50:16 +0000 (09:50 -0600)]
clk: mediatek: clarify mapped vs. unmapped ID
Update documentation comments to clarify the difference between which
.id fields are mapped (only struct clk.id) vs. unmapped (all struct
mtk_*.id and .parent fields). The unmapped IDs are the ones defined
in the devicetree bindings, while the mapped IDs are the ones used as
the index into the various clk arrays.
Also fix spelling of "parent" while we are touching this.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Wed, 7 Jan 2026 15:50:15 +0000 (09:50 -0600)]
clk: mediatek: add of_xlate ops
Add driver-specific of_xlate ops for MediaTek clocks. This provides
better checking of the args passed from the devicetree. Compared to
the default of_xlate implementation, this will return -EINVAL if there
are zero args (id is always required) and -ENOENT if the id is out of
range for the clock type. This will protect against out of bounds array
accesses later on when the clk->id is used to index into the clock
data arrays.
If there is a id_offs_map, then we have to do that translation first
before checking the id to see if it is in range. There is no sense in
doing the mapping multiple times, so we save the mapped ID in clk->id
and remove mtk_clk_get_id().
mtk_clk_find_parent_rate() also had to be updated since it creates a
temporary struct clk to represent the parent clock. It now has do the
translation in case the parent clock also uses an id_offs_map.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Wed, 7 Jan 2026 15:50:14 +0000 (09:50 -0600)]
clk: mediatek: organize infrasys functions
Move all infrasys ops and related functions next to each other in the
file for better organization.
Generally all ops functions are grouped together like this for the other
ops types (apmixedsys, topckgen, etc). However the infrasys functions
were mixed in with the other sections making them harder to find. This
will also give a logical place to add any future infrasys-specific
functions.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Wed, 7 Jan 2026 15:50:11 +0000 (09:50 -0600)]
clk: mediatek: add array size fields to clk trees
Add num_plls, num_fclks, num_fdivs, num_muxes, and num_gates fields to
the mtk_clk_tree struct and populate them in the clk trees for all
existing drivers.
Currently, there is no bounds checking when accessing the arrays in
the clk tree structs. Adding these fields will allow for bounds checking
in the future.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Sean Anderson [Tue, 6 Jan 2026 21:55:01 +0000 (16:55 -0500)]
phy: zynqmp: Only wait for PLL lock "primary" instances
For PCIe and DisplayPort, the phy instance represents the controller's
logical lane. Wait for the instance 0 phy's PLL to lock as other
instances will never lock. We do this in xpsgtr_wait_pll_lock so callers
don't have to determine the correct lane themselves.
The original comment is wrong about cumulative wait times. Since we are
just polling a bit, all subsequent waiters will finish immediately.
Sean Anderson [Tue, 6 Jan 2026 21:55:00 +0000 (16:55 -0500)]
phy: zynqmp: Store instance instead of type
The phy "type" is just the combination of protocol and instance, and is
never used apart from that. Store the instance directly, instead of
converting to a type first. No functional change intended.
Sean Anderson [Tue, 6 Jan 2026 21:54:59 +0000 (16:54 -0500)]
phy: zynqmp: Enable reference clock correctly
Lanes can use other lanes' reference clocks, as determined by refclk.
Use refclk to determine the clock to enable/disable instead of always
using the lane's own reference clock. This ensures the clock selected in
xpsgtr_configure_pll is the one enabled.
For the other half of the equation, always program REF_CLK_SEL even when
we are selecting the lane's own clock. This ensures that Linux's idea of
the reference clock matches the hardware. We use the "local" clock mux
for this instead of going through the ref clock network.
Sean Anderson [Tue, 6 Jan 2026 21:54:58 +0000 (16:54 -0500)]
phy: zynqmp: Allow variation in refclk rate
Due to limited available frequency ratios, the reference clock rate may
not be exactly the same as the required rate. Allow a small (100 ppm)
deviation.
Neal Frager [Mon, 12 Jan 2026 07:21:39 +0000 (07:21 +0000)]
arch: dts: zynqmp: align cpu_opp_table with linux
Align the cpp_opp_table and pss_ref_clk values with Linux according to the
following patch submission:
https://lists.openwall.net/linux-kernel/2025/11/11/424
Michal Simek [Wed, 7 Jan 2026 12:12:49 +0000 (13:12 +0100)]
arm64: xilinx: Fix DT coding style violations
All these violations have been found by https://github.com/kylebonnici/dts-linter
but not all of them are taken. Adding newlines or long lines changes are
not taken.
Sean Anderson [Tue, 6 Jan 2026 22:08:53 +0000 (17:08 -0500)]
PCI: xilinx-nwl: Avoid crashing if configuring when the link is down
The ECAM will return a slave error if we access non-root devices while
the link is down. Add a check for this like Linux does so we don't
crash.
Fixes: 2f5ad77cfea ("PCI: zynqmp: Add ZynqMP NWL PCIe root port driver") Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Reviewed-by: Stefan Roese <stefan.roese@mailbox.org> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20260106220853.731358-1-sean.anderson@linux.dev
Michal Simek [Tue, 6 Jan 2026 07:45:39 +0000 (08:45 +0100)]
amd: versal2: Align distro boot variables with default memory map
By default Versal Gen 2 is using memory map where TF-A is placed to DDR and
there is also some space allocated for OP-TEE that's why move default
variable setting out of this location to avoid using it when distro boot is
used for booting.
projects / thirdparty / u-boot.git / log
