Some nand flashes (like spi-nand one) are registered with mtd
subsystem only, thus nand command can't be used to work with
such flashes. As result some functionality is missing.
This patch implements 'nand torture' functionality for mtd command.
Some nand flashes (like spi-nand one) are registered with mtd
subsystem only, thus nand command can't be used to work with
such flashes. As result some functionality is missing.
This patch implements 'nand markbad' functionality for mtd command.
mtd: spinand: repeat reading in regular mode if continuous reading fails
Continuous reading may result in multiple flash pages reading in one
operation. Unfortunately, not all spinand controllers support such
large reading. They will read less data. Unfortunately, the operation
can't be continued.
In this case:
* disable continuous reading on this (not good enough) spi controller
* repeat reading in regular mode.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
mtd: spinand: try a regular dirmap if creating a dirmap for continuous reading fails
Continuous reading may result in multiple flash pages reading in one
operation. Typically only one flash page has read/written (a little bit
more than 2-4 Kb), but continuous reading requires the spi controller
to read up to 512 Kb in one operation without toggling CS in beetween.
Roughly speaking spi controllers can be divided on 2 categories:
* spi controllers without dirmap acceleration support
* spi controllers with dirmap acceleration support
Firt of them will have issues with continuous reading if restriction on
the transfer length is implemented in the adjust_op_size() handler.
Second group often supports acceleration of single page only reading.
Thus enabling of continuous reading can break flash reading.
This patch tries to create dirmap for continuous reading first and
fallback to regular reading if spi controller refuses to create it.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
mtd: spinand: Sync core code and device support with Linux 6.17-rc1
This makes the U-Boot SPI NAND driver almost the same as in Linux
6.17-rc1. The only major differences are:
* support of ECC engines. The Linux driver supports different ECC
engines while U-Boot uses on-die ECC only.
* per operation maximum SPI bus frequency
There is already a manufacturer hook, which is manufacturer specific but
not chip specific. We no longer have access to the actual NAND identity
at this stage so let's add a per-chip configuration hook to align the
chip configuration (if any) with the core's setting.
This is a port of linux commit da55809ebb45 ("mtd: spinand: Add a ->configure_chip() hook")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
mtd: spinand: propagate spinand_wait() errors from spinand_write_page()
Since commit 3d1f08b032dc ("mtd: spinand: Use the external ECC engine
logic") the spinand_write_page() function ignores the errors returned
by spinand_wait(). Change the code to propagate those up to the stack
as it was done before the offending change.
This is a port of linux commit 091d9e35b85b ("mtd: spinand: propagate spinand_wait() errors from spinand_write_page()")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
mtd: spinand: Enhance the logic when picking a variant
Currently the best variant picked in the first one in the list provided
in the manufacturer driver. This worked well while all operations where
performed at the same speed, but with the introduction of DTR transfers
this no longer works correctly.
Let's continue iterating over all the alternatives, even if we find a
match, keeping a reference over the theoretically fastest
operation. Only at the end we can tell which variant is the best.
This logic happening only once at boot.
The patch is based on linux commit 666c299be696 (mtd: spinand: Enhance the logic when picking a variant)
created by Miquel Raynal <miquel.raynal@bootlin.com>
The code was a bit restricted in the functionality since not all
required functionality is supported in the u-boot.
Cheng Ming Lin [Tue, 30 Sep 2025 00:21:01 +0000 (03:21 +0300)]
mtd: spinand: Add read retry support
When the host ECC fails to correct the data error of NAND device,
there's a special read for data recovery method which can be setup
by the host for the next read. There are several retry levels that
can be attempted until the lost data is recovered or definitely
assumed lost.
This is the port of linux commit f2cb43c98010 (mtd: spinand: Add read retry support)
Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
mtd: spinand: add support of continuous reading mode
The code was ported from linux-6.12. The original continuous reading
support was implemented by Miquel Raynal <miquel.raynal@bootlin.com>
in linux commit 631cfdd0520d (mtd: spi-nand: Add continuous read support).
Here is an original patch description:
--------------------------------------
A regular page read consist in:
- Asking one page of content from the NAND array to be loaded in the
chip's SRAM,
- Waiting for the operation to be done,
- Retrieving the data (I/O phase) from the chip's SRAM.
When reading several sequential pages, the above operation is repeated
over and over. There is however a way to optimize these accesses, by
enabling continuous reads. The feature requires the NAND chip to have a
second internal SRAM area plus a bit of additional internal logic to
trigger another internal transfer between the NAND array and the second
SRAM area while the I/O phase is ongoing. Once the first I/O phase is
done, the host can continue reading more data, continuously, as the chip
will automatically switch to the second SRAM content (which has already
been loaded) and in turns trigger the next load into the first SRAM area
again.
From an instruction perspective, the command op-codes are different, but
the same cycles are required. The only difference is that after a
continuous read (which is stopped by a CS deassert), the host must
observe a delay of tRST. However, because there is no guarantee in Linux
regarding the actual state of the CS pin after a transfer (in order to
speed-up the next transfer if targeting the same device), it was
necessary to manually end the continuous read with a configuration
register write operation.
Continuous reads have two main drawbacks:
* They only work on full pages (column address ignored)
* Only the main data area is pulled, out-of-band bytes are not
accessible. Said otherwise, the feature can only be useful with on-die
ECC engines.
Performance wise, measures have been performed on a Zynq platform using
Macronix SPI-NAND controller with a Macronix chip (based on the
flash_speed tool modified for testing sequential reads):
- 1-1-1 mode: performances improved from +3% (2-pages) up to +10% after
a dozen pages.
- 1-1-4 mode: performances improved from +15% (2-pages) up to +40% after
a dozen pages.
This series is based on a previous work from Macronix engineer Jaime
Liao.
--------------------------------------
SkyHigh spinand device has ECC enable bit in configuration register but
it must be always enabled. If ECC is disabled, read and write ops
results in undetermined state. For such devices, a way to avoid raw
access is needed.
Introduce SPINAND_NO_RAW_ACCESS flag to advertise the device does not
support raw access. In such devices, the on-die ECC engine ops returns
error to I/O request in raw mode.
Checking and marking BBM need to be cared as special case, by adding
fallback mechanism that tries read/write OOB with ECC enabled.
This is a port of linux commit 6d9d6ab3a82a (mtd: spinand: Introduce a way to avoid raw access)
Cheng Ming Lin [Tue, 30 Sep 2025 00:20:57 +0000 (03:20 +0300)]
mtd: spinand: Add support for setting plane select bits
Add two flags for inserting the Plane Select bit into the column
address during the write_to_cache and the read_from_cache operation.
Add the SPINAND_HAS_PROG_PLANE_SELECT_BIT flag for serial NAND flash
that require inserting the Plane Select bit into the column address
during the write_to_cache operation.
Add the SPINAND_HAS_READ_PLANE_SELECT_BIT flag for serial NAND flash
that require inserting the Plane Select bit into the column address
during the read_from_cache operation.
This is a port of linux commit ca229bdbef29 (mtd: spinand: Add support for setting plane select bits)
Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20240909092643.2434479-2-linchengming884@gmail.com Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Daniel Golle [Tue, 30 Sep 2025 00:20:56 +0000 (03:20 +0300)]
mtd: spinand: set bitflip_threshold to 75% of ECC strength
Reporting an unclean read from SPI-NAND only when the maximum number
of correctable bitflip errors has been hit seems a bit late.
UBI LEB scrubbing, which depends on the lower MTD device reporting
correctable bitflips, then only kicks in when it's almost too late.
Set bitflip_threshold to 75% of the ECC strength, which is also the
default for raw NAND.
This is a port of linux commit 1824520e7477 (mtd: spinand: set bitflip_threshold to 75% of ECC strength)
mtd: spinand: Sync core code and device support with Linux 6.10
This makes the U-Boot SPI NAND driver almost the same as in Linux 6.10.
The only major difference is support of ECC engines. The Linux driver
supports different ECC engines while U-Boot uses on-die ECC only.
changes:
* Move spinand_check_ecc_status(), spinand_noecc_ooblayout_ecc(),
spinand_noecc_ooblayout_free() and spinand_noecc_ooblayout close
to each other.
* some code formatting
* remove comments not present in linux driver
No functional changes, just some refactoring to better match linux
kernel driver.
changes:
* move spinand configuration reading out from spinand_init_cfg_cache()
to separate function spinand_read_cfg()
* move spinand flash initialization to separate function
spinand_init_flash()
* move direct mapping initialization to the end of spinand_init()
mtd: spinand: Extend spinand_wait() to match Linux kernel implementation
This aligns spinand_wait() with the linux kernel. Instead of calling into
spi_mem_poll_status() which is not implemented in U-Boot, we code the
polling logic and make sure that schedule() is called periodically.
The module misses MODULE_DEVICE_TABLE() for both SPI and OF ID tables
and thus never autoloads on ID matches.
Add the missing declarations.
Present since day-0 of spinand framework introduction.
This is a port of linux commit 25fefc88c71f ("mtd: spinand: core: add missing MODULE_DEVICE_TABLE()")
Signed-off-by: Alexander Lobakin <alobakin@pm.me> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210323173714.317884-1-alobakin@pm.me Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> # U-Boot port Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Make use of the spi-mem direct mapping API to let advanced controllers
optimize read/write operations when they support direct mapping.
Based on a linux commit 981d1aa0697c ("mtd: spinand: Use the spi-mem dirmap API")
created by Boris Brezillon <bbrezillon@kernel.org> with additional
fixes taken from Linux 6.10.
Michal Simek [Wed, 1 Oct 2025 06:20:07 +0000 (08:20 +0200)]
usb: onboard-hub: Make i2c-bus optional
DT binding doesn't mandate i2c-bus as required property because hub itself
doesn't need to have i2c connected.
It can be in standalone mode that only power regulator and reset should be
handled.
Or hub should be configured via spi interface.
Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Tom Rini [Fri, 3 Oct 2025 21:20:58 +0000 (15:20 -0600)]
Merge patch series "Drop ATAGS for B&R boards"
Wolfgang Wallner <wolfgang.wallner@br-automation.com> says:
There was recently a discussion on which boards need ATAGS support.
The B&R boards which have this support enabled actualyl don't need it.
This patch series drops the settings from the relevant defconfigs.
Tom Rini [Mon, 15 Sep 2025 19:05:48 +0000 (13:05 -0600)]
cmd: spl: Remove ATAG support from this command
While we continue to have some systems which support extremely legacy
OS booting methods, we do not have use cases for supporting this in
Falcon mode anymore. Remove this support and references from the
documentation.
Co-developed-by: Anshul Dalal <anshuld@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Mon, 22 Sep 2025 12:29:22 +0000 (14:29 +0200)]
linux/kernel.h: Update upper_NN_bits() and lower_NN_bits() macros
Synchronize upper_NN_bits() and lower_NN_bits() macros with Linux 6.16
commit 118d777c4cb4 ("wordpart.h: Add REPEAT_BYTE_U32()"). This fixes the
lower_32_bits() macros and assures it works with 64bit systems correctly.
This also adds 16bit variants of these macros, which will be used by the
Airoha PHY driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Tom Rini <trini@konsulko.com>
arm: armv8: remove redundant definition of mmu_status
mmu_status is used in io memcpy functions to prevent accesses to non
8-byte aligned addresses when the mmu is disabled. Though there is a
redundant definition enabled when icaches is turned off by setting
SYS_ICACHE_OFF.
This patch removes the redundant definition, allowing mmu_status to
properly report the status regardless of config settings. This shouldn't
be a problem since access to non 8-byte aligned data can be done
irrespective of icache state.
Commit 9fe2e4b46458 ("fdt: Make sure there is no stale initrd left")
introduces a regression in case when U-Boot transfers control to an EFI
app which acts as a subsequent bootloading program. Such an app might
try to set "linux,initrd-start" and "linux,initrd-end" fdt properties,
but by that time those properties are already removed by the code added
in the mentioned commit.
Particularly, the issue was observed on the E850-96 board where GBL EFI
app [1] can't run Android successfully anymore. More specifically, the
kernel can't see the ramdisk and panics with next messages:
/dev/root: Can't open blockdev
VFS: Cannot open root device "" or unknown-block(0,0): error -6
Please append a correct "root=" boot option; ...
Kernel panic - not syncing: VFS: Unable to mount root fs on
unknown-block(0,0)
fdt_initrd() function (where initrd dts properties are removed) is
called two times:
1. First it's called by EFI boot manager (e.g. as a part of U-Boot
Standard Boot mechanism) when it's installing FDT:
Martin Schwan [Wed, 1 Oct 2025 07:44:37 +0000 (09:44 +0200)]
doc: pytest: Fix inline code and other formatting
Mainly fix inline code and some other formatting mistakes. Inline code
uses double backticks `` in reStructuredText instead of single backticks
as in Markdown.
Also fix some smaller formatting issues, such as excess colons before
literal blocks.
Javier Tia [Tue, 30 Sep 2025 12:53:28 +0000 (06:53 -0600)]
doc: Update coding style to recommend b4 for patch submission
Replace references to patman with b4 as the recommended tool for
preparing and sending patches. b4 is widely adopted in the Linux kernel
community and U-Boot ships with configuration to simplify its use with
the project mailing list.
The updated guidelines describe how to prepare series with b4, handle
cover letters and recipient lists, run style checks, and send patches
safely. Instructions also highlight how to collect and apply review tags
before resending.
This change documents the preferred workflow for contributors and
ensures consistency with common practices across related upstream
communities.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Javier Tia <javier.tia@linaro.org>
Michal Simek [Mon, 22 Sep 2025 16:03:39 +0000 (18:03 +0200)]
env: spi: Fix gd->env_valid for the first write
When both SPI environment locations are invalid (gd->env_valid ==
ENV_INVALID), the first call to saveenv writes to the primary location and
sets the active flag. However, the logic for updating gd->env_valid
incorrectly sets it to ENV_REDUND, which does not match the actual location
written. This causes the first two writes to target the same location, and
alternation only begins after the second write.
Update the logic to alternate gd->env_valid based on whether the last write
was to the primary or redundant location, ensuring the first write sets
ENV_VALID and subsequent writes alternate as expected. This aligns
env_valid with the actual storage location and fixes the alternation
sequence from the first write.
With this change, the "Valid environment" printout correctly reflects the
active location after each save, and the alternation between primary and
redundant locations works as intended from the start.
Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org> Acked-by: E Shattow <e@freeshell.de>
Andrew Goodbody [Wed, 1 Oct 2025 09:28:37 +0000 (10:28 +0100)]
b4-config: Improve b4 config for correct operation
The recent change to .b4-config resulted in some expected recipients not
being added to the address lists. Rework the commands so that all
expected recipients are added while maintaining the ordering from the
first change.
Fixes: 26efc940c86 ("b4-config: configure `b4` for U-Boot") Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:
* Agilex5 enhancements:
- USB3.1 enablement and DWC3 host driver support
- System Manager register configuration for USB3
- Watchdog timeout increase and SDMMC clock API integration
- dcache handling improvements in SMC mailbox path
- Enable SPL_SYS_DCACHE_OFF in defconfig
* Clock driver improvements:
- Introduce dt-bindings header for Agilex clocks
- Add enable/disable API and EMAC clock selection fixes
- Replace manual shifts with FIELD_GET usage
* Device tree changes:
- Agilex5: disable cache allocation for reads
- Stratix10: add NAND IP node
- Enable driver model watchdog
- Enable USB3.1 node for Agilex5
* Config cleanups:
- Simplify Agilex7 VAB defconfig
- Remove obsolete SYS_BOOTM_LEN from N5X VAB config
- Enable CRC32 support for SoCFPGA
- Increase USB hub debounce timeout
Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.
This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
Tom Rini [Tue, 30 Sep 2025 22:01:05 +0000 (16:01 -0600)]
Merge tag 'u-boot-amlogic-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next
- set reversed bit when using internal phy on GXL SoCs
- support gpio toggle command for amlogic gpio
- fix saradc
- remove unreachable in meson clk driver
- Stop premature exit from for loop in meson pwm driver
- fix JetHub D1 eth mac fallback generation
Andrew Goodbody [Fri, 8 Aug 2025 09:34:43 +0000 (10:34 +0100)]
pwm: meson: Stop premature exit from for loop
In meson_pwm_probe the for loop attempts to get the name of a clock but
the following if..else statements only perform useful work if -ENODATA
is returned from clk_get_by_name. If clk_get_by_name simply succeeds
then this results in a premature exit from the for loop and the
following code can never be reached. Make the else clause only apply for
an error return from clk_get_by_name.
Andrew Goodbody [Tue, 22 Jul 2025 14:06:14 +0000 (15:06 +0100)]
adc: meson-saradc: uint cannot be less than zero
timeout is declared as a uint but then tested for being less than zero
which must always fail. Change the while loop for a pre-decrement on
timeout and test timeout for being zero.
Neil Armstrong [Fri, 2 May 2025 06:51:45 +0000 (08:51 +0200)]
net: mdio: mux-meson-gxl: set reversed bit when using internal phy
This bit is necessary to receive packets from the internal PHY.
Without this bit set, no activity occurs on the interface.
Normally u-boot sets this bit, but if u-boot is compiled without
net support, the interface will be up but without any activity.
The vendor SDK sets this bit along with the PHY_ID bits.
Ported from the Linux change at [1] from Da Xu merged in
commit [2].
[1] https://lore.kernel.org/all/20250425192009.1439508-1-da@libre.computer/
[2] b23285e93bef ("net: mdio: mux-meson-gxl: set reversed bit when using internal phy")
board: mpfs_icicle: fix pointer assignment in board_fdt_blob_setup()
Correct the assignment in board_fdt_blob_setup() to use *fdtp instead of
fdtp, ensuring the caller receives the correct FDT address. This
resolves an issue where the device tree pointer was not properly set due
to assigning to the local parameter rather than the dereferenced
pointer.
Restore support for environment storage in EXT4 filesystem on eMMC boot.
The previous cleanup incorrectly removed this fallback option which is
needed for boards that store their environment in an EXT4 partition.
This configuration is OS-specific rather than board-dependent and should
remain as it is configurable via menuconfig. Even if it is not described
in ST defconfigs people may have enabled it in their defconfig.
Tim Harvey [Mon, 29 Sep 2025 19:21:49 +0000 (12:21 -0700)]
net: lwip: ensure alignment of packet buffers
Network packet buffers should be aligned to PKTALIGN. Add a compiler
attribute to ensure this.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
[jf: use __aligned(x) from <linux/compiler_attributes.h>] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
net: lwip: dhcp: set ntpserverip environment variable
Once the DHCP exchange is complete, if we have an IP address for an NTP
server, set the ntpserverip environment variable accordingly. Although
not necessary to make the sntp command use that server (since it is
known internally to the lwIP stack), this makes the behavior in line
with the legacy NET stack. This is also consistent with exporting the
DNS servers etc.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Suggested-by: Michal Simek <michal.simek@amd.com>
net: lwip: dhcp: make NTP servers usable by the sntp command
When both CMD_DHCP and CMD_SNTP are enabled, one would expect the NTP
servers received by DHCP to be used by the sntp command by default. Fix
dhcp_loop() so that it is indeed the case.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reported-by: Michal Simek <michal.simek@amd.com>
net: lwip: enable debug traces for SNTP when CONFIG_LWIP_DEBUG is set
Now that SNTP is supported, enable SNTP debug traces when LWIP_DEBUG is
enabled. In particular, this allows to see which NTP servers are
received during DHCP.
Andrew Goodbody [Mon, 29 Sep 2025 09:11:57 +0000 (10:11 +0100)]
usb: dwc3: Remove redundant test
In dwc3_ep0_complete_data there is a test for 'r' being null and the
code will return at that point if so. After that point 'r' is guaranteed
to not be null and testing for that is redundant. Remove the test for
'r' being non-null.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org> Link: https://lore.kernel.org/r/20250929-dwc3_ep0-v1-1-1d5c58933bde@linaro.org Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Chance Yang [Tue, 26 Aug 2025 03:36:17 +0000 (11:36 +0800)]
fastboot: Fix has-slot command always returning yes for fb_nand
The issue was a mismatch in return value conventions between functions:
- getvar_get_part_info() expects >= 0 for success
- fb_nand_lookup() returns 0 on success, 1 on failure (from
mtdparts_init and find_dev_and_part)
When partition didn't exist, fb_nand_lookup returned 1, but
fastboot_nand_get_part_info passed it directly to getvar_get_part_info,
which treated 1 >= 0 as success, causing has-slot to always return yes.
Fix by converting positive return values to -ENOENT in
fastboot_nand_get_part_info to match the expected error convention.
arch: arm: socfpga: Configure USB3 System Manager registers
For successful reset staggering pulse operation, reset pulse
override bit is set. Port overcurrent bit 1, which in reality
reflects PIPE power present signal is set to avoid giving
false information of Vbus status to HPS controller.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
configs: Increase USB Hub debounce timeout in Agilex5
Some legacy USB mass storage devices during connection were
observed to have debounce issues. Hence, increasing the default
USB Hub debounce timeout value to handle this issue for devices
connected to Agilex5 boards.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
drivers: clk: agilex: Support for enable/disable API
Update Agilex clock driver to support enabling or disabling
the peripheral clocks via clock driver model APIs.
The caller will pass the clock ID to this driver and the driver
will then proceed to manipulate the desired bit in the Agilex clock
manager peripheral PLL register based on the given clock ID.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Boon Khai Ng [Thu, 14 Aug 2025 03:17:40 +0000 (11:17 +0800)]
cache: Check dcache availability before calling cache functions
When the data cache (dcache) is disabled, calling related
status functions can lead to compilation errors due to
undefined references.
Adding a !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) check before
invoking dcache_status() (used in common/memsize.c:get_ram_size())
and mmu_status() (from arch/arm/include/asm/io.h).
Without this check, builds with dcache disabled will fail to compile.
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Boon Khai Ng [Thu, 14 Aug 2025 03:17:39 +0000 (11:17 +0800)]
arch: arm: mach-socfpga: smc: Add dcache flushing and invalidation in smc_send_mailbox()
Adding the dcache flushing and invalidation in the smc_send_mailbox()
At the same time replace the use of u64 with uintptr_t to ensure
compatibility across different architectures and correct the
pointer arithmetic for buffer end address calculation.
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: socfpga: mailbox: Remove CONFIG_CADENCE_QSPI guard from QSPI mailbox API declarations
The QSPI mailbox API function declarations (mbox_qspi_close and
mbox_qspi_open) in mailbox_s10.h were guarded by CONFIG_CADENCE_QSPI
preprocessor conditional. This prevented their prototypes from being
visible to code that may use the stub implementations when
CONFIG_CADENCE_QSPI is disabled.
Remove the CONFIG_CADENCE_QSPI preprocessor conditional so these functions
are always declared, regardless of the configuration. This avoids potential
build or linkage errors when stubs are used.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: socfpga: Define Use FPGA switch handoff section size for Agilex5
Agilex5 FPGA switch section in the handoff data is larger by 32 bytes
than the default value as these extra sections contains I3C0 and I3C1
register offsets and values with 4 bytes each.
This requires 4 more times of reading the FPGA switch section of the
handoff data to fully populate the handoff data table in the memory
during runtime.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
drivers: ddr: altera: Correct DDR calibration status check
Bit 3 of the seq2core register is no longer set to indicate
calibration completion. Instead, added polling of the seq2core
register until it reads 0b00000111, signaling that the Nios
processor has started the calibration process.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Compatibility check of IOSSM mailbox with U-Boot is performed
by verifying the mailbox specification version. If check fails,
appropriate error message is displayed.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
configs: socfpga: Remove SYS_BOOTM_LEN from N5X VAB config
Remove the current CONFIG_SYS_BOOTM_LEN in N5X VAB defconfig.
Previously, the size was set to 32MB, but due to larger kernel image,
64MB size is required. This 64MB configuration has been set as
default in the Kconfig.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
To ensure unintentional bugs occurring because of config changes
in master defconfig and its VAB variants, VAB defconfig files now
include the master defconfig and enable config values specific to
VAB functionality only.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: dts: socfpga: Enable driver model for watchdog timer
All SoCFPGA platforms are switching to CONFIG_WDT (driver
model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Status
of watchdog is enabled to assist with this switching.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arch: arm: dts: agilex5: Disable cache allocation for reads
In order to circumvent CCU NOC issue in Agilex5, it is recommended
to disable cache allocation for reads. This prevents hang issues
caused by CCP (Common Cache Pipe) Fill Done FIFO overflow.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
While it is good that the "Licenses/" directory contains the text
for all licenses that are applicable to u-boot code, it is harder
to determine at a glance what the default and/or preferred license
is. While humans can look at the Licenses/README file, this is not
machine parseable, making it tricky for license detection tools to
automatically determine/report on the overall / aggregate u-boot
license.
The project previously had a top level COPYING file containing a
short blurb, followed by the GPL license text. This was removed
back in commit eca3aeb352c964bdb28b8e191d6326370245e03f when
the "Licenses/" directory was introduced. For the benefit of
automated tools, it is helpful to retain a top level COPYING
file in the repository. Rather than duplicate the license text,
however, a symlink from the Licenses/gpl-2.0.txt file should
suffice.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reported-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Tom Rini <trini@konsulko.com>
* Correct encodings for spl memory layout diagrams
* Suggest usage of KDOC_WERROR when building documentation
* Replace references to README.fdt-control
* Clarify precedence of environment locations
* Add documentation for the TI am335x_evm board
* Remove README.commands.itest
* Add a note about asking for feedback in the development process
Michal Simek [Wed, 24 Sep 2025 14:18:18 +0000 (16:18 +0200)]
efi_loader: Cleanup UEFI Variables menu selection
There are 3 options listed between choice/endchoice FILE/TEE/NO_STORE.
There is no reason to add other config with dependencies between
choice/endchoice because they can never be selected because they depends on
only that 3 options which can be selected.
That's why move additional configuration with dependency below choice
section.
Signed-off-by: Michal Simek <michal.simek@amd.com>
projects / thirdparty / u-boot.git / log
