This patch removes a number of struct and macro declaration that
were found through `git-grep` to be unused. Most of those are
related to compressor options and super block flags.
For reading a SquashFS image, we do not need the compressor options
or the flags. Those only encode settings used for packing the image,
mksquashfs uses them when appending data to an existing image. The
kernel implementation does not touch those, and we don't need them
either.
Signed-off-by: David Oberhollenzer <goliath@infraroot.at>
Sean Anderson [Sat, 28 Oct 2023 22:57:27 +0000 (18:57 -0400)]
test: eth: Don't crash if env_get returns NULL
env_get can return NULL if it fails to find the variable. Check its result
before using it.
Fixes: 6d9764c2a87 ("dm: test: Add a new test case against dm eth codes for NULL pointer access") Fixes: df33fd28897 ("test: eth: Add test for ethernet addresses") Signed-off-by: Sean Anderson <seanga2@gmail.com>
Tom Rini [Thu, 16 Nov 2023 17:55:48 +0000 (12:55 -0500)]
Merge patch series "spl: Use common function for loading/parsing images"
To quote the author:
This series adds support for loading all image types (Legacy (with and without
LZMA), FIT (with and without LOAD_FIT_FULL), and i.MX) to the MMC, SPI, NOR,
NET, FAT, EXT, NVMe, and semihosting load methods. It does this by introducing a
helper function which handles the minutiae of invoking the proper parsing
function, and reading the rest of the image.
Hopefully, this will make it easier for load methods to support all image types
that U-Boot supports, without having undocumented unsupported image types. I
applied this to several loaders which were invoking spl_load_simple_fit and/or
spl_parse_image_header, but I did not use it with others (e.g. DFU/RAM) which
had complications in the mix.
This series is organized roughly into two parts. Patches up to "spl: Add generic
spl_load function" are all setup or size-reduction oriented. Later patches
generally convert various load functions to spl_load.
bloat-o-meter results (for CONFIG_SPL only) at [1]. Size growth has been the
bigegst challenge to preparing this series. I have used every trick I can think
of to reduce bloat. Some SAMA boards no longer fit, but I have a plan to fix
them [2].
This is bar far the largest and most-difficult revision of this series to-date.
There are probably still things which can reduce the size, but I have been
working on this series for the better part of two months and I think it is a
good idea to get some feedback. Because of the SAMA bloat, this series will not
pass CI, so I expect to do a v7 before this is ready to apply. Feel free,
however, to apply patches in the first half (especially the fixes).
This version of the series is better-tested than ever before, thanks to some new
unit tests. However, things like the i.MX ROMAPI are untested. NAND should also
be tested more-widely, for reasons listed in the commit message. I encourage you
try this series out on your favorite board.
[1] https://gist.github.com/Forty-Bot/5bfe88676dd3c2aec6ebc23abb08e06f
This includes some changes to am335x_evm_spiboot and am65x_evm_r5_usbdfu
which have since been undone. This was ran for v6.
[2] https://lore.kernel.org/u-boot/20231105022742.632175-1-seanga2@gmail.com/
Sean Anderson [Wed, 8 Nov 2023 16:48:58 +0000 (11:48 -0500)]
spl: fat: Add option to disable DMA alignment
If we don't DMA-align buffers we pass to FAT, it will align them itself.
This behaviour likely should be deprecated in favor of
CONFIG_BOUNCE_BUFFER, but that's a task for another series. For the
meantime, don't bother aligning the buffer unless we had been doing so in
the past.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:57 +0000 (11:48 -0500)]
spl: spi: Consolidate spi_load_image_os into spl_spi_load_image
spi_load_image_os performs almost the same steps as the non-falcon-boot
path of spl_spi_load_image. The load address is different, and it also
loads a device tree, but that's it. Refactor the boot process so that
they can both use the same load function.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:56 +0000 (11:48 -0500)]
spl: Convert spi to spl_load
This converts the spi load method to use spl_load. The address used for
LOAD_FIT_FULL may be different, but there are no in-tree users of that
config. Since payload_offs is only used without OS_BOOT, we defer its
initialization.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:53 +0000 (11:48 -0500)]
spl: Convert nor to spl_load
This converts the nor load method to use spl_load. As a result it also
adds support for LOAD_FIT_FULL. Since this is the last caller of
spl_load_legacy_img, it has been removed.
We can't load FITs with external data with SPL_LOAD_FIT_FULL, so disable the
test in that case. No boards enable SPL_NOR_SUPPORT and SPL_LOAD_FIT_FULL, so
this is not a regression.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:51 +0000 (11:48 -0500)]
spl: Convert nand to spl_load
This converts the nand load method to use spl_load. nand_page_size may not
be valid until after nand_spl_load_image is called (see e.g. fsl_ifc_spl),
so we set bl_len in spl_nand_read. Since spl_load reads the header for us,
we can remove that argument from spl_nand_load_element.
There are two possible regressions which could result from this commit.
First, we ask for a negative address from spl_get_load_buffer. That is,
instead of
this could cause a problem if spl_get_load_buffer does not return valid
memory for negative offsets. Second, we now set bl_len for legacy images.
This can cause memory up to a bl_len - 1 before the image load address to
be written, which might not have been the case before. If this turns out to
be a problem, we can add an option for a bounce buffer.
We can't load FITs with external data with SPL_LOAD_FIT_FULL, so disable the
test in that case. No boards enable SPL_NAND_SUPPORT and SPL_LOAD_FIT_FULL, so
this is not a regression.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:50 +0000 (11:48 -0500)]
spl: Convert mmc to spl_load
This converts the mmc loader to spl_load. Legacy images are handled by
spl_load (via spl_parse_image_header), so mmc_load_legacy can be
omitted. To accurately determine whether mmc_load_image_raw_sector is used
(which might not be the case if SYS_MMCSD_FS_BOOT is enabled), we introduce
a helper config SYS_MMCSD_RAW_MODE. This ensures we can inline spl_load
correctly when a board only boots from filesystems. We still need to check
for SPL_MMC, since some boards enable configure raw mode even without MMC
support.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:47 +0000 (11:48 -0500)]
spl: Add generic spl_load function
Implementers of SPL_LOAD_IMAGE_METHOD have to correctly determine what
type of image is being loaded and then call the appropriate image load
function correctly. This is tricky, because some image load functions
expect the whole image to already be loaded (CONFIG_SPL_LOAD_FIT_FULL),
some will load the image automatically using spl_load_info.read()
(CONFIG_SPL_LOAD_FIT/CONFIG_SPL_LOAD_IMX_CONTAINER), and some just parse
the header and expect the caller to do the actual loading afterwards
(legacy/raw images). Load methods often only support a subset of the
above methods, meaning that not all image types can be used with all
load methods. Further, the code to invoke these functions is
duplicated between different load functions.
To address this problem, this commit introduces a "spl_load" function.
It aims to handle image detection and correct invocation of each of the
parse/load functions.
Although this function generally results in a size reduction with
several users, it tends to bloat boards with only a single user.
This is generally because programmers open-coding the contents of this
function can make optimizations based on the specific loader. For
example, NOR flash is memory-mapped, so it never bothers calling
load->read. The compiler can't really make these optimizations across
translation units. LTO solves this, but it is only available on some
arches. To address this, perform "pseudo-LTO" by inlining spl_load when
there are one or fewer users. At the moment, there are no users, so
define SPL_LOAD_USERS to be 0.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:46 +0000 (11:48 -0500)]
test: spl: Support testing LEGACY_LZMA filesystem images
These will soon be supported, so we need to be able to test it. Export the
lzma data and generally use the same process in spl_test_mmc_fs as
do_spl_test_load. If we end up needing this in third place in the future,
it would probably be good to refactor things out.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:44 +0000 (11:48 -0500)]
spl: nand: Remove spl_nand_legacy_read
Now that spl_nand_fit_read works in units of bytes, it can be combined with
spl_nand_legacy_read. Rename the resulting function spl_nand_read, since it
is no longer FIT-specific.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:43 +0000 (11:48 -0500)]
spl: Only support bl_len when we have to
Aligning addresses and sizes causes overhead which is unnecessary when we
are not loading from block devices. Remove bl_len when it is not needed.
For example, on iot2050 we save 144 bytes with this patch (once the rest of
this series is applied):
add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-144 (-144)
Function old new delta
spl_load_simple_fit 920 904 -16
load_simple_fit 496 444 -52
spl_spi_load_image 384 308 -76
Total: Before=87431, After=87287, chg -0.16%
We use panic() instead of BUILD_BUG_ON in spl_set_bl_len because we still
need to be able to compile it for things like mmc_load_image_raw_sector,
even if that function will not be used.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:42 +0000 (11:48 -0500)]
spl: Remove filename from spl_load_info
For filesystems, filename serves the same purpose as priv. However,
spl_load_fit_image also uses it to determine whether to use a DMA-aligned
buffer. This is beneficial for FAT, which uses a bounce-buffer if the
destination is not DMA-aligned. However, this is unnecessary now that
filesystems set bl_len to ARCH_DMA_MINALIGN instead. With this done, we can
remove filename entirely.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:41 +0000 (11:48 -0500)]
spl: Set FAT bl_len to ARCH_DMA_MINALIGN
Instead of relying on the presence of filename to determine whether we are
dealing with a FAT filesystem (and should DMA-align the buffer), have FAT set
bl_len to ARCH_DMA_MINALIGN instead. With this done, we can remove the
special-case logic checking for the presence of filename.
Because filesystems are not block-based, we may read less than the size passed
to spl_load_info.read. This can happen if the file size is not DMA-aligned. This
is fine as long as we read the amount we originally wanted to. Modify the
conditions for callers of spl_load_info.read to check against the original,
unaligned size to avoid failing spuriously.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:40 +0000 (11:48 -0500)]
spl: Refactor spl_load_info->read to use units of bytes
Simplify things a bit for callers of spl_load_info->read by refactoring it
to use units of bytes instead of bl_len. This generally simplifies the
logic, as MMC is the only loader which actually works in sectors. It will
also allow further refactoring to remove the special-case handling of
filename. spl_load_legacy_img already works in units of bytes (oops) so it
doesn't need to be changed.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 16 Nov 2023 17:46:09 +0000 (12:46 -0500)]
Merge patch series "nand: Add sandbox tests"
To quote the author:
This series tests raw nand flash in sandbox and fixes various bugs discovered in
the process. I've tried to do things in a contemporary manner, avoiding the
(numerous) variations present on only a few boards. The test is pretty minimal.
Future work could test the rest of the nand API as well as the MTD API.
Bloat (for v1) at [1] (for boards with SPL_NAND_SUPPORT enabled). Almost
everything grows by a few bytes due to nand_page_size. A few boards grow more,
mostly those using nand_spl_loaders.c. CI at [2].
Sean Anderson [Wed, 8 Nov 2023 16:48:38 +0000 (11:48 -0500)]
spl: Remove dev from spl_load_info
dev and priv serve the same purpose, and are never set at the same time.
Remove dev and convert all users to priv. While we're at it, reorder bl_len
to be last for better alignment.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:37 +0000 (11:48 -0500)]
spl: Remove NULL assignments in spl_load_info
Remove NULL assignments to fields in spl_load_info when .load doesn't
reference these fields. This can result in more efficient code. filename
must stay even if it is unused, since load_simple_fit uses it.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:36 +0000 (11:48 -0500)]
spl: semihosting: Don't close fd before spl_load_simple_fit
On real hardware, semihosting calls tend to have a large constant
overhead (on the order of tens of milliseconds). Reduce the number of
calls by one by reusing the existing fd in smh_fit_read, and closing it
at the end of spl_smh_load_image.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Wed, 8 Nov 2023 16:48:34 +0000 (11:48 -0500)]
arm: Disable SPL_FS_FAT when it isn't used
Several boards enable SPL_FS_FAT and SPL_LIBDISK_SUPPORT when they can't be
used (as there is no block device support enabled). Disable these configs.
The list of boards was generated with the following command:
LIBDISK was left enabled for the am* boards, since it seems to result in
actual size reduction, indicating that partitions are being used for
something.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Michal Simek <michal.simek@amd.com>
Sean Anderson [Wed, 8 Nov 2023 16:48:33 +0000 (11:48 -0500)]
spl: blk_fs: Fix uninitialized return value when we can't get a blk_desc
Initialize ret to avoid returning garbage if blk_get_devnum_by_uclass_id
fails.
Fixes: 8ce6a2e1757 ("spl: blk: Support loading images from fs") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sun, 5 Nov 2023 02:27:42 +0000 (22:27 -0400)]
arm: Enable SYS_THUMB_BUILD on AT91
Several AT91 boards are quite close to their SPL size limit. For example,
sama5d27_wlsom1_ek_mmc is just 173 bytes short of its limit and doesn't
even fit with older GCCs.
All AT91 processors should have thumb support. Enable SYS_THUMB_BUILD. This
shrinks SPL by around 30%.
Sean Anderson [Sat, 4 Nov 2023 20:37:53 +0000 (16:37 -0400)]
test: spl: Add a test for NAND
Add a SPL test for the NAND load method. We use some different functions to
do the writing from the main test since things like nand_write_skip_bad
aren't available in SPL.
We disable BBT scanning, since scan_bbt is only populated when not in SPL.
We use nand_spl_loaders.c as it seems to be common to at least a few boards
already. However, we do not use nand_spl_simple.c because it would require
us to implement cmd_ctrl. The various nand load functions are adapted from
omap_gpmc. However, they have been modified for simplicity/correctness.
Sean Anderson [Sat, 4 Nov 2023 20:37:52 +0000 (16:37 -0400)]
nand: Add sandbox driver
Add a sandbox NAND flash driver to facilitate testing. This driver supports
any number of devices, each using a single chip-select. The OOB data is
stored in-band, with the separation enforced through the API.
For now, create two devices to test with. The first is a very small device
with basic ECC. The second is an 8G device (chosen to be larger than 32
bits). It uses ONFI, with the values copied from the datasheet. It also
doesn't need too strong ECC, which speeds things up.
Although the nand subsystem determines the parameters of a chip based on
the ID, the driver itself requires devicetree properties for each
parameter. We do not derive parameters from the ID because parsing the ID
is non-trivial. We do not just use the parameters that the nand subsystem
has calculated since that is something we should be testing. An exception
is made for the ECC layout, since that is difficult to encode in the device
tree and is not a property of the device itself.
Despite using file I/O to access the backing data, we do not support using
external files. In my experience, these are unnecessary for testing since
tests can generally be written to write their expected data beforehand.
Additionally, we would need to store the "programmed" information somewhere
(complicating the format and the programming process) or try to detect
whether block are erased at runtime (degrading probe speeds).
Information about whether each page has been programmed is stored in an
in-memory buffer. To simplify the implementation, we only support a single
program per erase. While this is accurate for many larger flashes, some
smaller flashes (512 byte) support multiple programs and/or subpage
programs. Support for this could be added later as I believe some
filesystems expect this.
To test ECC, we support error-injection. Surprisingly, only ECC bytes in
the OOB area are protected, even though all bytes are equally susceptible
to error. Because of this, we take care to only corrupt ECC bytes.
Similarly, because ECC covers "steps" and not the whole page, we must take
care to corrupt data in the same way.
Sean Anderson [Sat, 4 Nov 2023 20:37:51 +0000 (16:37 -0400)]
arch: sandbox: Add function to create temporary files
When working with sparse data buffers that may be larger than the address
space, it is convenient to work with files instead. Add a function to create
temporary files of a certain size.
Sean Anderson [Sat, 4 Nov 2023 20:37:49 +0000 (16:37 -0400)]
nand: Add function to unregister NAND devices
This performs the opposite of nand_register, allowing drivers to unregister
nand devices. This is probably unnecessary for most regular drivers, but we
expect sandbox drivers to get repeatedly bound/unbound, so this will help
avoid dangling pointers.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Sean Anderson [Sat, 4 Nov 2023 20:37:44 +0000 (16:37 -0400)]
spl: nand: Set bl_len to page size
Since commit 34793598c83 ("mtd: nand: mxs_nand_spl: Remove the page aligned
access") there are no longer any users of nand_get_mtd. However, it is
still important to know what the page size is so we can allocate a
large-enough buffer. If the image size is not page-aligned, we will go off
the end of the buffer and clobber some memory.
Introduce a new function nand_page_size which returns the page size. For
most drivers it is easy to determine the page size. However, a few need to
be modified since they only keep the page size around temporarily.
It's possible that this patch could cause a regression on some platforms if
the offset is non-aligned and there is invalid address space immediately
before the load address. spl_load_legacy_img does not (except when
compressing) respect bl_len, so only boards with SPL_LOAD_FIT (8 boards) or
SPL_LOAD_IMX_CONTAINER (none in tree) would be affected.
All the sitara boards have DDR mapped at 0x80000000. gwventana is an i.MX6Q
which has DDR at 0x10000000. I don't have the IMX8MNRM handy, but on the
i.MX8M DDR starts at 0x40000000. Therefore all of these boards can handle a
little underflow.
Sean Anderson [Sat, 4 Nov 2023 20:37:43 +0000 (16:37 -0400)]
spl: legacy: Honor bl_len when decompressing
When allocating a buffer to load compressed data into, we need to ensure we
have enough space for over- and under-flow due to alignment. Otherwise we
will clobber the malloc bookkeeping data. Calculate the correct amount of
overhead and use it when determining the size.
Sean Anderson [Sat, 4 Nov 2023 20:37:42 +0000 (16:37 -0400)]
nand: spl_loaders: Only read enough pages to load the image
All other implementations of nand_spl_load_image only read as many pages as
are necessary to load the image. However, nand_spl_loaders.c loads the full
block. Align it with other load functions so that it is easier to
determine how large of a load buffer we need.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Contrary to what the help message says, this is the number of pages per
block. Calculate it automatically based on SYS_NAND_BLOCK_SIZE and
SYS_NAND_PAGE_SIZE. To better reflect its semantics, rename it to
SYS_NAND_BLOCK_PAGES.
Sean Anderson [Sat, 4 Nov 2023 20:37:40 +0000 (16:37 -0400)]
nand: Don't dereference NULL manufacturer_desc
When no manufacturer is matched, manufacturer_desc is NULL. Avoid
dereferencing it in that case.
Fixes: 4e67c571252 ("mtd,ubi,ubifs: sync with linux v3.15") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Simon Glass [Tue, 7 Nov 2023 09:17:40 +0000 (10:17 +0100)]
bootstage: Correct exhasuted typo
Correct this typo in the warning message shown when no more bootstage
records can be added.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 4 Nov 2023 19:57:33 +0000 (15:57 -0400)]
sandbox: Close file after mmaping it
After opening pathname, we must close ifd once we are done with it.
Fixes: b9274095c2c ("sandbox: Add a way to map a file into memory") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
CONFIG_DM_WARN has a text indicating that these messages should only
provided when debugging. This implies that the setting must be default no.
We should still create debug messages.
Reported-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 4 Nov 2023 16:25:24 +0000 (10:25 -0600)]
patman: Correct Python 3.6 behaviour
The importlib_resources import is not actually used. Fix this so that
patman can run on Python 3.6 to some extent, once
'pip3 install importlib-resources' has been run.
Simon Glass [Mon, 2 Oct 2023 01:14:37 +0000 (19:14 -0600)]
bootstd: Refactor mmc prep to allow a different scan
Adjust scan_mmc4_bootdev() and related function so that the caller can
do its own 'bootflow scan' command. This allows it to change the flags
if needed.
Simon Glass [Mon, 2 Oct 2023 01:14:36 +0000 (19:14 -0600)]
efi: Correct handling of frame buffer
The efi_gop driver uses private fields from the video uclass to obtain a
pointer to the frame buffer. Use the platform data instead.
Check the VIDEO_COPY setting to determine which frame buffer to use. Once
the next stage is running (and making use of U-Boot's EFI boot services)
U-Boot does not handle copying from priv->fb to the hardware framebuffer,
so we must allow EFI to write directly to the hardware framebuffer.
We could provide a function to read this, but it seems better to just
document how it works. The original change ignored an explicit comment
in the video.h file ("Things that are private to the uclass: don't use
these in the driver") which is why this was missed when the VIDEO_COPY
feature was added.
Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 8f661a5b662 ("efi_loader: gop: Expose fb when 32bpp") Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Patrice Chotard [Fri, 27 Oct 2023 14:43:04 +0000 (16:43 +0200)]
stm32mp2: initial support
Add initial support for STM32MP2 SoCs family.
SoCs information are available here :
https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html
Migrate all MP1 related code into stm32mp1/ directory
Create stm32mp2 directory dedicated for STM32MP2 SoCs.
Common code to MP1, MP13 and MP25 is kept into
arch/arm/mach-stm32/mach-stm32mp directory :
- boot_params.c
- bsec
- cmd_stm32key
- cmd_stm32prog
- dram_init.c
- syscon.c
- ecdsa_romapi.c
For STM32MP2, it also :
- adds memory region description needed for ARMv8 MMU.
- enables early data cache before relocation.
During the transition before/after relocation, the MMU, initially setup
at the beginning of DDR, must be setup again at a correct address after
relocation. This is done in enables_caches() by disabling cache, force
arch.tlb_fillptr to NULL which will force the MMU to be setup again but
with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been
updated after relocation in arm_reserve_mmu().
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrice Chotard [Fri, 27 Oct 2023 14:43:03 +0000 (16:43 +0200)]
ARM: dts: stm32: Add STM32MP257F Evaluation board support
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC,
with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC,
SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
Sync device tree with kernel v6.6-rc1.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
When building with AARCH64 defconfig, we got warnings for debug
message
- format '%x' expects argument of type 'unsigned int',
but argument 3 has type 'size_t' {aka 'long unsigned int'}).
- format '%lx' expects argument of type 'long unsigned int',
but argument 2 has type 'phys_addr_t' {aka 'long long unsigned
int'}
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrice Chotard [Fri, 27 Oct 2023 14:42:56 +0000 (16:42 +0200)]
arm: caches: Make DCACHE_DEFAULT_OPTION accessible for ARM64 arch
This fixes the following compilation error in ARM64:
arch/arm/mach-stm32mp/dram_init.c: In function ‘board_get_usable_ram_top’:
arch/arm/mach-stm32mp/dram_init.c:59:45: error: ‘DCACHE_DEFAULT_OPTION’ undeclared (first use in this function)
59 | mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
| ^~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Sam Protsenko [Tue, 7 Nov 2023 21:22:00 +0000 (15:22 -0600)]
clk: exynos: Add header guard for clk-pll.h
The clk-pll.h is going to be included in multiple files soon. Add
missing header guard to prevent possible build errors in future.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Fixes: 166097e87753 ("clk: exynos: add clock driver for Exynos7420 Soc") Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
clk_get_by_index() returns negative number on error. Assigning it to
unsigned int makes the subsequent "ret < 0" check always false, leading
in turn to possible unhandled errors. Change 'ret' variable type to
signed int so the code checks and handles clk_get_by_index() return code
properly.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Fixes: cf75cdf96ef2 ("serial: s5p: use clock api to get clock rate") Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Mon, 30 Oct 2023 16:55:02 +0000 (11:55 -0500)]
exynos: Avoid duplicate reset_cpu with SYSRESET enabled
The sysreset uclass unconditionally provides a definition of the
reset_cpu() function. So does the exynos soc code. Fix the build with
SYSRESET enabled by omitting the function from the soc code in that
case. The code still needs to be kept around for use in SPL.
This commit was inspired by commit 6e19dc84c14b ("sunxi: Avoid duplicate
reset_cpu with SYSRESET enabled").
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Fri, 20 Oct 2023 21:46:33 +0000 (16:46 -0500)]
watchdog: s5p_wdt: Include missing CPU header
s5p watchdog driver calls samsung_get_base_watchdog() function, but its
prototype is not included. That might lead to build warnings like this:
drivers/watchdog/s5p_wdt.c: In function 'wdt_stop':
drivers/watchdog/s5p_wdt.c:16:26:
warning: implicit declaration of function
'samsung_get_base_watchdog' [-Wimplicit-function-declaration]
16 | (struct s5p_watchdog *)samsung_get_base_watchdog();
| ^~~~~~~~~~~~~~~~~~~~~~~~~
Include asm/arch/cpu.h to fix that issue.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Fri, 20 Oct 2023 21:46:32 +0000 (16:46 -0500)]
arm: exynos: Include missing CPU header in gpio.h
arch/arm/include/asm/arch/gpio.h relies on definitions from cpu.h.
Include it explicitly in gpio.h. Otherwise next build error may occur:
In file included from ./arch/arm/include/asm/gpio.h:7,
from include/cros_ec.h:14,
from board/samsung/common/board.c:8:
./arch/arm/include/asm/arch/gpio.h:1357:4:
error: 'EXYNOS4_GPIO_PART1_BASE' undeclared here
(not in a function); did you mean 'EXYNOS4_GPIO_MAX_PORT'?
1357 | { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
| ^~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Marek Vasut [Sun, 5 Nov 2023 22:42:45 +0000 (23:42 +0100)]
mmc: renesas-sdhi: Disable clock after tuning reset when possible
Currently the renesas_sdhi_reset_tuning() unconditionally leaves SDHI
clock enabled after the tuning reset. This is not always necessary.
After the driver performed tuning reset at the end of probe function,
or in the unlikely case that tuning failed during regular operation,
the SDHI clock can be disabled after the tuning reset. The following
set_ios call would reconfigure the clock as needed.
In case of regular set_ios call which requires a tuning reset, keep
the clock enabled or disabled according to the mmc->clk_disable state.
With this in place, the controllers which have not been accessed via
block subsystem after boot are left in quiescent state. However, if an
MMC device is used e.g. for environment storage, that controller would
be accessed during the environment load and left active, including its
clock which would still be generated. This is due to the design of the
MMC subsystem, which does not deinit a controller after it was started
once, the controller is only deinited in case of mmc rescan, or before
OS boot.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> Tested-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Thuan Nguyen Hong <thuan.nguyen-hong@banvien.com.vn>
Tom Rini [Sun, 12 Nov 2023 21:36:22 +0000 (16:36 -0500)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
To quote Andre:
The first few patches are some easy refactorings and fixes, most of them
actually don't change the generated binaries at all. Then there is a
defconfig for a new board, for which we just gained the .dts file from
the last kernel DT sync.
On top there is support for a new PMIC (AXP313), and LPDDR4 support for
the Allwinner H616 SoC, both of which are needed to support new devices
that appeared lately, especially cheap TV boxes.
While those are technically new features, they don't affect existing
boards, for instance the LPDDR4 support code is guarded by a new DRAM
type Kconfig variable. So the risk for regressions is very slim.
Gitlab CI passed, and I booted that briefly on some boards, including an
H616 and an H618 one (with LPDDR4).
The H616 SoC family has support for several types of DRAM: DDR3,
LPDDR3, DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 and LPDDR3 memory.
Let's extend the driver to support the LPDDR4 memory. This type
of memory widely used in device with T507(-H) SoC and new orangepi
zero3 with H618.
The compatibility with T507 is not yet complete, because there
is difference in the phy_init array.
The LPDDR4-2133 timings correspond to DRAM Rayson RS1G32LO4D2BDS-53BT
found on the NOR SPI from the Orangepi Zero 3 4GB.
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Tested-by: Piotr Oniszczuk <piotr.oniszczuk@gmail.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com>
The original H616 DDR3 ODT configuration code wrote board specific values
into a sequence of paired registers.
For LPDDR3 support we needed to special-case one group of registers,
because for that DRAM type we need to write 0 into the lower register of
each pair. That already made the code less readable.
LPDDR4 support will make things even messier, so let's refactor that
code now: We allow to write different values into the lower and upper
half of each pair. The masking is moved into a macro, and use in each
write statement.
The effect is not as obvious yet, as we don't need the full flexibility at
the moment, but the motivation will become clearer with LPDDR4 support.
Andre Przywara [Sun, 30 Jul 2023 00:11:01 +0000 (01:11 +0100)]
power: pmic: sunxi: add AXP313 SPL driver
On boards using the AXP313 PMIC, the DRAM rail is often not setup
correctly at reset time, so we have to program the PMIC very early in
the SPL, before running the DRAM initialisation.
Add a simple AXP313 PMIC driver that knows about DCDC2(CPU) and
DCDC3(DRAM), so that we can bump up the voltage before the DRAM init.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Samuel Holland [Tue, 31 Oct 2023 04:57:40 +0000 (23:57 -0500)]
pinctrl: sunxi: Avoid using .bss for SPL
sunxi platforms put .bss in DRAM, so .bss is not available in SPL before
DRAM controller initialization. Therefore, this buffer must be placed in
the .data section.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Tue, 31 Oct 2023 05:22:35 +0000 (00:22 -0500)]
sunxi: mmc: Move header to the driver directory
The MMC controller driver is (and ought to be) the only user of these
register definitions. Put them in a header next to the driver to remove
the dependency on a specific ARM platform's headers.
Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
the register definitions were changed.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tom Rini [Mon, 17 Jul 2023 19:29:20 +0000 (15:29 -0400)]
arm: sunxi: Correct warning in board_fit_config_name_match
When building this with clang, we get a warning about having excess
parenthesis here, or that we're incorrectly using "==" when we want "=".
Correct these by using the common size macro.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
[Andre: Use SZ_512M as per Simon's suggestion] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 27 Jun 2021 00:13:09 +0000 (01:13 +0100)]
sunxi: board: simplify early PMIC setup conditions
So far we have a convoluted #ifdef mesh that guards the early AXP PMIC
setup in board.c. That combination of &&, || and negations is very hard
to read, maintain and especially to extend.
Fortunately we have those same conditions already modelled in the
Kconfig file, so they are actually redundant. On top of that the real
reason we have those preprocessor guards in the first place is about the
symbols that are *conditionally* defined: without #ifdefs the build
would break because of them being undefined for many boards.
To simplify this, just change the guards to actually look at the symbols
needed, so CONFIG_AXP_xxx_VOLT instead of CONFIG_AXPyyy_POWER.
This drastically improves the readability of this code, and makes adding
PMIC support a pure Kconfig matter.
Doing this revealed one bug in Kconfig: there is no axp_set_dcdc4() for
the AXP818, even though CONFIG_AXP_DCDC4_VOLT includes that PMIC.
Since the AXP818 wasn't included when calling axp_set_dcdc4() in board.c,
this wasn't an issue, but becomes one now, so also remove the AXP818 from
the DCDC4 Kconfig symbol.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Milan P. Stanić [Sat, 4 Nov 2023 14:38:15 +0000 (15:38 +0100)]
doc: build: fix wrongly written targests instead of targets
Signed-off-by: Milan P. Stanić <mps@arvanta.net> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Nishanth Menon [Wed, 1 Nov 2023 14:50:25 +0000 (09:50 -0500)]
doc: ti: j7200_evm: Fix OPTEE platform name
k3-j7200 does not exist in upstream OPTEE. Use j721e as the platform
name. Using k3-j7200 as OPTEE name results in broken boot due to wrong
configuration being picked.
Dylan Corrales [Sat, 28 Oct 2023 09:46:39 +0000 (05:46 -0400)]
hikey960: Fix 404 links
The build instructions for the hikey960 had some broken links. Update
the links to use new vendor URLs. Also change build instructions to
reference a different file name.
Tom Rini [Fri, 10 Nov 2023 20:25:47 +0000 (15:25 -0500)]
Merge patch series "arm: dts: k3-am6: Fix Ethernet/DMA"
To quote the author:
Since commit [1], Ethernet is broken on TI AM62 and AM64 platforms.
The commit [1] is not the culprit. It just unearths the problem by fixing
the error check in k3-udma.c. This issue was silently being ignored earlier
due to wrong error check. [NULL instead of FDT_ADDR_T_NONE].
Fix the issue by adding the necessary register spaces for the u-boot K3-UDMA
driver for AM62 and AM64 platforms.
These properties will eventually make it into the SoC DTSi files [2] after
which these can be dropped from k3-*-u-boot.dtsi files.
[1] - 5fecea171de3dd ("treewide: use dev_read_addr_*_ptr() where appropriate")
[2] - https://lore.kernel.org/linux-arm-kernel/20230810174356.3322583-1-vigneshr@ti.com/
projects / thirdparty / u-boot.git / log
