Pali Rohár [Sun, 22 Jan 2023 00:25:12 +0000 (01:25 +0100)]
cmd: mvebu/bubt: Add support for writing image to SATA disk
All 32-bit Armada SoCs and also 64-bit Armada 3720 SoC can load and boot
firmware from SATA disk. This adds support for updating firmware binary for
these SoCs. On 32-bit Armada SoC is firmware stored at sector 1 and on
Armada 3720 is stored at MBR partition 0x4d or GPT partition with type GUID 6828311A-BA55-42A4-BCDE-A89BB5EDECAE (Marvell Armada 3700 Boot partition).
Pali Rohár [Sat, 21 Jan 2023 21:58:28 +0000 (22:58 +0100)]
cmd: mvebu/bubt: Add support for selecting eMMC HW partition
Support for burning into the correct eMMC HW boot partition was broken and
removed in commit 96be2f072768 ("mvebu: bubt: Drop dead code"). Reimplement
this functionality and bring it back again.
Fixes: 96be2f072768 ("mvebu: bubt: Drop dead code") Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Tue, 10 Jan 2023 21:33:56 +0000 (22:33 +0100)]
tools: kwboot: Show image type and error parsing reasons
Show image type and version during parsing of kwbimage.
And show reasons in error messages when parsing failed.
This can help to debug issues with invalid images.
Pali Rohár [Sat, 21 Jan 2023 11:59:20 +0000 (12:59 +0100)]
tools: kwboot: Fix patching of SPI/NOR XIP images
Marvell BootROM interprets execaddr of SPI/NOR XIP images as relative byte
offset from the from the beginning of the flash device. So if data image
offset and execute offset are not same then it is needed to adjust them
also in DDR RAM.
Fixes: f2c644e0b8bc ("tools: kwboot: Patch destination address to DDR area for SPI image") Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Sun, 8 Jan 2023 12:46:14 +0000 (13:46 +0100)]
tools: kwboot: Add check that kwbimage contains DDR init code
Some NOR images may be execute-in-place and do not contain DDR init code in
its kwbimage header. Such images cannot be booted over UART as BootROM
loads them to RAM. Add check that kwbimage contains DDR init code in its
header (either as binary code header or as the simple register-value set).
In some cases it is possible to load very small image into L2SRAM and when
DDR init code is not required. So check for L2SRAM load address and skip
DDR init code check in this case.
Pali Rohár [Sun, 8 Jan 2023 12:38:27 +0000 (13:38 +0100)]
tools: kwboot: Fix parsing UART image without data checksum
The 32-bit data checksum in UART image is not checked by the BootROM and
also Marvell tools do not generate it.
So if data checksum stored in UART image does not match calculated checksum
from the image then treat those checksum bytes as part of the executable
image code (and not as the checksum) and for compatibility with the rest of
the code manually insert data checksum into the in-memory image after the
executable code, without overwriting it.
This should allow to boot UART images generated by Marvell tools.
Pali Rohár [Sat, 21 Jan 2023 18:57:28 +0000 (19:57 +0100)]
tools: kwboot: Add image type documentation
Add information of all available image types and where they should be
stored. Storage location offsets where documented from the disassembly of
the A385 BootROM image dump.
Pali Rohár [Sun, 8 Jan 2023 12:34:24 +0000 (13:34 +0100)]
tools: kwboot: Add more documentation references
Add reference to Avanta Boot Flow documentation, BobCat2, AlleyCat3 and
PONCat3 BootROM Firmware documentation and links to public Marvell tools:
hdrparser.c and doimage.c
Pali Rohár [Sun, 8 Jan 2023 23:52:09 +0000 (00:52 +0100)]
arm: mvebu: spl: Fix support for loading U-Boot proper from SD card
Marvell BootROM loads MMC image from sector 0 (HW boot or data partition)
and SD image from sector 1.
So for SD card booting it is needed to not use constant CONFIG MMC options
and instead of them it is needed to define functions spl_mmc_boot_mode()
spl_mmc_get_uboot_raw_sector() which determinate offsets at SPL runtime
based on MMC or SD card.
Calculation of SD card sector expects following values:
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header") Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Sat, 21 Jan 2023 14:13:08 +0000 (15:13 +0100)]
spl: mmc: Allow to disable SYS_MMCSD_FS_BOOT_PARTITION
On some platforms is SYS_MMCSD_FS_BOOT_PARTITION unsupported. So allow to
completely disable MMC FS Boot support via new option SYS_MMCSD_FS_BOOT.
By default MMC FS Boot support is enabled (like it was before) except for
ARCH_MVEBU where MMC FS Boot supported is unsupported due to Marvell
BootROM limitations.
When eMMC boot is selected then BootROM loads kwbimage header (U-Boot SPL)
from the selected eMMC boot partition. So for eMMC boot ensure that U-Boot
SPL loads U-Boot proper (from kwbimage) also from the same selected eMMC
boot partition.
Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header") Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Sun, 8 Jan 2023 12:27:07 +0000 (13:27 +0100)]
arm: mvebu: spl: Remove checks for BOOT_DEVICE_MMC2 and BOOT_DEVICE_MMC2_2
BOOT_DEVICE_MMC2 and BOOT_DEVICE_MMC2_2 are representing mmc dev 1 but all
Armada SoCs have only one mmc controller. So remove references to
non-existent second mmc controller.
Pali Rohár [Sat, 21 Jan 2023 12:59:20 +0000 (13:59 +0100)]
cmd: mvebu/bubt: Fix parsing SATA kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SATA image as number of sectors the beginning of the hard
drive, but as number of sectors relative to the main header.
Reject invalid and accept valid SATA images.
Fixes: 5a0653493307 ("cmd: mvebu/bubt: Check for A38x image data checksum") Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Sat, 21 Jan 2023 12:47:45 +0000 (13:47 +0100)]
arm: mvebu: spl: Fix parsing SATA kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SATA image as number of sectors the beginning of the hard
drive, but as number of sectors relative to the main header.
To process SATA kwbimage and load U-Boot proper from it in the same way as
Marvell BootROM, it is needed to interpret srcaddr as relative offset to
the main header. This change fixes booting of U-Boot proper from SPL code
in SATA image.
Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header") Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Sat, 21 Jan 2023 12:45:36 +0000 (13:45 +0100)]
tools: kwboot: Fix parsing SATA kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SATA image as number of sectors the beginning of the hard
drive, but as number of sectors relative to the main header.
To parse SATA kwbimage in the same way as Marvell BootROM, it is needed to
interpret srcaddr as relative offset to the main header. This change fixes
loading of SATA images via kwboot over UART.
Pali Rohár [Sat, 21 Jan 2023 12:34:55 +0000 (13:34 +0100)]
tools: kwbimage: Fix generating, verifying and extracting SATA kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SATA image as number of sectors the beginning of the hard
drive, but as number of sectors relative to the main header.
The main header is stored at absolute sector number 1. So do not add or
subtract it when calculating with relative offsets to the main header.
Fixes: 501a54a29cc2 ("tools: kwbimage: Fix generation of SATA, SDIO and PCIe images") Fixes: 5c61710c9880 ("tools: kwbimage: Properly set srcaddr in kwbimage v0") Fixes: e0c243c398a7 ("tools: kwbimage: Validate data checksum of v1 images") Fixes: aa6943ca3122 ("kwbimage: Add support for extracting images via dumpimage tool") Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Sun, 8 Jan 2023 12:18:39 +0000 (13:18 +0100)]
cmd: mvebu/bubt: Fix parsing SDIO kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SDIO image as offset in number of sectors (like for SATA
image), but as offset in bytes (like for all other images except SATA).
To ensure that we do not store invalid SDIO image to the boot location
(read by the Marvell BootROM), we need to check that image is valid
and srcaddr is intepreted in bytes, in the same way as it is done by
Marvell BootROM.
This fixes rejecting valid and accepting invalid SDIO images by bubt command.
Fixes: 5a0653493307 ("cmd: mvebu/bubt: Check for A38x image data checksum") Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Sun, 8 Jan 2023 12:16:38 +0000 (13:16 +0100)]
arm: mvebu: spl: Fix parsing SDIO kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SDIO image as offset in number of sectors (like for SATA
image), but as offset in bytes (like for all other images except SATA).
To process SDIO kwbimage and load U-Boot proper from it in the same way as
Marvell BootROM, it is needed to interpret srcaddr in bytes. This change
fixes booting of U-Boot proper from SPL code stored in SDIO image.
Fixes: 2226ca173486 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header") Signed-off-by: Pali Rohár <pali@kernel.org>
Pali Rohár [Sun, 8 Jan 2023 12:20:20 +0000 (13:20 +0100)]
tools: kwboot: Fix parsing SDIO kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SDIO image as offset in number of sectors (like for SATA
image), but as offset in bytes (like for all other images except SATA).
To parse SDIO kwbimage in the same way as Marvell BootROM, it is needed to
interpret srcaddr in bytes. This change fixes loading of SDIO images via
kwboot over UART.
Pali Rohár [Sun, 8 Jan 2023 12:22:03 +0000 (13:22 +0100)]
tools: kwbimage: Fix generating, verifying and extracting SDIO kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SDIO image as offset in number of sectors (like for SATA
image), but as offset in bytes (like for all other images except SATA).
To generate SDIO kwbimage compatible with Marvell BootROM, it is needed to
have srcaddr in bytes. This change fixes SDIO images for Armada 38x SoCs.
Fixes: 501a54a29cc2 ("tools: kwbimage: Fix generation of SATA, SDIO and PCIe images") Fixes: 5c61710c9880 ("tools: kwbimage: Properly set srcaddr in kwbimage v0") Fixes: e0c243c398a7 ("tools: kwbimage: Validate data checksum of v1 images") Fixes: aa6943ca3122 ("kwbimage: Add support for extracting images via dumpimage tool") Signed-off-by: Pali Rohár <pali@kernel.org>
Tom Rini [Wed, 1 Mar 2023 01:24:25 +0000 (20:24 -0500)]
Merge tag 'u-boot-rockchip-20230228' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
Please pull the updates for rockchip platform:
- Add support for rk3588 soc;
- Add rk3588 Edgeble Neu6 board and Radxa ROCK5B board;
- Add rk3308 Radxa ROCK Pi S board;
- Add rk3568 Radxa ROCK 3 board,
- Add rk3566 Radxa Compute Module 3 board;
- Add support for sdram reg info version 3
- Refactor rockchip OTP/eFuse driver and add more soc support;
- Add external TPL support for binman;
binman support for mkimage ignore missing entry is based on [1];
Tom Rini [Tue, 28 Feb 2023 14:50:16 +0000 (09:50 -0500)]
Merge tag 'tpm-next-28022023' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next
TPM auto startup and testing:
Due to U-Boot's lazy binding we always relied on command line tools to
initialize the TPM subsystem and devices. One exception is the EFI
subsystem. When compiled with TCG2 measured boot support the TPM was
automatically initialized.
However that init was not complete. The TCG specs [0] (and specifically
§12.3 Self-test modes) describe how self-tests on the device should be
performed. This PR is adding an extra API function, that can be used to
initialize the TPM2.0 properly.
Simon added the equivalent for TPM1.2 and refactored the DM tests to
include the new funtion.
- mark reserved blocks from Ashok Reddy Soma
- backport BRCMNAND changes from Linux from Linus Walleij
- fix display of unknown raw ID from Patrice Chotard
- show reserved block in chip.erase from Michael Trimarchi
Eugen Hristev [Wed, 22 Feb 2023 09:05:12 +0000 (11:05 +0200)]
board: rockchip: add Radxa ROCK5B Rk3588 board
ROCK 5B is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa.
There are tree variants depending on the DRAM size : 4G, 8G and 16G.
Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
MIPI CSI 2 multiple lanes connector
eMMC module connector
uSD slot (up to 128GB)
2x USB 2.0, 2x USB 3.0
2x HDMI output, 1x HDMI input
Ethernet port
40-pin IO header including UART, SPI, I2C and 5V DC power in
USB PD over USB Type-C
Size: 85mm x 54mm
Kernel commits: a1d3281450ab ("arm64: dts: rockchip: Add rock-5b board") 6fb13f888f2a ("arm64: dts: rockchip: Update sdhci alias for rock-5b")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmc
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568
will return error in this case. Apparently, SDHCI silently ignores the
error and as a result eMMC initialization fails.
Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Booting from SDMMC is one of the fast and easy booting methods
for initial support of any SoC to upstream more features.
This patch is trying to add the sdmmc node for rk3588 and added
as u-boot specific node in -u-boot.dtsi as upstream Linux is not
supporting yet.
As soon as Linux supports it, a sync of the Linux device tree
would eventually drop this node.
Clock properties as added according to the rockchip mmc driver
but the actual definition might add scmi clocks into 0 and 1
indexes. This is due to scmi clock are not supporting in upstream
U-Boot. Properly addition of scmi clock would eventually follow
sdmmc clock definition of Linux once they upstreamed.
Jagan Teki [Mon, 30 Jan 2023 14:57:45 +0000 (20:27 +0530)]
arm: rockchip: Add RK3588 arch core support
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76
and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU,
Mali-G610 MP4, HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2,
LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0,
PCIe 3.0, SATA 3, Ethernet, SDIO3.0 I2C, UART, SPI, GPIO and PWM.
Add arch core support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:42 +0000 (20:27 +0530)]
arm64: dts: rockchip: Add base DT for rk3588 SoC
This initial version supports CPU, dma, interrupts, timers, UART and
SDHCI (everything necessary to boot Linux on this system on chip) as
well as Ethernet, I2C, PWM and SPI.
The DT is split into rk3588 and rk3588s, which is a reduced version
(i.e. with less peripherals) of the former.
Jagan Teki [Mon, 30 Jan 2023 14:57:41 +0000 (20:27 +0530)]
arm: rockchip: Add ioc header for rk3588
Add IOC unit header include for rk3588.
Signed-off-by: Steven Liu <steven.liu@rock-chips.com> Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:38 +0000 (20:27 +0530)]
ram: rockchip: Add rk3588 ddr driver support
Add ddr driver for rk3588 to get the ram capacity.
Co-developed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 13 Feb 2023 22:27:39 +0000 (16:27 -0600)]
rockchip: rk3568: enable automatic power savings
It enables automatic clock gating on idle, disables the eDP phy by
default, and sets the core pvtpll ring length. It is reported this
lowers the temperature on at least one SoC by 7C.
Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 13 Feb 2023 22:27:38 +0000 (16:27 -0600)]
rockchip: rk3568: add boot device detection
Enable spl to detect which device it was booted from.
Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 13 Feb 2023 22:27:35 +0000 (16:27 -0600)]
dts: rockchip: px30: add gpio-ranges property to gpio nodes
Add the gpio-ranges property to each GPIO node for use in deriving
the correct bank ID. Note that invoking "gpio status -a" no longer
causes the board to hit a "Synchronous Abort".
Fixes: 537b1a277479 ("rockchip: add px30 devicetrees") Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 13 Feb 2023 22:27:34 +0000 (16:27 -0600)]
gpio: gpio-rockchip: parse gpio-ranges for bank id
Use the new devicetree property of gpio-ranges to determine the GPIO
bank ID. Preserve the "old" way of doing things too, so that boards
can be migrated and tested gradually (I only have a 3566 and 3326 to
test).
Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Manoj Sai [Fri, 17 Feb 2023 11:58:45 +0000 (17:28 +0530)]
rk3566: radxa-cm3: Enable USB2.0, USB3.0 support
=> usb start
starting USB...
Bus usb@fd000000: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@fd800000: USB EHCI 1.00
scanning bus usb@fd000000 for devices... cannot reset port 1!?
2 USB Device(s) found
scanning bus usb@fd800000 for devices... 4 USB Device(s) found
scanning usb for storage devices... 2 Storage Device(s) found
=> usb tree
USB device tree:
1 Hub (5 Gb/s, 0mA)
| U-Boot XHCI Host Controller
|
+-2 Mass Storage (5 Gb/s, 224mA)
SanDisk Dual Drive 04019c9b2e1a58f24ee318c3c123aa5
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Hub (480 Mb/s, 100mA)
| USB 2.0 Hub
|
+-3 Mass Storage (480 Mb/s, 500mA)
| JetFlash Mass Storage Device 19M7I4ZQFTSC08SU
|
+-4 Human Interface (12 Mb/s, 98mA)
Logitech USB Receiver
Co-developed-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Fri, 17 Feb 2023 11:58:41 +0000 (17:28 +0530)]
drivers: phy: add naneng combphy for rk3568
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram
of the complex connection.
Manoj Sai [Fri, 17 Feb 2023 11:58:40 +0000 (17:28 +0530)]
phy: rockchip-inno-usb2: Add USB2 PHY for rk3568
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port
of PHY0 support OTG mode with charging detection function, they are
similar to previous Rockchip SoCs.
However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.
This patch only PHY1 with necessary attributes required to function
USBPHY1 on U-Boot.
Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com> Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Co-developed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Fri, 17 Feb 2023 11:58:39 +0000 (17:28 +0530)]
phy: rockchip: inno-usb2: Add support #address_cells = 2
New Rockchip devices have the usb phy nodes as standalone devices.
These nodes have register nodes with #address_cells = 2, but only
use 32 bit addresses.
Adjust the driver to check if the returned address is "0", and adjust
the index in that case.
Derived and adjusted the similar change from linux-next with below
commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support
#address_cells = 2")
Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Radxa Compute Module 3(CM3) is one of the modules from a series
System On Module based on the Radxa ROCK 3 series and is compatible
with Raspberry Pi CM4 pinout and form factor.
Specification:
- Rockchip RK3566
- up to 8GB LPDDR4
- up to 128GB high performance eMMC
- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless,
BT 5.0, BLE with onboard and external antenna.
- Gigabit Ethernet PHY
Radxa CM3 needs to mount on top of this IO board in order to create
complete Radxa CM3 IO board platform.
Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is
possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board.
linux-next commit for the same,
commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa
CM3")
Add support for Radxa CM3.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Co-developed-by: FUKAUMI Naoki <naoki@radxa.com> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
include: rk3328: Add default env for compressed kernel images
Add default memory addresses for kernel_comp_addr_r and kernel_comp_size
to enable booting from a compressed kernel image. This area is temporarily
used to decompress the kernel image on-the-fly.
Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Akash Gajjar [Tue, 14 Feb 2023 15:31:09 +0000 (21:01 +0530)]
arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S support
Add Radxa ROCK 3 Model A support. sync rk3308-rock-pi-s.dts from
Linux 6.2.0-rc7.
ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a,
- 256MB/512MB DDR3 RAM
- SD, NAND flash (optional on board 1/2/4/8Gb)
- 100MB ethernet, PoE (optional)
- Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module
- USB2.0 Type-A HOST x1
- USB3.0 Type-C OTG x1
- 26-pin expansion header
- USB Type-C DC 5V Power Supply
Linux commit commit for the same,
<2e04c25b1320> ("arm64: dts: rockchip: add ROCK Pi S DTS support")
Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 25 Feb 2023 19:01:35 +0000 (19:01 +0000)]
binman: Mark mkimage entry missing when its subnodes is missing
Using the mkimage entry with the multiple-data-files prop and having a
missing external blob result in an unexpected ValueError exception using
the --allow-missing flag.
ValueError: Filename 'missing.bin' not found in input path (...)
Fix this by using _pathname that is resolved by ObtainContents for blob
entries, ObtainContents also handles allow missing for external blobs.
Mark mkimage entry as missing and return without running mkimage when
missing entries is reported by CheckMissing.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 25 Feb 2023 19:01:34 +0000 (19:01 +0000)]
rockchip: Use an external TPL binary on RK3568
Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps
back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then
jumps to U-Boot SPL to continue the normal boot flow.
However, there is no support to initialize DRAM on RK35xx SoCs using
U-Boot TPL and instead an external TPL binary must be used to generate a
bootable u-boot-rockchip.bin image.
Add CONFIG_ROCKCHIP_EXTERNAL_TPL to indicate that an external TPL should
be used. Build U-Boot with ROCKCHIP_TPL=/path/to/ddr.bin to generate a
bootable u-boot-rockchip.bin image for RK3568.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
Jonas Karlman [Sat, 25 Feb 2023 19:01:33 +0000 (19:01 +0000)]
binman: Add support for a rockchip-tpl entry
The rockchip-tpl entry can be used when an external TPL binary should be
used instead of the normal U-Boot TPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
Jonas Karlman [Fri, 10 Feb 2023 18:30:05 +0000 (18:30 +0000)]
rockchip: dts: rk3328: fix sdram params
The rk3328 sdram driver read sdram parameters from the devicetree into a
struct rk3328_sdram_params using dev_read_u32_array.
After commit 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30")
changed the size of struct ddr_pctl_regs, a member of struct
rk3328_sdram_params, U-Boot TPL can no longer initialize DRAM on RK3328.
Add ten u32 to the sdram parameter array in devicetree to align with
this size change. This fixes DRAM initialization on RK3328.
Fixes: 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3328-cc
Jonas Karlman [Tue, 7 Feb 2023 17:27:11 +0000 (17:27 +0000)]
rockchip: sdram: add dram bank with usable memory beyond 4GB
Add a second dram bank of usable memory beyond the blob of space for
peripheral near 4GB. Any memory that exists beyond the 4GB mark is added
to the second bank.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 7 Feb 2023 17:27:10 +0000 (17:27 +0000)]
rockchip: sdram: add basic support for sdram reg info version 3
Newer DRAM initialization blobs from vendor can encode sdram info in a
new version 3 format. The new format makes use of more bits in sys_reg3
compared to the version 2 format.
Add basic support for detecting the version 3 format and decoding the
high bits used for ddrtype.
This fixes decode of sdram size on my RK3568 boards that have LPDDR4X.
Details on the new format was deciphered from vendor u-boot commit [1].
Quentin Schulz [Tue, 17 Jan 2023 17:26:54 +0000 (18:26 +0100)]
rockchip: ringneck: fix SDRAM init fail
CONFIG_RAM_PX30_DDR4 got renamed to CONFIG_RAM_ROCKCHIP_DDR4 in commit 26f92be07e2a ("ram: rockchip: Add common ddr type configs"). Since both
patchsets were merged unbeknownst to the other, the conflict wasn't
detected while testing each patchset individually and could only be
observed after a merge to master branch.
Fixes: c925be73a0a8 ("rockchip: add support for PX30 Ringneck SoM on Haikou Devkit") Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The CLKDIV register should always be programmed with a value
higher than zero (0); that is, a clock divider should always be
used for 8-bit DDR mode.
In Linux, the driver applies this logic for all SoCs using the driver
and does not distinguish RK3288, so presumably this requirement is the
same for all other Rockchip SoCs using this IP.
Add the necessary code to double the clock frequency when 8-bit DDR is
selected. The dw_mmc core already handles setting CLKDIV correctly
given the input clock and desired bus clock.
Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Mihai Sain [Thu, 23 Feb 2023 09:12:58 +0000 (11:12 +0200)]
ARM: dts: at91: sama7g5: fix clock id for ebi node
The PMC_MCK1 clock id for the ebi node is 23.
Fixes: 746b738224ad ("ARM: dts: at91: sama7g5/sama7g5ek: align with Linux DT") Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Simon Glass [Tue, 21 Feb 2023 13:24:51 +0000 (06:24 -0700)]
tpm: Separate out the TPM tests for v1 and v2
Currently there is only one test and it only works on TPM v2. Update it
to work on v1.2 as well, using a new function to pick up the required
TPM.
Update sandbox to include both a v1.2 and v2 TPM so that this works.
Split out the existing test into two pieces, one for init and one for
the v2-only report_state feature.
Ilias Apalodimas [Sat, 18 Feb 2023 15:18:49 +0000 (17:18 +0200)]
tpm: sandbox: Change the return code when device is already open
All the TPM drivers as well as out TCG TIS API for a TPM2.0 device
return -EBUSY if the device has already been opened. Adjust
the sandbox TPM do return the same error code.
Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Ilias Apalodimas [Wed, 25 Jan 2023 11:06:03 +0000 (13:06 +0200)]
efi_loader: use tpm_auto_start for the tpm device
A previous commit is adding a new tpm startup functions which
initializes the TPMv2 and performs all the needed selftests.
Since the TPM selftests might be needed depending on the requested
algorithm or functional module use that instead.
Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Ilias Apalodimas [Wed, 25 Jan 2023 10:18:36 +0000 (12:18 +0200)]
tpm: add a function that performs selftest + startup
As described in [0] if a command requires use of an untested algorithm
or functional module, the TPM performs the test and then completes the
command actions.
Since we don't check for TPM_RC_NEEDS_TEST (which is the return code of
the TPM in that case) and even if we would, it would complicate our TPM
code for no apparent reason, add a wrapper function that performs both
the selftest and the startup sequence of the TPM.
It's worth noting that this is implemented on TPMv2.0. The code for
1.2 would look similar, but I don't have a device available to test.
projects / thirdparty / u-boot.git / log
