Jonas Karlman [Mon, 21 Jul 2025 22:07:13 +0000 (22:07 +0000)]
phy: rockchip: naneng-combphy: Simplify init ops
The init ops for Rockchip COMBPHY driver is more complex than it needs
to be, e.g. declaring multiple init functions that only differ in the
error message.
Simplify the init ops based on code from the Linux mainline driver.
This change also ensure that errors returned from combphy_cfg() and
reset_deassert_bulk() is propertly propagated to the caller. No other
runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip COMBPHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:11 +0000 (22:07 +0000)]
phy: rockchip: usbdp: Simplify init ops
With working shared reference counting for Generic PHY ops there is no
need for the Rockchip USBDP PHY driver to keep its own status (reference
counting) handling.
Simplify the init ops now that shared reference counting is working.
This also removes the unused mode_change handling as part of the
simplication.
No runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip USBDP PHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
E.g. on a ROCK 5B following could be observed:
=> usb start
starting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> usb reset
resetting USB...
[...]
rockchip_udphy phy@fed90000: cmn ana lcpll lock timeout
rockchip_udphy phy@fed90000: failed to init usbdp combophy
rockchip_udphy phy@fed90000: PHY: Failed to init phy@fed90000: -110.
Can't init PHY1
Bus usb@fc400000: probe failed, error -110
scanning usb for storage devices... 0 Storage Device(s) found
With shared reference counting this is fixed:
=> usb reset
resetting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andrew Goodbody [Thu, 31 Jul 2025 11:46:10 +0000 (12:46 +0100)]
mmc: rockchip_sdhci: Do not test unsigned for being less than 0
In rockchip_sdhci_execute_tuning the variable tuning_loop_counter is
tested for being less than 0. Ensure that it is a signed type by
declaring it as s8 instead of char.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 13 Aug 2025 14:07:43 +0000 (16:07 +0200)]
power: rk8xx: allow to customize RK806 reset mode
The RK806 PMIC has a bitfield for configuring the restart/reset behavior
(which I assume Rockchip calls "function") whenever the PMIC is reset
either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL
or RESETB pins.
For RK806, the following values are possible for RST_FUN:
0b00 means "Restart PMU"
0b01 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode"
0b10 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode, and simultaneously
pull down the RESETB PIN for 5mS before releasing"
0b11 means the same as for 0b10 just above.
This adds the appropriate logic in the driver to parse the new
rockchip,reset-mode DT property to pass this information. It just
happens that the values in the binding match the values to write in the
bitfield so no mapping is necessary.
For backward compatibility reasons, if the property is missing we set it
to 0b10 (i.e. BIT(7)) like before this commit was merged instead of
leaving it untouched like in the kernel driver.
Note that this does nothing useful for U-Boot at the moment as the ways
to reset the device (e.g. via `reset` command) doesn't interact with the
RK8xx PMIC and simply does a CPU reset.
Considering the upstream Linux kernel left this register untouched until
(assumed) v6.17[1], this is useful for cases in which the U-Boot
bootloader has this patch (and running with a DT with
rockchip,reset-mode property set) and running an upstream kernel before
(assumed) v6.17, or alternatively later without the property in the
kernel DT.
Quentin Schulz [Wed, 13 Aug 2025 14:07:42 +0000 (16:07 +0200)]
arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger
The bootloader for RK3588 Tiger currently forces the PMIC reset behavior
(stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X
which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Quentin Schulz [Wed, 13 Aug 2025 14:07:41 +0000 (16:07 +0200)]
arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar
The bootloader for RK3588 Jaguar currently forces the PMIC reset
behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC)
to 0b1X which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Quentin Schulz [Wed, 13 Aug 2025 14:07:40 +0000 (16:07 +0200)]
arm64: dts: rockchip: add header for RK8XX PMIC constants
To make it easier to read the device tree, let's add constants for the
rockchip,reset-mode property values that are currently only applicable
to RK806 PMIC.
Quentin Schulz [Wed, 13 Aug 2025 14:07:39 +0000 (16:07 +0200)]
dt-bindings: mfd: rk806: Allow to customize PMIC reset mode
The RK806 PMIC allows to configure its reset/restart behavior whenever
the PMIC is reset either programmatically or via some external pins
(e.g. PWRCTRL or RESETB).
The following modes exist:
- 0; restart PMU,
- 1; reset all power off reset registers and force state to switch to
ACTIVE mode,
- 2; same as mode 1 and also pull RESETB pin down for 5ms,
For example, some hardware may require a full restart (mode 0) in order
to function properly as regulators are shortly interrupted in this mode.
This is the case for RK3588 Jaguar and RK3588 Tiger which have a
companion microcontroller running on an independent power supply and
monitoring the PMIC power rail to know the state of the main system.
When it detects a restart, it resets its own IPs exposed to the main
system as if to simulate its own reset. Failing to perform this fake
reset of the microcontroller may break things (e.g. watchdog not
automatically disabled, buzzer still running until manually disabled,
leftover configuration from previous main system state, etc...).
Some other systems may be depending on the power rails to not be
interrupted even for a small amount of time[1].
This allows to specify how the PMIC should perform on the hardware level
and may differ between hardware designs, so a DT property seems
warranted. I unfortunately do not see how this could be made generic
enough to make it a non-vendor property.
Jonas Karlman [Wed, 30 Jul 2025 23:52:45 +0000 (23:52 +0000)]
rockchip: rk3528: Disable USB3OTG U3 port early
The RK3528 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (COMBPHY).
Some board designs may not use the COMBPHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 port early and leave it to the
COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 30 Jul 2025 23:52:42 +0000 (23:52 +0000)]
rockchip: rk3528-generic: Fix boot after dts/upstream v6.16-dts merge
The rk3528-generic target can no longer boot after v6.16-dts was merged
into dts/upstream, and instead end up in a boot loop:
No serial driver found
resetting ...
After Linux commit 34d2730fbbdd ("arm64: dts: rockchip: move rk3528
i2c+uart aliases to board files") there is no longer an alias for
serial0 defined for the U-Boot only rk3528-generic device tree.
Add a board specific aliases node that include the missing serial0 alias
to resolve the boot issue and ensure that stdout-path = "serial0:..."
can be resolved by U-Boot.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Marius Dinu [Wed, 11 Jun 2025 11:04:54 +0000 (11:04 +0000)]
rk3288: add fdtoverlay_addr_r to default env
rk3288 is missing fdtoverlay_addr_r.
The new addresses match those used by rk3308.
Tested on Asus TinkerBoard S.
Signed-off-by: Marius Dinu <m95d+git@psihoexpert.ro> Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@vrull.eu> Cc: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Fri, 27 Jun 2025 13:30:19 +0000 (15:30 +0200)]
rockchip: puma-rk3399: enable "env erase" command
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 1 Aug 2025 20:43:39 +0000 (20:43 +0000)]
board: rockchip: Add ArmSoM Sige5
ArmSoM-Sige5 adopts the second-generation 8nm high-performance AIOT
platform Rockchip RK3576, with a 6 TOPS computing power NPU and support
for up to 16GB of large memory. It supports 4K video encoding and
decoding, offers rich interfaces including dual gigabit Ethernet ports,
WiFi 6 & BT5, and various video outputs.
Features tested on a ArmSoM Sige5 v1.1:
- SD-card boot
- eMMC boot
- Ethernet
- PCIe NVMe
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Frank Wang [Fri, 1 Aug 2025 20:32:44 +0000 (20:32 +0000)]
phy: rockchip: usbdp: Add support for RK3576
Add support for the USB3.0+DP PHY used in the RK3576 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Frank Wang [Fri, 1 Aug 2025 20:32:43 +0000 (20:32 +0000)]
phy: rockchip-inno-usb2: Add support for RK3576
Add support for the USB2.0 PHYs used in the RK3576 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 1 Aug 2025 20:32:41 +0000 (20:32 +0000)]
arm: dts: rockchip: Include OTP in U-Boot pre-reloc phase for RK3576
Update rk3576-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for
checkboard() to be able to read information about the running SoC model
and variant from OTP and print it during boot:
U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000)
Model: Generic RK3576
SoC: RK3576
DRAM: 8 GiB
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 1 Aug 2025 20:32:39 +0000 (20:32 +0000)]
board: rockchip: Add minimal generic RK3576 board
Add a minimal generic RK3576 board that only have eMMC, SDMMC and USB
OTG enabled. This defconfig can be used to boot from eMMC or SD-card on
most RK3576 boards that follow reference board design.
Da Xue [Tue, 10 Jun 2025 19:08:20 +0000 (19:08 +0000)]
arm64: dts: rockchip: roc-3328-cc: use 1600 ddr4 timing
Swap the ROC-3328-CC from DDR4 666 to 1600 timing to boost performance.
Signed-off-by: Da Xue <da@libre.computer> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Da Xue [Tue, 10 Jun 2025 19:08:19 +0000 (19:08 +0000)]
ram: rk3328: add ddr4-1600 sdram timing
Add DDR4 1600MHz SDRAM timing data from LibreComputer u-boot sources
for the ROC-3328-CC board.
Signed-off-by: Da Xue <da@libre.computer> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The information is read from the OTP and also the DDR_GRF. There's no
public information as far as I know about the layout and stored
information on OTP but this was provided by Rockchip themselves through
their support channel.
The OTP stores the information of whether the SoC is PX30K or something
else. To differentiate between PX30/RK3326 and PX30S/RK3326S, one needs
to read some undocumented bitfield in a DDR_GRF register as done in
vendor kernel,
c.f. https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr5.1/drivers/soc/rockchip/rockchip-cpuinfo.c#L118-L133.
I do not own a PX30S, nor RK3326/RK3326S so cannot test it works
properly.
Also add the OTP node to the pre-relocation phase of U-Boot proper so
that the SoC variant can be printed when DISPLAY_BOARDINFO is enabled.
This is not required if DISPLAY_BOARDINFO_LATE is enabled because this
happens after relocation. If both are enabled, then the SoC variant will
be printed twice in the boot log, e.g.:
Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
SoC: PX30 <---- due to DISPLAY_BOARDINFO
DRAM: 2 GiB
PMIC: RK809 (on=0x40, off=0x00)
Core: 293 devices, 27 uclasses, devicetree: separate
MMC: mmc@ff370000: 1, mmc@ff390000: 0
Loading Environment from MMC... Reading from MMC(1)... OK
In: serial@ff030000
Out: serial@ff030000
Err: serial@ff030000
Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
SoC: PX30 <----- due to DISPLAY_BOARDINFO_LATE
Net: eth0: ethernet@ff360000
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Alex Shumsky [Thu, 3 Jul 2025 06:04:48 +0000 (09:04 +0300)]
rockchip: rockchip-inno-usb2: Fix Synchronous Abort on usb start
Fix NULL pointer dereference that happen when rockchip-inno-usb2 clock
enabled before device probe. This early clock enable call happen in process
of parent clock activation added in ac30d90f3367.
Fixes: 229218373c22 ("phy: rockchip-inno-usb2: Add support for clkout_ctl_phy"). Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting") Co-authored-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Alex Shumsky <alexthreed@gmail.com> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andrew Goodbody [Thu, 7 Aug 2025 16:35:23 +0000 (17:35 +0100)]
power: regulator: tps65941: Cannot test unsigned for being negative
In tps65941_buck_val and tps65941_ldo_val hex is an unsigned variable
being assigned the return value from a function that returns int. Change
hex to be an int so that the following test for an error as a negative
value will work as expected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Andrew Goodbody [Thu, 7 Aug 2025 16:35:21 +0000 (17:35 +0100)]
power: regulator: rzg2l-usbphy: Add parenthesis to return expression
In order to get the expected result from
rzg2l_usbphy_regulator_get_enable the return expression needs
parenthesis so that the binary and is performed before the double
logical not.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Andrew Goodbody [Thu, 7 Aug 2025 16:35:20 +0000 (17:35 +0100)]
power: regulator: palmas: Cannot test unsigned for being negative
In palmas_smps_val and palmas_ldo_val hex is an unsigned variable being
assigned the return value from a function that returns int. Change hex
to be an int so that the following test for an error as a negative value
will work as expected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Andrew Goodbody [Thu, 7 Aug 2025 16:35:19 +0000 (17:35 +0100)]
power: regulator: lp87565: Cannot test unsigned for being negative
In lp87565_buck_val hex is an unsigned variable being assigned the return
value from a function that returns int. Change hex to be an int so that
the following test for an error as a negative value will work as expected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Andrew Goodbody [Thu, 7 Aug 2025 16:35:18 +0000 (17:35 +0100)]
power: regulator: lp873x: Cannot test unsigned for being negative
In lp873x_buck_val and lp873x_ldo_val hex is an unsigned variable being
assigned the return value from a function that returns int. Change hex
to be an int so that the following test for an error as a negative value
will work as expected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Andrew Goodbody [Thu, 7 Aug 2025 14:28:58 +0000 (15:28 +0100)]
power: power_i2c: ret is uninitialised if not DM_I2C
In pmic_reg_read ret is only assigned to inside #if
CONFIG_IS_ENABLED(DM_I2C) so move the test and return ret inside as well
and also guard the declaration of ret with CONFIG_IS_ENABLED(DM_I2C) to
prevent a warning about an unused variable.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Andrew Goodbody [Thu, 7 Aug 2025 14:28:57 +0000 (15:28 +0100)]
power: axp: Remove redundant code
In axp_init after checking the chip ID there is an else clause that
returns ret. ret is guaranteed to be 0 at this point as the code would
have returned above if not. The next statement is a return 0 so the
return ret is redundant, remove it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Andrew Goodbody [Wed, 13 Aug 2025 16:30:12 +0000 (17:30 +0100)]
usb: cdns3: Do not access memory after free
The call to cdns3_gadget_ep_free_request will free priv_req so do the
call to list_del_init which accesses the memory pointed to by priv_req
before the free.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
- Various patches from Andrew to address issues found by Smatch
- Reinitialize job ring in crypto fsl rng
- Set scaler values for fsl dspi CS-SCK and SCK-CS
u-boot internals were being corrupted following an EFI callback to
get_rng(). One of the many footprints was a corruption of the EFI
protocols linked list.
A request for >16 bytes of random data is broken into smaller requests.
Those requests are fed in a loop to the CAAM RNG, which uses a job
queue ring for interaction.
However, the job queue descriptor is created only at probe time. That
descriptor may end up needing an endian swap (LS1046A) before being fed
to the CAAM RNG. This corrupts the descriptor for the next iteration,
since it will be blindly endian swapped yet again.
Two issues arise. The number of words to endian swap is taken from the
input descriptor itself. So on the second iteration, the length has been
corrupted. This results in a corruption past the end of the descriptor:
whatever is after in memory is endian swapped too. Second, some of the
entries in the descriptor are DMA addresses. If the descriptor is still
somehow considered valid after swapping, the data at the corrupted DMA
address is now trampled.
Linux properly initializes the descriptor for each iteration. This is
what is now done with this commit.
Signed-off-by: Anthony Pighin <anthony.pighin@nokia.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
fsl_dspi: set scaler values for CS-SCK and SCK-CS delays
These values were calculated but not set.
They are required for the calculation of the delays, as stated in the
"QorIQ LS1043A Reference Manual, Rev. 6, 07/2020" page 2172.
The delays are calculated as (1/freq)*PCSSCK*CSSCK and
(1/freq)*PASC*ASC.
Signed-off-by: Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Mon, 11 Aug 2025 16:25:17 +0000 (17:25 +0100)]
serial: lpuart: Return value from correct variable
In get_lpuart_clk_rate if the call to clk_get_rate returns an error then
the call to return should pass the value of the error which is in rate
rather than ret which will be 0 as its value is not affected by this
error.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Fri, 8 Aug 2025 10:29:33 +0000 (11:29 +0100)]
drivers: qe: avoid double free()
Avoid calling free(addr) twice if the device for ucode is not found.
This patch repeats a similar fix but that only applied to code without
CONFIG_TFABOOT enabled. This patch applies to the code with
CONFIG_TFABOOT enabled.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Mon, 4 Aug 2025 16:56:59 +0000 (17:56 +0100)]
net: fsl-mc: Incorrect variable used in error path
In mc_fixup_dpc_mac_addr noff is assigned the return value from
fdt_add_subnode so that is the variable that should be passed to
fdt_strerror and returned when negative.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Mon, 4 Aug 2025 16:56:58 +0000 (17:56 +0100)]
net: fsl-mc: NULL check dflt_dpni before dereference
In dpni_exit there is a NULL check for dflt_dpni after it is
dereferenced a number of times. Instead move the NULL check to early in
the function. Also assign NULL to dflt_dpni after free in both dpni_init
and dpni_exit.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Mon, 4 Aug 2025 16:56:57 +0000 (17:56 +0100)]
net: fsl-mc: NULL check dflt_dpbp before dereference
In dpbp_exit there is a NULL check for dflt_dpbp after it is
dereferenced a number of times. Instead move the NULL check to early in
the function. Also assign NULL to dflt_dpbp after free in both dpbp_init
and dpbp_exit.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Mon, 4 Aug 2025 16:56:56 +0000 (17:56 +0100)]
net: fsl-mc: NULL check dflt_dpio before dereference
In dpio_exit there is a NULL check for dflt_dpio but it happens after
dpio_dflt has been dereferenced a number of times already. Instead move
the NULL check to first thing in the function. Also assign NULL to
dflt_dpio after free in both dpio_init and dpio_exit.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Mon, 4 Aug 2025 16:56:55 +0000 (17:56 +0100)]
net: fsl_enetc: Fix copy/paste error
In netc_blk_ctrl_probe the test for failure of the function
clk_prepare_enable should not return PTR_ERR(ipg_clk) as it does not
check IS_ERR(ipg_clk) instead it should return err as that is what is
holding the error code in this case.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Mon, 4 Aug 2025 16:03:59 +0000 (17:03 +0100)]
net: fm: Correct test for timeout
In memac_wait_until_free and memac_wait_until_done the use of
post-decrement on the test in the while loop for a timeout means that
timeout will be equal to -1 on exit in that case. Adjust the test for
this expected value.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Mon, 4 Aug 2025 16:03:58 +0000 (17:03 +0100)]
net: fm: NULL check dev before dereference
In fm_eth_bind there is a dereference of dev before it is NULL checked.
Add a NULL check before the first dereference and remove a later NULL
check that is now redundant.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Mon, 4 Aug 2025 16:03:57 +0000 (17:03 +0100)]
net: fm: Correct test for timeout
In bmi_rx_port_disable and bmi_tx_port_disable the use of post-decrement
on the test in the while loop for a timeout means that timeout will be
equal to -1 on exit in that case. Adjust the test for this expected
value.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Lucien.Jheng [Sun, 17 Aug 2025 15:02:03 +0000 (23:02 +0800)]
misc: fs_loader: Add request_firmware_into_buf_via_script() for flexible firmware loading via U-Boot script
This commit introduces a new API,
request_firmware_into_buf_via_script(), to the fs_loader framework.
This function allows firmware to be loaded into memory using
a user-defined U-Boot script, providing greater flexibility for
firmware loading scenarios that cannot be handled by static file
paths or device/partition selection alone.
Key features:
- The API runs a specified U-Boot script (by name), which is responsible
for loading the firmware into memory by any means (e.g., load from MMC, USB, network, etc.).
- The script must set two environment variables: 'fw_addr'
(the memory address where the firmware is loaded) and
'fw_size' (the size of the firmware in bytes).
- The function validates these variables, copies the firmware into a newly
allocated buffer (using memdup), and returns the pointer
via the provided double pointer argument.
- The maximum allowed firmware size is checked to prevent buffer overflows.
- The environment variables are cleared after use to avoid stale data.
- Detailed error messages are provided for all failure conditions to aid debugging.
Usage example:
1. Define a U-Boot script in the environment that loads the firmware
and sets the required variables:
=> env set my_fw_script 'load mmc 0:1 ${loadaddr} firmware.bin &&
env set fw_addr ${loadaddr} && env set fw_size ${filesize}'
2. In your code, call the new API:
void *fw_buf = NULL;
int ret = request_firmware_into_buf_via_script(&fw_buf, 0x46000000, "my_fw_script");
if (ret < 0)
return ret;
This approach allows board integrators and users to customize the firmware
loading process without modifying the source code,
simply by changing the script in the U-Boot environment.
Signed-off-by: Lucien.Jheng <lucienzx159@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[trini: Fix printf of size_t needing to use %zx] Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 26 Aug 2025 18:49:35 +0000 (12:49 -0600)]
Merge patch series "Update SoM detection related code and configs"
Wadim Egorov <w.egorov@phytec.de> says:
Update Kconfig options for phyCORE-AM62Ax to align with other boards and
prepare common board code for the upcoming phyCORE-AM62L which has the
SoM EEPROM connected on a different bus.
Wadim Egorov [Fri, 15 Aug 2025 11:10:50 +0000 (13:10 +0200)]
board: phytec: phycore-am62a: Update SoM detection Kconfig options
Drop SUPPORT_EXTENSION_SCAN and enable PHYTEC_SOM_DETECTION_BLOCKS
to align with other PHYTEC platforms. These options were missed when
phyCORE-AM62Ax support was added.
Tom removed an unused TPM driver and fixed a few prints to include
the 'z' prefix for size_t declaratiuons. Andrew fixed an unsigned int
comparision against < 0 in the tpm infineon driver.
- Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp25_defconfig
- Fix to avoid inifite loop in stm32_sdmmc2 driver
- Populate oobavail field of nand_ecclayout in stm32_fmc2_nand driver
ufs: amd-versal2: Configure RMMI and M-PHY registers for HS mode
Configure RMMI and M-PHY registers for HS mode required for selection of
bit rate series A or B. If it is not a calibrated part, then switch back
to SLOWAUTO_MODE and skip all these configurations.
Implemented below sequence as per the DWC RMMI databook.
1. Override RMMI CBRATESEL with the desired rate.
2. Set TX_CFGUPDT_0 to 1'b1 for one TX_CFGCLK_0 cycle.
3. Override PHY rx_req to 1, then poll on PHY rx_ack register till it
goes 1(both lanes).
4. Override PHY rx_req to 0, then poll on PHY rx_ack register till it
goes 0(both lanes).
5. Remove PHY rx_req override(both lanes).
6. Start the LS PMC.
Michal Simek [Thu, 31 Jul 2025 07:06:18 +0000 (09:06 +0200)]
CI: Wire mbv32 combinations
After upgrading to QEMU 10 by commit 1d782a3f229c ("Docker, CI: Update to
latest Ubuntu and Dockerfile") let's wire mbv32 which is the part of QEMU
to have it under regression.
Michal Simek [Fri, 25 Jul 2025 12:01:22 +0000 (14:01 +0200)]
dm: core: Mark root_info as const
root_info driver structure is not changing that's why mark them as const
which ensure that structure will be moved from .data section to .rodata
section.
Michal Simek [Fri, 25 Jul 2025 12:01:21 +0000 (14:01 +0200)]
mailbox: zynqmp-ipi: Mark zynqmp_ipi_dest_mbox_ops as const
Operations are not changing that's why mark them as const which ensure that
structure will be moved from .data section to .rodata section.
Also mark them as static because they are not used out of this file.
Michal Simek [Wed, 23 Jul 2025 09:06:47 +0000 (11:06 +0200)]
serial: uartlite: Add support for OF_PLATDATA
The first change is to list DM_DRIVER_ALIAS for compatible string to be
able to match the driver. Only xps one is listed because opb one is likely
unused for quite a long time.
The second change is to add dtplat structure to plat data and fill register
base in probe.
Michal Simek [Wed, 23 Jul 2025 09:06:46 +0000 (11:06 +0200)]
serial: uartlite: Use private data instead of platform
plat data should be used only in probe or of_to_plat to fill it information
from DT. Then in probe platform data should be stored in private structure
which should be used by the other driver functions.
Anshul Dalal [Thu, 14 Aug 2025 15:21:43 +0000 (20:51 +0530)]
remoteproc: k3: update compatible for am654 syscon
The existing compatible name for U-Boot's k3 system controller driver
i.e "ti,am625-system-controller" has been added to linux[1] device-tree.
This compatible in kernel is meant for configuring the Control Module
registers (CTRL_MMR0).
However in U-Boot, the matching driver was being used to load the system
firmware on the secure M-cores by the R5 SPL and therefore must be
updated to a different compatible to avoid conflicts.
Therefore, this patch renames all references of the compatible to
"ti,am654-tisci-rproc-r5". The "-r5" is appended so as to avoid any
future conflicts since r5 specific compatibles should only be useful for
U-Boot.
Initially, only one STM32MP25 based board was available, the
stm32mp257f-ev1 board which was set by default in stm32mp25_defconfig.
Since commit 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
we inherited of a second MP25 based board which is the stm32mp257f-dk board.
Enable OF_UPSTREAM_BUILD_VENDOR and set OF_UPSTREAM_VENDOR to allow all
STMicroelectronics DT compilation.
Avoid unlimited while loop by adding a timeout. The timeout is
calculated based on a minimal throughput of 256 KB/s.
The timeout is set at least to 2 seconds.
mtd: rawnand: stm32_fmc2: set available OOB bytes per page
File system such as YAFFS2 need to know the number of available
OOB bytes per page to be able to choose if they should locate their
metadata in the data area or in the spare area.
configs: versal2: Add usb_pgood_delay for versal2 boards
Add usb_pgood_delay to ensure proper detection of USB devices.
Increase the USB power good delay for versal2 specific boards,
as certain USB sticks may not be detected without it.
Andrew Goodbody [Mon, 18 Aug 2025 09:24:36 +0000 (10:24 +0100)]
net: axi_emac: Fix timeout test
The timeout test in axi_dma_init is not correct due to the
post-decrement used on the timeout variable which will mean timeout is
not 0 if the timeout occurs. Make the timeout variable an int instead of
a u32 and then test for timeout being -1.
Michal Simek [Tue, 29 Jul 2025 13:55:20 +0000 (15:55 +0200)]
arm64: zynqmp: Add missing ethernet alias for kr260-revB
Ethernet aliases are used in fdt_fixup_ethernet() to inject
local-mac-address in every boot for OS. Similar change has been done for
other carrier cards by commit c4a711253613 ("arm64: zynqmp: Describe
ethernet controllers via aliases on SOM").
projects / thirdparty / u-boot.git / log
