Tom Rini [Tue, 12 Aug 2025 17:31:09 +0000 (11:31 -0600)]
env: Correct Kconfig type for ENV_MMC_SW_PARTITION
As part of renaming environment related Kconfig options,
ENV_MMC_SW_PARTITION was inadvertently changed from a string to a bool.
Correct this.
Fixes: ffc4914703a2 ("env: Rename ENV_MMC_PARTITION to ENV_MMC_SW_PARTITION") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tom Rini <trini@konsulko.com>
- Board: mbv: Prepare MBV for CI
- Board: MPFS Icicle Kit cleanup
- Board: Add Andes Voyager board support
- RISCV: Update SYS_BOOTM_LEN to commonly used value
- starfive: fix return code of `mac write_eeprom`
- arch/riscv/lib: update memmove and memcpy for big-endian
Ben Dooks [Thu, 7 Aug 2025 16:49:33 +0000 (17:49 +0100)]
arch/riscv/lib: update memmove and memcpy for big-endian
Change the shift patterns for the unaligned memory move and copy code
to deal with big-endian by definign macros to change the shfit left and
right to go the opposite way.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Jamie Gibbons [Fri, 1 Aug 2025 12:36:26 +0000 (13:36 +0100)]
board: microchip: mpfs_icicle: update to use system controller
A new system controller driver has been created to make code modular and
improve and clean code. Update and remove functions to account for these
additional drivers.
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Jamie Gibbons [Fri, 1 Aug 2025 12:36:25 +0000 (13:36 +0100)]
board: microchip: mpfs_icicle: enable new driver configs
Enable the MPFS mailbox and system controller drivers for use with the
Icicle kit. These functions are crucial for the board setup functions
that run in the Icicle board file - mpfs_icicle.c.
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Jamie Gibbons [Fri, 1 Aug 2025 12:36:24 +0000 (13:36 +0100)]
misc: add PolarFire SoC system controller
This driver provides an interface to access the functions of the system
controller on the Microchip PolarFire SoC.
This driver includes functions to use the system controller to read
the device serial number.
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Enable CONFIG_OF_BOARD_SETUP and other dependencies to allow the use of
the ft_board_setup() function to replace fdt set in boot scripts for
Microchip's MPFS Icicle kit.
Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Michal Simek [Tue, 22 Jul 2025 11:03:46 +0000 (13:03 +0200)]
xilinx: mbv: Use separate DTB for binman nodes
The commit d92fdb60677b ("binman: Add option for pointing to separate
description") added support for separating binman description to own file
not the be the part of DT for OS.
The main reason is that binman is not passing dt schema validation that's
why want to keep it separated.
Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Michal Simek [Tue, 22 Jul 2025 11:03:43 +0000 (13:03 +0200)]
xilinx: mbv: Disable OF_HAS_PRIOR_STAGE
There is no reason to use OF_BOARD for MBV because reduced DT is used by
SPL and full DT is passed via u-boot.img or u-boot.itb. There is no reason
to pick up DTB from certain address.
Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Martin Herren [Sat, 19 Jul 2025 21:46:34 +0000 (23:46 +0200)]
riscv: Remove default SYS_BOOTM_LEN from defconfig
Remove CONFIG_SYS_BOOTM_LEN from all riscv defconfigs where the new
default value is used.
Signed-off-by: Martin Herren <sputnik@on-the-web.ch> Acked-by: Michal Simek <michal.simek@amd.com> # xilinx_mbv Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Martin Herren [Sat, 19 Jul 2025 21:46:32 +0000 (23:46 +0200)]
riscv: Set SYS_BOOTM_LEN explicitly to 0x800000
For all riscv defconfigs that use the current default value.
This is done in provision of changing the default value to the most
common used value of 0x4000000.
Signed-off-by: Martin Herren <sputnik@on-the-web.ch> Acked-by: Michal Simek <michal.simek@amd.com> # xilinx_mbv Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Michal Simek [Thu, 17 Jul 2025 06:26:15 +0000 (08:26 +0200)]
riscv: cpu: Use CONFIG_IS_ENABLED(CPU) instead of plain ifdef
ifdef CONFIG_CPU only works in U-Boot proper but macro is not working when
XPL phases are used. In this case CONFIG_SPL_CPU is also defined and can be
disabled which is causing compilation error.
Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
rockchip: add /chosen/bootsource to U-Boot proper DT
U-Boot typically can be loaded from different storage media, such as
eMMC, SD card, SPI flash, but also from non-persistent media such as USB
(via proprietary protocols loading directly into SRAM, or fastboot, DFU,
etc..), JTAG, ...
This information is usually reported by the BootROM via some proprietary
mechanism (some specific address in registers/DRAM for example). For
Rockchip, that information is stored in a register
(BROM_BOOTSOURCE_ID_ADDR).
While we already have the information about which medium was used to
load U-Boot proper from SPL (via /chosen/u-boot,spl-boot-device), this
new property represents the medium used to load U-Boot first phase
(depending on configuration, can be VPL/TPL/SPL) which absolutely may
differ from the one used to load U-Boot proper!
It would be useful to know which medium was used to load the first phase
of U-Boot, for example to check fallback mechanisms (proper loaded from
a different medium than first phase) are actually working.
For now, this only applies to Rockchip's U-Boot proper DT but could be
applied to the kernel's as well and possibly for other architectures or
vendors.
Andrew Goodbody [Thu, 7 Aug 2025 11:20:01 +0000 (12:20 +0100)]
pinctrl: qcom: sa8775: Limit check for array index not correct
In sa8775p_get_pin_name the limit check for the index into
msm_special_pins_data allows for more elements than exist. Add code to
ensure the array index remains in bounds.
Andrew Goodbody [Wed, 23 Jul 2025 10:58:04 +0000 (11:58 +0100)]
button: qcom-pmic: Fix dereference of uninitialised pointer
The pointer 'label' is declared and later dereferenced without ever
having a value assigned to it. Add an assignment to this pointer so it
will be valid later when dereferenced.
Andrew Goodbody [Mon, 11 Aug 2025 17:03:40 +0000 (18:03 +0100)]
serial: msm-geni: No need to NULL check priv
The NULL check for priv in qcom_geni_serial_poll_bit serves no useful
prupose as too much other code surrounding it relies on priv being
valid. Remove the NULL check for priv and other related code.
Andrew Goodbody [Mon, 11 Aug 2025 17:03:39 +0000 (18:03 +0100)]
serial: msm-geni: Detect error from get_clk_div_rate
In msm_serial_setbrg if the call to get_clk_div_rate fails then there
will not have been an assignment to clk_div which will lead to the call
to geni_serial_baud using an uninitialised value.
Check for an error from get_clk_div_rate and return an error code if so.
Casey Connolly [Mon, 11 Aug 2025 10:45:13 +0000 (12:45 +0200)]
mach-snapdragon: fix erroneous lmb allocations
In commit 6e4675b8e5d8 ("lmb: replace the lmb_alloc() and
lmb_alloc_base() API's") an additional allocation was mistakenly
introduced resulting in ${kernel_comp_size} containing the address of a
second 64mb region rather than the actual value of KERNEL_COMP_SIZE.
Additionally, in commit b40d7b8f72f1 ("Merge patch series "lmb: use
a single API for all allocations"") merge conflict resulted in an
additional 128mb allocation for ${loadaddr} when CONFIG_FASTBOOT
is enabled, where it should actually be set to the same value as
${fastboot_addr_r} to respect size constraints (and since it doesn't
seem to interfer with any bootflows).
Fixup both of these, freeing up 192mb of memory.
Fixes: 6e4675b8e5d8 ("lmb: replace the lmb_alloc() and lmb_alloc_base() API's") Fixes: b40d7b8f72f1 ("Merge patch series "lmb: use a single API for all allocations"") Link: https://lore.kernel.org/r/20250811104710.1896382-1-casey.connolly@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Andrew Goodbody [Wed, 6 Aug 2025 16:55:04 +0000 (17:55 +0100)]
phy: qcom: Fix ret is uninitialised
In qcom_snps_eusb2_phy_probe after the call to devm_clk_get if an error
is found then ret is printed but has not been assigned to by the code.
Decode the error from the pointer and assign it to ret.
Andrew Goodbody [Tue, 29 Jul 2025 16:16:16 +0000 (17:16 +0100)]
mmc: gen_atmel_mci: Remove duplicate checks
Remove duplicate checks on status from mci_data_read and mci_data_write
which are guaranteed to be true as exiting the above do..while loop
above requires that to be so.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Andrew Goodbody [Mon, 28 Jul 2025 16:12:13 +0000 (17:12 +0100)]
mfd: atmel-smc: Ensure match is initialised
If the test in the for loop is never matched then the variable 'match'
will never be assigned to. Provide an initial value so this cannot be a
problem.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Wed, 23 Jul 2025 14:13:49 +0000 (15:13 +0100)]
clk: at91: Fix use of unsigned loop index
The use of the unsigned variable 'i' as a loop index leads to the test
for i being non-negative always being true. Instead declare 'i' as an
int so that the for loop will terminate as expected.
If the original for loop completes 'i' will be 1 past the end of the
array so decrement it in the subsequent error path to prevent an out of
bounds access occurring.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Wed, 23 Jul 2025 14:13:48 +0000 (15:13 +0100)]
clk: at91: Fix testing of unsigned variable to be negative
The variable 'index' is declared as unsigned but used to receive the
return value of a function returning 'int'. This value is then tested
for being less than zero to detect an error condition but as index is
unsigned this can never be true. Change the variable 'index' to be an
int so that the error condition can be detected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
However, this is racy: QSPI_SR_INSTRE can be set before QSPI_SR_CSR,
and will then be cleared by the read. If that happens, the condition
"(sr & imr) == imr" can never be true, and the function times out.
This race condition is avoided in at91bootstrap by accumulating the
status bits across reads until both bits have been observed:
/* Poll INSTruction End and Chip Select Rise flags. */
imr = (QSPI_SR_INSTRE | QSPI_SR_CSR);
sr = 0;
do {
udelay(1);
sr |= qspi_readl(qspi, QSPI_SR) & imr;
} while ((--timeout) && (sr != imr));
Update U-Boot's atmel_qspi_transfer() to use the same pattern,
ensuring that both flags are observed even if they are not set
simultaneously.
Signed-off-by: Ramin Moussavi <lordrasmus@gmail.com>
[eugen.hristev@linaro.org: remove 'sr' and fix commit msg] Signed-off-by: Eugen Hristev <eugen.hristev@linaro.org>
Tom Rini [Tue, 12 Aug 2025 13:53:33 +0000 (07:53 -0600)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
These changes are mostly smaller fixes, and some additions that were
dependent on recent DT updates: We switch the S3/V3/V3s over to
OF_UPSTREAM, the DTs were already identical anyway. While at it, Paul
sent more fixes for this SoC, I am pulling in two easy fixes that were
ready and low risk. Apart from other assorted fixes, this PR also
enables Ethernet on the new A527/T527 boards, made possible by the DT
update from the DT rebasing repository.
This passed the CI, and was boot tested on boards with Allwinner A10,
A20, A33, V40, A80, A83T, T113s3, F1C100s, H3, A64, H6, H616, A133 and
T527 SoCs.
The JEDEC LPDDR3 spec defines mode register 0 (MR0) as being read-only,
so there is no point in trying to set its value.
Also the H616 memory controller encodes the mode register index to be
written starting from bit 8 in MRCTRL1 (for LPDDR3 and LPDDR4 chips), so
we need to OR in that number to tell the controller which MR to program.
On top of that, the mode registers between DDR3 and LPDDR3 are
completely different, so writing values crafted for DDR3 into a LPDDR3
chip is just wrong. Due to the above mentioned bugs the writes for
MR0-MR2 did not have any effect (as they were all trying to set the
read-only MR0), so the mode registers just stayed unchanged.
Looking at the LPDDR3 spec and the BSP code, let's write the proper MR
values into LPDDR3 chips, using the proper addressing mode.
Use the opportunity to document the LPDDR3 mode register bits written.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Eric Anderson [Sun, 13 Jul 2025 00:27:41 +0000 (17:27 -0700)]
sunxi: Enable SPL/SPI boot for OLinuXino Lime2
58e9502e6 "arm: sunxi: Enable SPL/SPI boot for Olinuxino Lime2-eMMC
boards" enabled SPI boot for the eMMC variant. Olimex offers the
"s16MB" variant with SPI flash populated but without eMMC populated.
Tested on board rev L.
Signed-off-by: Eric Anderson <ejona86@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 20 Jul 2025 15:29:19 +0000 (16:29 +0100)]
sunxi: spl: initialise timer before clocks
Recent changes in the H6 clock code added delay() calls into the SPL clock
setup routine, which requires the timers to work. When compiling for
AArch64, we are always using the Arm Generic Timer (aka. arch timer),
which does not require further setup, hence having an empty timer_init()
routine.
However for 32-bit SoCs we use the Allwinner timers, which require some
setup routine, and hence we need timer_init() to be called before
clock_init().
Swap the order of the two calls, to be more robust when compiling the H6
clock code for AArch32 or when using the Allwinner timers for whatever
reason.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Fri, 18 Jul 2025 23:58:34 +0000 (00:58 +0100)]
sunxi: a133: dram: fix data type for address variable
Variables holding addresses are typically using the "long" C type in
U-Boot, to be easily compatible with both 32-bit and 64-bit builds.
The A133 DRAM driver is typically compiled for AArch64, so u64 is the
same type as unsigned long, but that breaks when compiling the DRAM
driver in AArch32 (for some experiments).
Fix the type to make the code more portable.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Mon, 28 Jul 2025 23:24:52 +0000 (00:24 +0100)]
sunxi: a527: radxa/avaota: enable Ethernet
The first of the two Ethernet controllers in the Allwinner A527/T527 is
compatible to the MAC from the previous SoCs. Consequently the recent DT
update brought use the MAC node, using the A64 compatible string as the
fallback, which works out of the box.
Enable the sun8i-emac Ethernet driver in the defconfig for the Radxa and
the Avaota boards, so that kernels and other data can be loaded via
TFTP. Please note that only one of the Ethernet sockets will work, the
second MAC is not compatible, and needs a new U-Boot driver. The
X96QPro+ TV box unfortunately uses only this second EMAC, so Ethernet
cannot be used there at the moment.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
sunxi: Kconfig: Fix default order for V3s DRAM clock
The V3s (using co-packaged DRAM) runs at 360 MHz, which is specified in
the common platform Kconfig file. However the value for MACH_SUN8I will
be picked up instead due to ordering.
Re-order the defaults to have MACH_SUN8I_V3S before MACH_SUN8I and let
it select the correct default. Also update the LicheePi Zero Dock
defconfig to remove the value, which is now correctly selected.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Andrew Goodbody [Fri, 25 Jul 2025 11:48:22 +0000 (12:48 +0100)]
gpio: dwapb_gpio: Using wrong function to free memory
In gpio_dwapb_bind plat is used to reference memory allocated by
devm_kcalloc but it is attempted to be freed using kfree. Instead free
this memory using the correct devm_kfree function.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
Andrew Goodbody [Fri, 25 Jul 2025 10:41:12 +0000 (11:41 +0100)]
clk: cdce9xx: Fix use of dev_read_u32_default
The function dev_read_u32_default does not return an error and the
variable 'val' is unsigned so testing for >= 0 will always be true. It
looks like the code was attempting to return -1 if xtal-load-pf was not
present but that cannot work. Instead use dev_read_u32 which returns an
error code separately from writing the value into the passed pointer.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Fixes: 260777fc2333 ("clk: cdce9xx: add support for cdce9xx clock synthesizer") Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
Tom Rini [Fri, 18 Jul 2025 01:15:52 +0000 (19:15 -0600)]
sandbox: Add more dummy functions to mimic other architectures
This adds more common functions found on other architectures that will
allow for more compile-testing of drivers. These are either dummy
functions as we do not need them or mappings to existing functions,
similar to how other architectures handle it.
board: phytec: phycore-am64x: Add watchdog start to bootcmd
Allows run-time control over watchdog auto-start and the timeout via
setting the environment variable watchdog_timeout_ms. A value of zero
means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value.
Users can enable the watchdog to monitor the boot process until userspace
or OS takes over to serve the watchdog.
We switched towards standard boot with still keeping a fallback
using legacy boot command alive. Add a deprecation warning to
make it more clear that we will remove it in future versions.
board: phytec: phycore-am62x: Add watchdog start to bootcmd
Allows run-time control over watchdog auto-start and the timeout via
setting the environment variable watchdog_timeout_ms. A value of zero
means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value.
Users can enable the watchdog to monitor the boot process until userspace
or OS takes over to serve the watchdog.
board: phytec: phycore-am62ax: Add watchdog start to bootcmd
Allows run-time control over watchdog auto-start and the timeout via
setting the environment variable watchdog_timeout_ms. A value of zero
means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value.
Users can enable the watchdog to monitor the boot process until userspace
or OS takes over to serve the watchdog.
arch: arm: dts: k3-am642-phyboard-electra: Disable unused watchdogs in U-Boot
The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.
arch: arm: dts: k3-am62a7-phyboard-lyra: Disable unused watchdogs in U-Boot
The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.
arch: arm: dts: k3-am625-phyboard-lyra: Disable unused watchdogs in U-Boot
The watchdog driver probes all available watchdog devices.
This causes SMP boot errors when bringing up secondary CPUs.
In our setup, only a single watchdog is needed to monitor the
boot process until userspace or the OS takes over. Disable all
unnecessary watchdog devices in U-Boot to avoid conflicts
during CPU bring-up.
Tom Rini [Mon, 11 Aug 2025 17:58:25 +0000 (11:58 -0600)]
arm: socfpga: Correct how we set BOOTFILE
In order to set the BOOTFILE symbol we first need to have USE_BOOTFILE
be set, or some of the logic might not work as expected later on when
building. Second, defaults like this belong with the symbol itself.
Fixes: da595d236b97 ("include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile") Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 8 Aug 2025 17:13:41 +0000 (11:13 -0600)]
Merge tag 'u-boot-socfpga-next-20250808' of https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request introduces initial U-Boot support for Agilex7 M-series, along
with several enhancements and cleanups across existing Agilex platforms. Key
changes include new board support, DDR driver additions, updated device trees,
and broader SoCFPGA SPL improvements.
Highlights:
- Agilex7 M-series bring-up:
- Basic DT support and board initialization for Agilex7 M-series SoC and
SoCDK.
- New sdram_agilex7m DDR driver with UIBSSM mailbox support and HBM support.
- Clock driver support for Agilex7 M-series.
- New defconfig: socfpga_agilex7m_defconfig.
- Agilex and Agilex5 enhancements:
- Improved SPL support: ASYNC interrupt enabling, system manager init
refactor, and cold scratch register usage.
- Updated firewall probing and watchdog support in SPL.
- Cleaned up DDR code, added secure region support for ATF, and improved warm
reset handling.
- Device Tree and config updates:
- Migration to upstream Linux DT layout for Agilex platforms.
- Consolidated socfpga_agilex_defconfig and removed deprecated configs.
- Platform-specific environment variables for Distro Boot added.
- Driver fixes and cleanups:
- dwc_eth_xgmac and clk-agilex cleanup and improvements.
- Several coverity and style fixes.
Contributions in this PR are from Alif Zakuan Yuslaimi, Tingting Meng, and
Andrew Goodbody. This patch set has been tested on Agilex 5 devkit, Agilex
devkit and Agilex7m devkit.
Passing all pipeline tests at SoCFPGA U-boot custodian
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27318
- Several Smatch reported fixes.
- Enable the temperature command on imx8ulp-evk.
- Fix mx8mm_fracpll_tbl.
- Make optee packaging optional for imx8m.
- Reuse and export low_drive_freq_update() on imx9.
- Enable USB OTG ID pin pull up in SPL on dh-imx6.
Tingting Meng [Mon, 4 Aug 2025 01:24:56 +0000 (18:24 -0700)]
ddr: altera: Add DDR driver for Agilex7 M-series
This is for new platform enablement for Agilex7 M-series.
Add DDR driver for Agilex7 M-series. This driver is designed to support
DDR and HBM memory. The official HBM handoff is not ready yet, therefore
hardcoded handoff is used for HBM driver validation on mUDV board.
Tingting Meng [Mon, 4 Aug 2025 01:24:55 +0000 (18:24 -0700)]
ddr: altera: Add uibssm mailbox support for Agilex7 M-series with HBM
Add uibssm mailbox driver for Agilex7 M-series. HPS will interact with UIB
and HBM subsystem through software defined mailbox interface.
HPS can retrieve HBM memory interface calibration status, UIB
configuration, memory interfae configuration, trigger calibration and etc
with the list of supported mailbox command type and opcode.
Tingting Meng [Mon, 4 Aug 2025 01:24:53 +0000 (18:24 -0700)]
include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile
ATF boot flow (SPL->ATF->U-Boot Proper->OS) boot to OS via kernel.itb file
using bootm command.
Change to use CONFIG_SPL_ATF to differentiate the bootfile of default
environment variable. We shouldn't use CONFIG_FIT because it is enabled
by default for U-Boot Proper.
Tingting Meng [Mon, 4 Aug 2025 01:24:47 +0000 (18:24 -0700)]
arch: arm: dts: agilex: Switch to using upstream Linux DT config
Migrate the legacy Agilex platform to use the upstream Linux device tree
configuration. This helps reduce maintenance overhead and aligns U-Boot
with the Linux kernel's DTS hierarchy and naming conventions.
This change improves consistency between U-Boot and Linux by removing
custom/legacy DTS handling and instead relying on the standardized
definitions provided by the upstream Linux DTS.
Tingting Meng [Mon, 4 Aug 2025 01:24:46 +0000 (18:24 -0700)]
arch: arm: agilex: Clean up DT settings in U-Boot dtsi files
Reorganize misplaced properties by moving board-common settings from
socfpga_agilex_socdk-u-boot.dtsi to socfpga_agilex-u-boot.dtsi to maintain
proper separation between common and board-level configurations.
arm: socfpga: soc64: Perform warm reset after L2 reset in SPL
SPL checks for a magic word in the system manager's scratch
register to determine if an L2 reset has occurred. If detected,
SPL places all slave CPUs (CPU1–3) into WFI mode. The master
CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3
system register and also enters WFI mode.
This warm reset flow is handled entirely within the HPS. The
function `socfpga_sysreset_request()` triggers the warm
reset, and upon SPL re-entry, the updated `lowlevel_init_soc64.S`
handles the necessary initialization.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
ddr: altera: agilex: Get ACF from boot scratch register
The DDR data rate must be set correctly in the DDRIOCTRL
register according to the Actual Clock Frequency (ACF) value.
By enabling the reading of ACF value from bit 18 of the boot
scratch register during initialization, the DDR data rate is
able to be configured accurately.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: socfpga: Define the usage of boot scratch cold reg 8
The boot scratch cold reg 8 is shared between DBE, DDR init progress
update and Linux EDAC. This patch defines how the bits are used by
respective features above and their macro names used in U-Boot.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
ddr: altera: soc64: Add secure region support for ATF flow
Setting up firewall regions based on SDRAM memory banks configuration
(up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space.
First 1 MiB (0 to 0xfffff) of SDRAM is configured as secure region,
other address spaces are non-secure regions. The ARM Trusted Firmware (ATF)
image is located in this first 1 MiB memory region. So, this can prevent
software executing at non-secure state EL0-EL2 and non-secure masters
access to secure region.
Add common function for firewall setup and reuse for all SoC64 devices.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
projects / thirdparty / u-boot.git / log
