Tom Rini [Sun, 8 Dec 2024 17:07:28 +0000 (11:07 -0600)]
Gitlab: Avoid downloading all artifacts in later stages
In the test.py stage of the build we mark the pytest results as
artifacts to save, so that they can be used for reports. This however
leads to all of the artifacts being downloaded (and then not used) in
later stages. Optimize this out by using an empty list of dependencies
here (which is the keyword for which artifacts are needed).
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sun, 8 Dec 2024 17:07:27 +0000 (11:07 -0600)]
GitLab: Add a default workflow stanza
When validating our current pipeline, a warning is produced about a lack
of a default workflow. For how we use it, we can add a simple default of
"always".
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sun, 8 Dec 2024 17:07:26 +0000 (11:07 -0600)]
GitLab CI: Make wider use of tags
First, introduce DEFAULT_ALL_TAG, DEFAULT_ARM64_TAG, DEFAULT_AMD64_TAG
and DEFAULT_FAST_AMD64_TAG and remove the previous DEFAULT_TAG (as
anyone making use of that will need to adjust their jobs). This allows
us to say that some jobs can run on amd64 or arm64 hosts under the all
tag, while some jobs must run on amd64 (the Xtensa jobs due to
binary-only toolchains and sandbox for now) Then we rework the world
build stage to only run on our very fast amd64 hosts, or our arm64 hosts
(which are also very fast). This should result in a similar overall
build time but also a much more consistent overall build time as we
won't have the two big world jobs possibly run on our slower build
nodes.
Tom Rini [Sun, 8 Dec 2024 17:07:24 +0000 (11:07 -0600)]
Docker/CI: Only test Xtensa on amd64 hosts
The xtensa architecture is interesting in that the platforms we support
are only valid on the binary-only toolchains as the DC233C instruction
set requires those toolchains (and not the FSF instruction set). Only
install the binary toolchain on amd64 hosts and only run the tests on
them as well.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 19 Dec 2024 10:52:46 +0000 (11:52 +0100)]
net: rswitch: Add missing cache invalidate of TX descriptor
TFTP transfers of large files, for example 128 MiB, can sporadically
get stuck and the transfer slows down considerably.
This happens because the TX DMA descriptor in DRAM becomes out of sync
with the view of the TX DMA descriptor content from the CPU side, which
is viewed through the CPU caches. In order to guarantee these two views
are consistent, the cache over TX DMA descriptor that has possibly been
written by the rswitch hardware must first be invalidated, only then can
the descriptor be cleared and updated by the CPU, and finally the cache
over that area must be flushed back into DRAM to make sure the rswitch
hardware has consistent view of the updated descriptor content.
The very first invalidation operation was missing, which led to sporadic
corruption of the TX DMA descriptor. Fix it, add the missing invalidation
operation.
Reported-by: Enric Balletbo i Serra <eballetb@redhat.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Tested-by: Enric Balletbo i Serra <eballetb@redhat.com>
Marek Vasut [Wed, 18 Dec 2024 19:41:28 +0000 (20:41 +0100)]
net: renesas: Enable TFTP_TSIZE on all Renesas hardware
TFTP transfer size can be used to re-size the TFTP progress bar on
single line based on the server reported file size. Enable it by
default for Renesas hardware to avoid long scrolling walls of '#'
character during long TFTP transfers.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks
Early revisions of the R-Car V4M Series Hardware User’s Manual
contained an incorrect formula for the CPU core clocks:
ZCnφ = (PLL2VCO x 1/2) x mult/32
Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the
parent clock.
In Rev.0.70 of the documentation, the formula was corrected to:
ZCnφ = (PLL2VCO x 1/4) x mult/32
As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2,
the use of CLK_PLL2_DIV2 is a recurring source of confusion. Hence get
rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the
invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4
(and Gen3) SoCs.
Ported from Linux commit 92850bed9d4d ("clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks")
common: memtop: Fix the return type for find_ram_top
As the return type is "int" for find_ram_top() function and
returning the "base" which is of phys_addr_t is breaking when the
"base" address is 64-bit. So fix this by updating the return type as
phys_addr_t.
Manorit Chawdhry [Tue, 10 Dec 2024 09:16:45 +0000 (14:46 +0530)]
Makefile: Match the full path to ccache for filtering
One can use ccache by keeping ccache in PATH or by providing the full
path to ccache as well. Providing the full path to ccache fails as the
current regex tries to look for ccache being the initial token during
filtering.
Do a greedy search to remove anything before ccache for regex matching.
Fixes: 04b1d84221d5 ("Makefile: fix empty MK_ARCH when using ccache") Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Ilias Apalodimas [Wed, 18 Dec 2024 09:00:06 +0000 (11:00 +0200)]
imx: Fix usable memory ranges for imx8m SOCs
commit e27bddff4b97 ("imx8m: Restrict usable memory to space below 4G boundary")
tried to adjust the usable memory limits on a 4GB boundary.
ram_top is described as 'top address of RAM used by U-Boot' and we want
to preserve that. This is defined as a phys_addr_t and unfortunately
its size differs across architectures. This has lead us to a weird
state where 32bit boards define it 'SZ_4GB - 1' and 64bit boards as
'SZ_4GB' unless it was otherwise defined.
With some recent LMB changes and specifically
commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank")
the board fails to boot properly although the commit above is correct
since it's making sure that no memory above ram_top is usable -- but
added to our memory map so EFI can hand it over to the booted OS.
The reason for that is that during the LMB init we add all usable memory
in lmb_add_memory(). In that function any memory above ram_top gets added
as 'reserved' for LMB. With the current values tha's set to 0xFFFF_FFFF
for this board. Later LMB is trying to protect the memory area U-Boot lives
in with lmb_reserve_common(). The latter fails though since it tries to
add U-Boot top (which is 0xFFFF_FFFF as well) to U-Boot 'bottom'. This call
will fail since 1 byte of that memory range is already marked as 'reserved'.
Since we are close to the release, LMB seems to assume that the address
is rounded up and is the 'next address' and so does parsing and adding
memory ranges from DT files, bump the ram_top of the board by 1byte.
In the long run we should change all of the above and have 32b and 64b
platforms define ram_top identically.
Add a Fixes tag although the commit is correct, so people can figure out
the broken scenarios in the future.
Suggested-by: Sughosh Ganu <sughosh.ganu@linaro.org> Fixes: commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank") Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reported-by: João Paulo Gonçalves <jpaulo.silvagoncalves@gmail.com> Closes: https://lore.kernel.org/all/20241216114231.qpfwug3zfqkxn3d5@joaog-nb.corp.toradex.com/ Reviewed-by: Peng Fan <peng.fan@nxp.com> Fixes: 74f88b72219e ("ARM: imx: imx8m: Fix board_get_usable_ram_top()")
("Enable EFI_LOADER_BOUNCE_BUFFER") is not the correct fix for the
problem it describes.
The change of memory addressing leading to side-effects in commit 22f2c9ed9f53 ("efi: memory: use the lmb API's for allocating and
freeing memory") is remedied by commit 1a48b0be93d4 ("lmb: prohibit
allocations above ram_top even from same bank").
Android:
- Fix kcmdline_extra support when parsing boot image
- Fix memory leak when after bootargs concatenation
- Fix length calculation when merging bootargs, cmdline and kcmdline
Paul HENRYS [Mon, 25 Nov 2024 18:16:54 +0000 (19:16 +0100)]
tools: binman: etype: fit: Append DTB directory to the list of input directories
When specifying a directory containing DTBs with 'fit,fdt-list-dir', it can be
handy not to have to also specify this directory to the input directories of
binman with '-I' option and use the method tools.append_input_dirs() append it.
This avoids to have to specify the DTB directory in both the device tree
provided to binman and through '-I' option to binman.
Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Paul HENRYS [Mon, 25 Nov 2024 17:54:21 +0000 (18:54 +0100)]
tools: binman: etype: Allow to replace 'NAME' in node names
This change allows to replace both 'SEQ' and 'NAME' keywords by respectively a
sequence number and the name of the FDT to provide more flexibility in the node
name for the device trees included in the FIT.
Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Paul HENRYS [Mon, 25 Nov 2024 17:47:16 +0000 (18:47 +0100)]
tools: binman: add 'fit, encrypt' property to pass keys directory to mkimage
mkimage can be used for both signing the FIT or encrypt its content and the
option '-k' can be used to pass a directory where both signing and encryption
keys can be retrieved. Adding 'fit,encrypt' property to the 'fit' node, leads to
try to find keys directory among binman include directories.
_get_priv_keys_dir() is renamed as _get_keys_dir() and adapted to support both
signing and encryption nodes in the FIT.
Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Paul HENRYS [Mon, 25 Nov 2024 17:47:15 +0000 (18:47 +0100)]
aes: Allow to store randomly generated IV in the FIT
When the initialisation vector is randomly generated, its value shall be
stored in the FIT together with the encrypted data. The changes allow to
store the IV in the FIT also in the case where the key is not stored in
the DTB but retrieved somewhere else at runtime.
Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
The current buffer address makes fastboot downloads work only on
hardware with 2GB of RAM.
To fix this issue:
1. Lower CONFIG_FASTBOOT_BUF_ADDR to 0x88200000. This makes the buffer
to be equal ot CONFIG_SYS_LOAD_ADDR, which is a safe address to
download files using fastboot.
2. Reduce the size of the download buffer to 128MB, avoiding overlaps
with RAMDISK_ADDR_R. This is a good enough value for individual
downloads.
These changes make fastboot downloads work with 512MB and 1GB devices.
Fixes: defe30a78b76 ("verdin-am62: add DFU, USB and UUU fastboot support") Signed-off-by: Hiago De Franco <hiago.franco@toradex.com> Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Paul HENRYS [Wed, 20 Nov 2024 10:39:43 +0000 (11:39 +0100)]
arch: x86: lib: Add support of legacy 64-bit entry point at 0x200
Support of legacy 64-bit entry point was already present when booting a bzimage
with 'zboot' but not supported with 'bootm' when the x86_64 Linux kernel is
embedded in a FIT image.
Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This patch-set repairs ability to use sandbox with CONFIG_OF_EMBED=y.
For now, to use OF_EMBED, the following must be done
1) sandbox64_defconfig should have:
```
-CONFIG_OF_LIVE=y
+CONFIG_OF_EMBED=y
```
2) On sandbox when CONFIG_OF_EMBED=y, the u-boot process can't start
due to:
```
Bloblist at b000 not found (err=-2)
initcall failed at call 000000000011829c (err=-2: No such file or \
directory)
### ERROR ### Please RESET the board ###
```
So, it is natural desire to disable CONFIG_BLOBLIST just to test
sandbox with OF_EMBED=y (disable it one way or another):
```
config SANDBOX
- select BLOBLIST
+ select BLOBLIST if SOME_NON_EXISTING_OPTION
```
3) As a result, having such changes (CONFIG_OF_EMBED=y &&
CONFIG_BLOBLIST=n) leads to the link & run-time errors, being fixed
by this patch series.
Tom Rini [Wed, 18 Dec 2024 18:34:58 +0000 (12:34 -0600)]
Merge patch series "fdt: Correct condition for receiving bloblist"
This series is from Simon Glass <sjg@chromium.org>.
It first corrects the test for checking if a bloblist could have come
from TPL and so we check for a device tree, and then changes the
argument order for board_fdt_blob_setup() to be more inline with our
usual argument ordering.
Evgeny Bachinin [Mon, 2 Dec 2024 13:45:25 +0000 (16:45 +0300)]
test: sandbox: fix link error with do_ut_bootm if BLOBLIST=n
Having CONFIG_OF_EMBED=y && CONFIG_BLOBLIST=n leads to the link
error:
```
ld: /tmp/ccwtRVty.ltrans28.ltrans.o:(.data.rel+0x4e8): undefined \
reference to `do_ut_bootm'
```
Evgeny Bachinin [Mon, 2 Dec 2024 13:45:24 +0000 (16:45 +0300)]
test: sandbox: fix link error with do_ut_bloblist if BLOBLIST=n
Having CONFIG_OF_EMBED=y && CONFIG_BLOBLIST=n leads to the link
error:
```
ld: /tmp/ccwtRVty.ltrans28.ltrans.o:(.data.rel+0x4b0): undefined \
reference to `do_ut_bloblist'
```
Fixes: 6ea5df39e8d ("test: Only enable bloblist test when supported") Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Evgeny Bachinin [Mon, 2 Dec 2024 13:45:23 +0000 (16:45 +0300)]
test: sandbox: fix invalid_use_of_IF_ENABLED_INT if BLOBLIST=n
Having CONFIG_OF_EMBED=y && CONFIG_BLOBLIST=n leads to the link
error:
```
ld: /tmp/ccRVty.ltrans40.ltrans.o: in function `lib_test_is_enabled':
test/lib/kconfig.c:24: undefined reference to \
`invalid_use_of_IF_ENABLED_INT'
ld: test/lib/kconfig.c:26: undefined reference to \
`invalid_use_of_CONFIG_IF_ENABLED_INT'
```
Fixes: 29784d62ede ("test: Add some tests for kconfig.h") Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Evgeny Bachinin [Mon, 2 Dec 2024 13:45:22 +0000 (16:45 +0300)]
sandbox: fix bloblist_finish() linker error if BLOBLIST=n
Having CONFIG_OF_EMBED=y && CONFIG_BLOBLIST=n leads to the link
error:
```
ld: /tmp/ccwtRVty.ltrans0.ltrans.o: in function `state_uninit':
arch/sandbox/cpu/state.c:508: undefined reference to `bloblist_finish'
```
Fixes: 1c52fcca72b ("sandbox: Write out bloblist when exiting") Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 2 Nov 2024 17:49:42 +0000 (11:49 -0600)]
fdt: Swap the signature for board_fdt_blob_setup()
This returns a devicetree and updates a parameter with an error code.
Swap it, since this fits better with the way U-Boot normally works. It
also (more easily) allows leaving the existing pointer unchanged.
No yaks were harmed in this change, but there is a very small code-size
reduction.
For sifive, the OF_BOARD option must be set for the function to be
called, so there is no point in checking it again. Also OF_SEPARATE is
defined always.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
[trini: Update total_compute] Signed-off-by: Tom Rini <trini@konsulko.com>
- Board: Support LicheeRV Nano
- Board: Support bananapi-f3
- Board: Switch to OF_UPSTREAM for StarFive JH7110
- Board: Add sdhci driver for TH1520 SoC
Nicolas Belin [Tue, 17 Dec 2024 13:29:10 +0000 (14:29 +0100)]
boot: android: rework bootargs concatenation
Rework the bootargs concatenation allocating more accurately
the length that is needed.
Do not forget an extra byte for the null termination byte as,
in some cases, the allocation was 1 byte short.
Nicolas Belin [Tue, 17 Dec 2024 13:29:08 +0000 (14:29 +0100)]
boot: android: fix extra command line support
Check that the value at the address kcmdline_extra is not 0
instead of checking the address value itself keeping it
consistent with what is done for kcmdline.
Marek Vasut [Sun, 15 Dec 2024 23:29:15 +0000 (00:29 +0100)]
ARM: dts: stm32: Deduplicate CONFIG_OF_SPL_REMOVE_PROPS on DH STM32MP15xx DHSOM
The content of CONFIG_OF_SPL_REMOVE_PROPS is the same in both
STM32MP15xx DHCOM and DHCOR defconfigs, deduplicate the content
into stm32mp15_dhsom.config .
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Sun, 15 Dec 2024 23:29:13 +0000 (00:29 +0100)]
ARM: dts: stm32: Reinstate SPL_SYS_MMCSD_RAW_MODE on DH STM32MP15xx DHSOM
Commit 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options")
broke booting from SD card on STM32MP15xx , reinstate raw mode SD
boot configuration options and select the correct raw mode partition
for STM32MP15xx to fix SD boot on STM32MP15xx DHSOM.
Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Reported-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The root oscillators reference used to be in rcc node since 3d15245502c4 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver")
however this is not part of upstream stm32mp151.dtsi . The
RCC driver does need this reference, reinstate it locally.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Sun, 15 Dec 2024 23:31:38 +0000 (00:31 +0100)]
ARM: dts: stm32: Reinstate missing root oscillators on STM32MP15xx
The root oscillators reference used to be in rcc node since 3d15245502c4 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver")
however this is not part of upstream stm32mp151.dtsi . The
RCC driver does need this reference, reinstate it globally.
Patrice Chotard [Wed, 18 Dec 2024 07:58:33 +0000 (08:58 +0100)]
Kconfig: Set STACK_SIZE to 16KB for STM32 MCUs
Since commit 6534d26ee9a5 ("lmb: do away with arch_lmb_reserve()"),
STM32F746-disco hangs when loading device tree just before starting
kernel:
Retrieving file: /stm32f746-disco.dtb
Kernel image @ 0xc0008000 [ 0x000000 - 0x19ae00 ]
Flattened Device Tree blob at c0408000
Booting using the fdt blob at 0xc0408000
Working FDT set to c0408000
Loading Device Tree to c05f8000, end c05ff71c ...
Adjust STACK_SIZE to 16KB for STM32 MCUs (F4/F7 and H7) boards
to fix kernel boot process as some of these boards embeds a limited
amount of memory.
Fixes: 6534d26ee9a5 ("lmb: do away with arch_lmb_reserve()") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Randolph [Fri, 13 Dec 2024 06:51:16 +0000 (14:51 +0800)]
riscv: spl: add FIT name for RISC-V Falcon mode
The FIT name in RISC-V Falcon mode should be different from that in
normal boot mode; it is called linux.itb. If the setting is missing
in common/spl, the normal boot file name will be used.
Kongyang Liu [Sun, 15 Dec 2024 05:02:41 +0000 (13:02 +0800)]
riscv: spacemit: bananapi_f3: initial support added
Add basic support for SpacemiT's Banana Pi F3 board.
Update the k1.dtsi align with mainline.
Note that the device tree files follow the mainline Linux source[1].
Hal Feng [Sun, 8 Dec 2024 09:19:36 +0000 (17:19 +0800)]
riscv: dts: jh7110: Add u-boot device tree for JH7110 based boards
To support the other JH7110 based boards, add u-boot
device tree for them.
Tested-by: Anand Moon <linux.amoon@gmail.com> Tested-by: E Shattow <lucent@gmail.com> Reviewed-by: E Shattow <lucent@gmail.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Cc: H Bell <dmoo_dv@protonmail.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 8 Dec 2024 09:19:31 +0000 (17:19 +0800)]
dts: starfive: Switch to using upstream DT
Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to
the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi
to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b
device tree as the default device tree.
Drop redundant DT files from arch/riscv/dts/ and redundant clock and
reset definitions from include/dt-bindings/.
Since the old clock definitions is a little different from those in
upstream Linux, update the clock definitions in clock drivers
accordingly.
Tested-by: Anand Moon <linux.amoon@gmail.com> Tested-by: E Shattow <lucent@gmail.com> Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
riscv: dts: sophgo: add device tree for LicheeRV Nano
Import a slightly modified version of the LicheeRV Nano and SG2002
device trees from the Linux Kernel. The current supported IPs are UART,
MMC, Timer, PLIC and CLINT.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
This is a debug command to monitor the retention state of the data on
the array. The command needs a duplication of the mtd_read_oob()
function to actually return the maximum number of bitflips encountered
while reading the page. We could write a specific implementation for the
Sunxi driver but this is probably enough.
nand watch <off> <size> - check an area for bitflips
nand watch.part <part> - check a partition for bitflips
nand watch.chip - check the whole device for bitflips
The output may be a bit verbose and could look like:
=> nand watch.chip
device 0 whole chip
size adjusted to 0xff60000 (5 bad blocks)
NAND watch for bitflips in area 0x0-0xff60000:
Page 0 (0x00000000) -> error -74
Page 1 (0x00000800) -> error -74
Page 2 (0x00001000) -> error -74
Page 3 (0x00001800) -> error -74
Page 4 (0x00002000) -> error -74
Page 5 (0x00002800) -> error -74
Page 6 (0x00003000) -> error -74
Page 7 (0x00003800) -> error -74
Page 8 (0x00004000) -> error -74
Page 9 (0x00004800) -> error -74
Page 10 (0x00005000) -> error -74
Page 11 (0x00005800) -> error -74
Page 12 (0x00006000) -> error -74
Page 13 (0x00006800) -> error -74
Page 14 (0x00007000) -> error -74
Page 15 (0x00007800) -> error -74
Page 16 (0x00008000) -> error -74
Page 17 (0x00008800) -> error -74
Page 18 (0x00009000) -> error -74
Page 19 (0x00009800) -> error -74
Page 20 (0x0000a000) -> error -74
Page 21 (0x0000a800) -> error -74
Page 22 (0x0000b000) -> error -74
Page 23 (0x0000b800) -> error -74
Page 1110 (0x0022b000) -> up to 1 bf/chunk
Page 1122 (0x00231000) -> up to 1 bf/chunk
Page 1132 (0x00236000) -> up to 1 bf/chunk
Page 1362 (0x002a9000) -> up to 1 bf/chunk
Page 4990 (0x009bf000) -> up to 1 bf/chunk
Page 5728 (0x00b30000) -> up to 1 bf/chunk
Page 7116 (0x00de6000) -> up to 1 bf/chunk
Page 7160 (0x00dfc000) -> up to 1 bf/chunk
Page 7494 (0x00ea3000) -> up to 1 bf/chunk
Page 10842 (0x0152d000) -> up to 1 bf/chunk
Page 11614 (0x016af000) -> up to 1 bf/chunk
Page 11970 (0x01761000) -> up to 1 bf/chunk
Page 12536 (0x0187c000) -> up to 1 bf/chunk
Page 12687 (0x018c7800) -> up to 1 bf/chunk
Page 14298 (0x01bed000) -> up to 1 bf/chunk
Page 18268 (0x023ae000) -> up to 1 bf/chunk
Page 18760 (0x024a4000) -> up to 1 bf/chunk
Page 21440 (0x029e0000) -> up to 1 bf/chunk
Page 22336 (0x02ba0000) -> up to 1 bf/chunk
Page 22592 (0x02c20000) -> up to 1 bf/chunk
Page 23872 (0x02ea0000) -> up to 1 bf/chunk
Page 27584 (0x035e0000) -> up to 1 bf/chunk
Page 35008 (0x04460000) -> up to 1 bf/chunk
Page 37184 (0x048a0000) -> up to 1 bf/chunk
Page 41728 (0x05180000) -> up to 1 bf/chunk
Page 42176 (0x05260000) -> up to 1 bf/chunk
Page 43200 (0x05460000) -> up to 1 bf/chunk
Page 43328 (0x054a0000) -> up to 1 bf/chunk
Page 45376 (0x058a0000) -> up to 1 bf/chunk
Page 47040 (0x05be0000) -> up to 1 bf/chunk
Page 47552 (0x05ce0000) -> up to 1 bf/chunk
Page 49344 (0x06060000) -> up to 1 bf/chunk
Page 49856 (0x06160000) -> up to 1 bf/chunk
Page 62784 (0x07aa0000) -> up to 1 bf/chunk
Page 65153 (0x07f40800) -> up to 1 bf/chunk
Page 65228 (0x07f66000) -> up to 1 bf/chunk
Page 65382 (0x07fb3000) -> up to 1 bf/chunk
Page 98624 (0x0c0a0000) -> up to 1 bf/chunk
Page 101952 (0x0c720000) -> up to 1 bf/chunk
Page 107584 (0x0d220000) -> up to 1 bf/chunk
Page 118208 (0x0e6e0000) -> up to 1 bf/chunk
Page 126656 (0x0f760000) -> up to 1 bf/chunk
Page 127680 (0x0f960000) -> up to 1 bf/chunk
Page 129920 (0x0fdc0000) -> up to 1 bf/chunk
Maximum number of bitflips: 1
Pages with bitflips: 44/130752
It is also possible to reduce the output with the .quiet suffix in order
to just show the summary.
=> nand watch.chip
device 0 whole chip
size adjusted to 0xff60000 (5 bad blocks)
NAND watch for bitflips in area 0x0-0xff60000:
Maximum number of bitflips: 1
Pages with bitflips: 44/130752
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Patrice Chotard [Fri, 13 Dec 2024 13:26:55 +0000 (14:26 +0100)]
ARM: stm32mp: Fix dram_bank_mmu_setup() for LMB located above ram_top
Previously, all LMB marked with LMB_NOMAP (above and below ram_top)
are considered as invalid entry in TLB.
Since commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top
even from same bank") all LMB located above ram_top are now marked
LMB_NOOVERWRITE and no more LMB_MAP.
This area above ram_top is reserved for OPTEE and must not be cacheable,
otherwise this leads to a Panic on some boards (Issue on STM32MP135F-DK).
Restore previous behavior by marking invalid entry all TLB above ram_top.
Fixes: 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
cc: Sughosh Ganu <sughosh.ganu@linaro.org> Acked-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Simon Glass [Wed, 11 Dec 2024 13:18:58 +0000 (06:18 -0700)]
test/py: Always use the current dir as the source tree
The logic in get_details() retrieves the default source directory from
the Labgrid settings. This is convenient for interactive use, since it
allows pytests to be run from any directory and still find the source
tree.
However, it is not actually correct.
Gitlab sets the current directory to the source tree and expects that to
be used. At present it is ignored. The result is that Gitlab builds
whatever happens to be in the default source directory, ignoring the
tree it is supposed to be building.
Fix this by using the directory of the source tree, always. This is
obtained by looking at the grandparent of the conftest.py file.
Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Tom Rini <trini@konsulko.com> Fixes: bf89a8f1fc2 ("test: Introduce the concept of a role") Tested-by: Tom Rini <trini@konsulko.com>
Svyatoslav Ryhel [Fri, 13 Dec 2024 14:53:19 +0000 (16:53 +0200)]
driver: clk: tegra: init basic clocks on probe
In case DM drivers probe earlier than board clock setup is done
init of basic clocks should be done in CAR driver probe as well.
Add it to avoid possible clock related problems.
Christoph Fritz [Mon, 16 Dec 2024 14:59:00 +0000 (15:59 +0100)]
imx: hab: fix srktool -c usage by removing spaces
The srktool option -c does not allow spaces between certificate
filenames. Only commas (',') should separate the filenames. If spaces
are incorrectly included, srktool will not display an error or warning
message but will only process the first certificate in the list.
So adapt documentation accordingly.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Ronald Wahl [Wed, 11 Dec 2024 20:52:00 +0000 (21:52 +0100)]
mmc: Fix potential timer value truncation
On 64bit systems the timer value might be truncated to a 32bit value
causing malfunctions. For example on ARM the timer might start from 0
again only after a cold reset. The 32bit overflow occurs after a bit
more than 49 days (1000 Hz counter) so booting after that time may lead
to a surprise because the board might become stuck requiring a cold
reset.
Signed-off-by: Ronald Wahl <ronald.wahl@legrand.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Peng Fan [Tue, 3 Dec 2024 13:42:57 +0000 (21:42 +0800)]
smbios: address build warning
include display_options.h to address build warning:
lib/smbios.c: In function ‘smbios_update_version’:
lib/smbios.c:305:9: warning: implicit declaration of function ‘print_buffer’
[-Wimplicit-function-declaration]
print_buffer((ulong)ptr, ptr, 1, old_len + 1, 0);
^~~~~~~~~~~~
Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
bios_emulator: fix incorrect printing of address in "jump near immediate"
In the x86emuOp_jump_call_near_IMM() function the target address is
printed incorrectly when jumping backwards. For example instead of
"jmp 0xe8bc" the string "jmp ffffe8bc" is printed. That's because
of the following macro:
Yuri Zaporozhets [Sat, 30 Nov 2024 20:56:25 +0000 (21:56 +0100)]
bios_emulator: fix incorrect printing of address in "call near immediate"
In the x86emuOp_call_near_IMM() function the address of CALL is
printed incorrectly when jumping backwards. For example, the correct
disassemble of the bytes below would be:
Yuri Zaporozhets [Tue, 26 Nov 2024 23:29:53 +0000 (00:29 +0100)]
bios_emulator: fix garbled printing of disassembled SET* instructions
When DEBUG_DECODE_F is enabled in bios_emulator, the printing of
SET{O,NO,B,NB,Z,NZ,BE,NBE,S,NS,P,TP,L,NL,LE,NLE} instructions
is not followed by newline and is, therefore, immediately followed
by the printed address of a new instruction. This garbles the output
and makes it very difficult to read.
This patch adds missing DECODE_PRINTF("\n") calls to print newlines.
Yuri Zaporozhets [Tue, 26 Nov 2024 21:59:37 +0000 (22:59 +0100)]
bios_emulator: fix garbled printing of disassembled BSF instruction
When DEBUG_DECODE_F is enabled in bios_emulator, the printing of BSF
instructions is garbled because the '\n' symbol is used instead of
the correct '\t'. Fix that.
Currently if a gigabit-capable PHY is connected to FEC via RMII or MII, it
will advertise 1000FULL and 1000HALF to a link partner.
Different problems may arise here:
- usually with (R)MII between MAC and PHY the PHY's connection to magnetics
would have only 2 pairs routed as well, otherwise a PHY can negotiate 1000
speed and there will be no traffic possible;
- but even if there is no way to negotiate 1000 speed in HW (only 2 signal
pairs routed), it may take a lot of time for PHY to figure this out; in
case of AD1300 it takes 17-20 seconds, which is waay longer than default
4s PHY_ANEG_TIMEOUT.
Use phy_set_supported() in such cases to disable gigabit advertised
options.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
imx: mach: imx8: fdt: set correct frequencies for the industrial SoC
Set correct CPU and GPU frequencies for the industrial i.MX8 SoC
variant.
Ensure that the CPU and GPU frequencies are properly configured for the
industrial variant of the SoC. According to the "i.MX 8QuadMax
Industrial Applications Processors" datasheet, the frequency limits for
this variant are as follows:
- Cortex-A72: 1.296 GHz
- Cortex-A53: 1.104 GHz
- GPU core: 625 MHz
- GPU shader: 625 MHz
The CPU clock is enforced by the System Controller Firmware (SCFW), but
the cpufreq driver is unaware of this enforcement. By removing
unsupported frequencies from the operating points, we ensure that the
cpufreq driver aligns correctly with the SCFW's settings.
The GPU frequency, on the other hand, is not enforced by the SCFW. As a
result, the GPU could potentially be overclocked. To prevent this, we
set the correct clock frequency and update the operating points
accordingly, ensuring compliance with the datasheet specifications.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
toradex: apalis-imx8: simplify module version handling
Simplify module version handling by removing the special case for the
Apalis iMX8QM.
The Apalis iMX8QM has been treated as a special case in module version
handling, but was always the default. By removing this special handling,
the code is simplified and easier to maintain.
We will not print the message "Unknown Apalis iMX8 module" anymore.
However, we still handle this because if the config block is missing we
show "MISSING TORADEX CONFIG BLOCK" and if the serial number is unknown
we show "Model: Toradex 0000 UNKNOWN MODULE V1.1A". Therefore, it is
still possible to detect such issues.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
projects / thirdparty / u-boot.git / log
