Petar Jovanovic [Tue, 9 May 2017 15:57:59 +0000 (15:57 +0000)]
mips: reduce compiler warnings
Compiler complained about
warning: implicit declaration of function ‘vgPlain_prctl’
in coregrind/m_machine.c.
Also, it complained about
warning: no previous prototype for ‘vgSysWrap_mips_linux_sys_ptrace_before’
[-Wmissing-prototypes]
warning: no previous prototype for ‘vgSysWrap_mips_linux_sys_ptrace_after’
[-Wmissing-prototypes]
Carl Love [Wed, 3 May 2017 17:28:35 +0000 (17:28 +0000)]
PPC64 ISA 3.0B, add support for the additional instructions: addex, mffscdrn,
mffscdrni, mffsce, mffscrn, mffscrni, mffsl. vmsumudm.
Additionally, the OV32 and CA32 bits were introduced in ISA 3.0 but
Valgrind add support for setting these bits for ISA 3.0. The OV32 and CA32
bits must now be set on a number of pre ISA 3.0 instructions. So now the
instructions produce different results in the XER register. Thus we need pre
and post ISA 3.0 expect files. Command line options were added to thee
pre ISA test cases so instructions that didn't change could be run with one
set of command line args. The instructions that have different XER results
are run using a different set of command line args. The tests were split into
two, one for instructions that didn't change on for instructions that do
change under ISA 3.0. We then create ISA3.0 expect files only for the tests
that run differently. By doing this we minimized the size of the expect files
needed.
Vex commit 3359 Has the source code changes for the instruction and OV32, CS32
support
This commit is all the test case changes, adding the new test case files.
Carl Love [Wed, 3 May 2017 17:24:55 +0000 (17:24 +0000)]
PPC64 ISA 3.0B, add support for the additional instructions: addex, mffscdrn,
mffscdrni, mffsce, mffscrn, mffscrni, mffsl. vmsumudm.
Additionally, the OV32 and CA32 bits were introduced in ISA 3.0 but
Valgrind add support for setting these bits for ISA 3.0. The OV32 and CA32
bits must now be set on a number of pre ISA 3.0 instructions. So now the
instructions produce different results in the XER register. Thus we need pre
and post ISA 3.0 expect files. Command line options were added to thee
pre ISA test cases so instructions that didn't change could be run with one
set of command line args. The instructions that have different XER results
are run using a different set of command line args. The tests were split into
two, one for instructions that didn't change on for instructions that do
change under ISA 3.0. We then create ISA3.0 expect files only for the tests
that run differently. By doing this we minimized the size of the expect files
needed.
Rhys Kidd [Sat, 29 Apr 2017 22:06:20 +0000 (22:06 +0000)]
macos: Improve macOS 10.12 support. bz#365327.
The new macOS 10.12 way of loading dylib (placing them at the end of the currently
loaded segments) requires that Valgrind needs to know where the last segment was loaded.
A new structure (load_info_t) has been created to store all this information and easily
carry it around.
Changes:
- dyld text address is relative instead of absolute (macOS 10.12)
- Handle dylinker's offset (macOS 10.12)
- Handle the executable requesting a non-default stack address (macOS 10.12)
- Refactor to use load_info_t structure (all macOS)
Petar Jovanovic [Tue, 25 Apr 2017 14:40:54 +0000 (14:40 +0000)]
mips: limit cvt.s.l instruction translation to fp_mode64
The documentation says:
"For CVT.S.L, the result of this instruction is UNPREDICTABLE if the
processor is executing in the FR=0 32-bit FPU register model; it is
predictable if executing on a 64-bit FPU in the FR=1 mode, but not with
FR=0, and not on a 32-bit FPU."
Bug 369459 - valgrind on arm64 violates the ARMv8 spec (ldxr/stxr)
This implements a fallback LL/SC implementation as described in bug 344524.
The fallback implementation is not enabled by default, and there is no
auto-detection for when it should be used. To use it, run with the
flag --sim-hints=fallback-llsc. This commit also allows the existing
MIPS fallback implementation to be enabled with that flag.
VEX side changes:
* priv/main_main.c, pub/libvex.h
Adds new field guest__use_fallback_LLSC to VexAbiInfo
Have a cleaner way to remove the massif preload from LD_PRELOAD.
The previous code was removing the massif preload (when --pages-as-heap=yes)
by replacing the entry with spaces.
This is not very clear, and I suspect this gives problems with the
android linker, which seems to use such a space entry as a real entry
to load (and then fails to start the application).
This patch really removes the entry, by shifting the characters.
Petar Jovanovic [Thu, 13 Apr 2017 16:33:06 +0000 (16:33 +0000)]
add additional stderr.exp file for helgrind/tests/pth_destroy_cond
On some platforms, Helgrind detects valid additional data race over "cond".
Thread one is at pthread_cond_wait(&cond, &mutex).
Thread two is at pthread_cond_destroy(&cond).
This fixes helgrind/tests/pth_destroy_cond on different platforms.
Petar Jovanovic [Thu, 13 Apr 2017 16:11:54 +0000 (16:11 +0000)]
increase heuristic-fence-post limit for gdbserver_tests/mcmain_pic
GDB reports to be "unable to find the start of the function" and suggests
increasing the range of the search using the 'set heuristic-fence-post'
command. So we did.
It fixes gdbserver_tests/mcmain_pic on some platforms.
Petar Jovanovic [Wed, 12 Apr 2017 17:51:45 +0000 (17:51 +0000)]
fix early initialization of s390_host_hwcaps in LibVEX_FrontEnd
This is a follow-up to r3341 and r3344. r3341 split LibVEX_Translate into
LibVEX_FrontEnd and LibVEX_BackEnd. s390_host_hwcaps needs to be initialized
early when arch_host is VexArchS390X.
This also fixes none/tests/libvexmultiarch_test on MIPS64 BE platforms.
Mark Wielaard [Wed, 12 Apr 2017 13:01:29 +0000 (13:01 +0000)]
Update libiberty demangler.
Update the libiberty demangler using the auxprogs/update-demangler
script to the gcc svn r246502 revision. Replaces our rust demangling
with the upstream variant (which is basically the same code in a
separate file). Adds handling of inheriting constructor. Handle
noexcept and throw-spec. Demangle Dc as decltype(auto). And various
(crasher) bug fixes.
Mark VPMULHRSW ymm3/m256, ymm2, ymm1 as a "verbose instruction". This
pertains to failures documented at https://bugs.kde.org/show_bug.cgi?id=375839
comments 10 to 18.
Mark Wielaard [Tue, 4 Apr 2017 12:02:14 +0000 (12:02 +0000)]
Initialize s390_host_hwcaps early in LibVEX_FrontEnd.
VEX svn r3341 split LibVEX_Translate into LibVEX_FrontEnd and
LibVEX_BackEnd. The s390_host_hwcaps (KLUDGE) needs to be initialized
early in LibVEX_FrontEnd.
Petar Jovanovic [Mon, 3 Apr 2017 14:30:13 +0000 (14:30 +0000)]
mips64: sign-extend results from dirty helper
Values returned from the dirty helper may not be sign-extended, so let's
make sure the values get passed as sign-extended for Ity_I32, Ity_I16, and
Ity_I8 cases.
At the same time, we can remove now redundant sign-extensions introduced in
VEX r3304.
This fixes memcheck/test/bug340392 on some MIPS64 boards.
Split LibVEX_Translate into front- and back-end parts. Also, removes use
of __typeof__ when built with MSVC. A combination of parts of two patches
from Andrew Dutcher <andrewrdutcher@gmail.com>.
x86 guest: switch descriptor table registers to ULong type so they will take up
consistent amount of space (VEX side). Andrew Dutcher <andrewrdutcher@gmail.com>.
Julian Seward [Thu, 30 Mar 2017 12:14:23 +0000 (12:14 +0000)]
Bug 358697 - valgrind.h: Some code remains even when defining NVALGRIND.
Patch from Matthias Schwarzott (zzam@gentoo.org). The patch removes
a volatile memory read which was only there to stop compilers warning
about |format| being unused.
Julian Seward [Wed, 29 Mar 2017 16:13:35 +0000 (16:13 +0000)]
Add a mechanism for hinting to the core disassembler loop, that the
just-disassembled instruction is very verbose. This allows dynamic changes to
the maximum number of guest instructions allowed in the current IRSB.
Fixes #375839.
This is in support of "Bug 375839 - Temporary storage exhausted, when long
sequence of vfmadd231ps instructions to be executed", and reduces code size by
around 3% in that case.
Julian Seward [Mon, 27 Mar 2017 18:32:10 +0000 (18:32 +0000)]
Rewrite dis_FMA so it generates not-quite-so-terrible code. It's still terrible
(breaks vectors into scalars) but this rewrite does it in a way which makes it
interact better with put-to-get forwarding. It also removes all the
Iop_Reinterp casting involved. For long sequences of FMA instructions this
reduces the amount of memcheck-generated code to about 75% of what it was
before. Improves the situation for
Bug 375839 - Temporary storage exhusted , when long sequence of vfmadd231ps instructions to be executed
but isn't a convincing fix.
Ivo Raisr [Fri, 24 Mar 2017 13:46:15 +0000 (13:46 +0000)]
Use consistently chase1() in MSVC specific transformation hacks.
This code is experimental and not used by default but should be self-consistent.
n-i-bz
Ivo Raisr [Thu, 23 Mar 2017 23:22:21 +0000 (23:22 +0000)]
Fix for 377698 - Missing memory check for futex() uaddr arg for FUTEX_WAKE,
and FUTEX_WAKE_BITSET, check only 4 args for FUTEX_WAKE_BITSET,
and 2 args for FUTEX_TRYLOCK_PI.
Fixes BZ#377698.
Patch by: diane.meirowitz@oracle.com
Julian Seward [Mon, 20 Mar 2017 21:34:02 +0000 (21:34 +0000)]
Bug 377717 - Fix massive space leak when reading compressed debuginfo sections.
This makes reading of compressed debuginfo usable for very large object files.
It also adds a bunch extra documentation about a tricky invariant in the
compressed debuginfo handling (a recursive cache refill path!) and adds a
whole bunch of assertions.
Follow up to fix 376956 syswrap of SNDDRV and DRM_IOCTL_VERSION causing some
addresses to be wrongly marked as addressable
As noted by Ivo, if the syscall fails, then we have a leak.
So, enable the flag SfPostOnFail if we allocate memory.
In the POST ioctl, check that FAILURE only happens for this drm ioctl,
and free the memory for both SUCCESS and FAILURE.
Do the POST_MEM_WRITE only if SUCCESS
Add missing break for the DRM ioctl operations that do not have any args
Due to this missing break, the code was falling through to
the case VKI_SNDRV_CTL_IOCTL_PVERSION:
and was then setting some bytes as defined at (whatever address is in) ARG3.
The lfdpx, stdpx, lfdp and stfdp instructions work on a register pair. The
register pair test must only be applied to these instructions in the
dis_fp_pair() function.
Updating NEWS file for the commit
VEX commit 3308 makes the fix in VEX/priv/guest_ppc_toIR.c
The lfdpx, stdpx, lfdp and stfdp instructions work on a register pair. The
register pair test must only be applied to these instructions in the
dis_fp_pair() function.
projects / thirdparty / valgrind.git / log
