Florian Krohm [Sun, 14 Oct 2012 00:16:28 +0000 (00:16 +0000)]
Char/ HChar cleanup: The various panic and printf-like functions
all take const HChar * arguments.
__FILE__ and __func__ expand into string literals (or character
arrays initialised by them), as do strings created by the preprocessor
e.g. #stuff.
This change reduces the number of warnings from 17000+ to ~5500
Some wrong options silently ignored if starting with same letters as valid option
For example, options below are silently "accepted"+ignored:
valgrind --profile-heaps=yes --max-stackframes=35 memcheck/tests/trivialleak
valgrind --profile-heaps=oui --max-stackframes=3.141592654 memcheck/tests/trivialleak
Also fixed the on-line --help output for option --core-redzone-size
Florian Krohm [Sun, 7 Oct 2012 21:59:42 +0000 (21:59 +0000)]
This is the 2nd installment of the cache info reorganisation.
The host's VexArchInfo is passed to the tool instrumentation
functions. Purely mechanic patch.
Florian Krohm [Sun, 7 Oct 2012 19:47:04 +0000 (19:47 +0000)]
This patch is the first installment of the cache info reorganisation.
It's reorg only. No new cache autodetection stuff has been added.
coregrind
pub_tool_cpuid.h is removed as it is no longer exposed to tools.
Its contents has moved to pub_core_cpuid.h.
New file: coregrind/m_cache.c to contain the autodetect code for
cache configurations and define other cache characteristics that
cannot be autodetected (i.e. icaches_maintain_coherence). Most of
cg-arch/x86-amd64.c was moved here. The cache detection code for
x86-64 needs to be fixed to properly initialise VexCacheInfo. It
currently has cachegrind bias.
m_cache.c exports a single function (to coregrind):
VG_(machine_get_cache_info)(VexArchInfo *vai)
This function is called from VG_(machine_get_hwcaps) after hwcaps have
been detected.
cachegrind
Remove cachegrind/cg-{ppc32,ppc43,arm,mips32,s390x,x86-amd64}.c
With the exception of x86/mamd64 those were only establishing a
default cache configuration and that is so small a code snippet that
a separate file is no longer warranted. So, the code was moved to
cg-arch.c. Code was added to extract the relevant info from
x86-amd64.
New function maybe_tweak_LLc which captures the code to massage the
LLc cache configuration into something the simulator can handle. This
was originally in cg-x86-amd64.c but should be used to all architectures.
Changed warning message about missing cache auto-detect feature
to be more useful. Adapted filter-stderr scripts accordingly.
Florian Krohm [Sun, 7 Oct 2012 19:44:40 +0000 (19:44 +0000)]
Add data structures for cache representation to libvex.h:
VexCacheInfo, VexCache, and VexCacheKind.
VexArchInfo gets a VexCacheInfo member which LibVEX_default_VexArchInfo
initialises.
Florian Krohm [Sun, 7 Oct 2012 15:42:37 +0000 (15:42 +0000)]
s390: This is a pre-patch for DFP support. It renames certain
identifiers to explicitly refer to BFP, as there will be counterparts
in the future for DFP.
Patch by Maran <maranp@linux.vnet.ibm.com>.
Part of fixing #307113.
Petar Jovanovic [Thu, 4 Oct 2012 23:53:03 +0000 (23:53 +0000)]
Change uname based arch-check to match machine hardware name in sgcheck.
Some hardware platforms will return "unknown" for 'uname -i', so it is more
accurate and common to run 'uname -m' which returns machine hardware name.
This way, some platforms that do not support sgcheck will avoid running tests
for it.
Unbreak build on ppc64 (error: ‘EmWarn_PPC64_redir_underflow’ undeclared)
coregrind/m_translate.c does not compile on ppc64 (ppc32 maybe also?)
due to missing include file.
Note: libvex_emnote.h is unconditionally included, even if only
useful for ppc. I suppose we do not want #ifdef for that.
Make header files compilable by itself to get two benefits:
- never have to worry about order of inclusion
- never have to figure out hidden dependencies in order to be
able to include a file
Change the return value of LibVEX_{Chain,UnChain,PatchProfInc}.
These functions now always return the address range that was
patched. Therefore, these functions no longer need knowledge
about I-cache coherency of the host system.
fix n-i-bz report error for vgdb snapshot requested before execution
Massif does not accept to take snapshots of heap before execution has started.
So, if such a snapshot is requested (using vgdb and option --vgdb-error=0),
then such a snapshot must be refused rather than causing an assert.
(problem reported by dark_footix@yahoo.fr)
Unbreak build on Mac_OS where __NR_mprotect is not defined.
The test is not executed on Darwin but should compile.
(based on fix suggestion by Rich Coe)
Petar Jovanovic [Fri, 21 Sep 2012 22:44:45 +0000 (22:44 +0000)]
A new post.exp file that provides more details for overloaded-new test.
Valgrind for MIPS will give more details on the heap allocation functions
(operator new) than the existing post.exp presents.
This fixes massif/tests/overloaded-new for MIPS and likely other arch if they
provide the info.
Petar Jovanovic [Fri, 21 Sep 2012 00:06:14 +0000 (00:06 +0000)]
Shorten the list of allocable registers for MIPS to fit Loongson MIPS32 mode.
In order to fit MIPS32 mode on Loongson and work around its issues, we avoid
use of odd single precision FP registers. This results in expected execution/
results of some FPU instructions on Loongson. Running FPU intensive tests has
not shown any performance decrease after the change is introduced.
Petar Jovanovic [Wed, 19 Sep 2012 12:48:09 +0000 (12:48 +0000)]
Another exp file for tc23_bogus_condwait.c.
struct pthread_mutex_t is different on MIPS32 and x86_64, and thus passing a
bogus mutex pthread_cond_wait (line 72) will corrupt memory in a different way
on two platforms. This causes the subsequent call to pthread_cond_wait to fail
on MIPS and i386 but not on x86_64.
This change fixes helgrind/tests/tc23_bogus_condwait on MIPS and i386.
Petar Jovanovic [Wed, 19 Sep 2012 11:51:31 +0000 (11:51 +0000)]
Adding tc19_shadowmem.stderr.exp-mips32 to match different output.
Writing to a double is done via two store-word instructions on MIPS platforms.
Thus, Helgrind will report "Possible data race during write of size 4" twice on
subsequent locations on MIPS instead of a single "Possible data race during
write of size 8". New exp file is added to cover this case.
This fixes helgrind/tests/tc19_shadowmem on MIPS.
Petar Jovanovic [Tue, 18 Sep 2012 21:02:59 +0000 (21:02 +0000)]
Add exp file for tc20_verifywrap due to different errno values on MIPS.
Different error numbers on MIPS require us to add an extra exp file for this
test. EDEADLK is 45 on MIPS (and not 35), and EOPNOTSUPP is 122 (and not 95).
Furthermore, sem_post will pass due to different implementation on MIPS (in
comparison to x86_64), and thus one error less has to be reported in the log.
STM<c>.W <Rn>{!},<registers> (Encoding T2): allow the base register to
appear in the list in any position, provided that writeback is not
selected. Fixes #306297.
Be more flexible by allowing the compile command to be prefixed,
e.g. ccache gcc whatever... This fixes bugzilla #252955.
Patch from Stephen McCamant <smcc@CS.Berkeley.EDU>.
Petar Jovanovic [Sat, 15 Sep 2012 02:36:21 +0000 (02:36 +0000)]
Adding new exp file for tc18_semabuse in helgrind.
The existing tc18_semabuse.stderr.exp expects that sem_post on a bogus semaphore
will fail, yet it does not on platforms such as MIPS or ARM. This is specific to
implementation of sem_post for i386/x86_64 that has some assumptions such as that
'private' field is not clobbered. This will eventually result in different
parameter passed to syscall and thus different output is encountered.
This change fixes helgrind/tests/tc18_semabuse for MIPS.
Add a test which checks the leak search recovery mechanism
The leak search must recover if unreadable pages are scanned.
This test creates such unreadable pages by doing non SIMD mprotect
syscall (not seen by the aspacemgr).
Adjust the vbit tester to deal with shift operations that require
an immediate constant as the shift amount. This is needed for
powerpc Iop_ShlD64 etc. What it basically means that we do not
iterate over the bits in the 2nd operand because there are no
V-bits to set. An immediate constant is always completely defined.
Fixes bugzilla #305948.
Tweak the IR injector so it can handle an immediate operand for
shift operations. This is needed for Iop_ShlD64 and the like on
powerpc where the shift amount is an immediate field in the insn.
Part of fixing bugzilla #305948.
s390: Change the handling of S390_ROUND_PER_FPC (which indicates that the
actual rounding mode is to be taken from the FPC register). Previously, this
was just mapped to S390_ROUND_NEAREST_EVEN, which obviously has correctness
issues.
First, we add a function get_bfp_rounding_mode_from_fpc to extract the
rounding mode from the guest FPC when building IR.
Second, have encode_bfp_rounding_mode invoke get_bfp_rounding_mode_from_fpc
whenever a S390_ROUND_PER_FPC is requested.
Third, in insn selection track whether (and if so to what value) the
rounding mode was set for the IRSB at hand. That way redundant assignments
can be avoided. This works well because the IR optimiser do a fine job
recognising end eliminating the expressions returned earlier from
get_bfp_rounding_more_from_fpc. So they get all mapped to the same IRTemp.
Note, VEX r2524 is essential to get this behaviour.
Fourth, remove the rounding more from the bfp_unop/binop/triop s390_insns.
Fifth, if the rounding mode can be set on the insn directly, prefer that
over setting it in the FPC and picking it up from there.
projects / thirdparty / valgrind.git / log
