]> git.ipfire.org Git - thirdparty/kernel/linux.git/blob
projects / thirdparty / kernel / linux.git / blob
? search:


4.0.0-next-20150424-sasha-00037-g4796e21
[thirdparty/kernel/linux.git] /
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TI CAL camera interface driver
4 *
5 * Copyright (c) 2015 Texas Instruments Inc.
6 * Benoit Parrot, <bparrot@ti.com>
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/ioctl.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/of_graph.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <linux/videodev2.h>
24
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-common.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-event.h>
30 #include <media/v4l2-fh.h>
31 #include <media/v4l2-fwnode.h>
32 #include <media/v4l2-ioctl.h>
33 #include <media/videobuf2-core.h>
34 #include <media/videobuf2-dma-contig.h>
35
36 #include "cal_regs.h"
37
38 #define CAL_MODULE_NAME "cal"
39
40 MODULE_DESCRIPTION("TI CAL driver");
41 MODULE_AUTHOR("Benoit Parrot, <bparrot@ti.com>");
42 MODULE_LICENSE("GPL v2");
43 MODULE_VERSION("0.1.0");
44
45 static unsigned video_nr = -1;
46 module_param(video_nr, uint, 0644);
47 MODULE_PARM_DESC(video_nr, "videoX start number, -1 is autodetect");
48
49 static unsigned debug;
50 module_param(debug, uint, 0644);
51 MODULE_PARM_DESC(debug, "activates debug info");
52
53 #define cal_dbg(level, cal, fmt, arg...) \
54 do { \
55 if (debug >= (level)) \
56 dev_printk(KERN_DEBUG, &(cal)->pdev->dev, \
57 fmt, ##arg); \
58 } while (0)
59 #define cal_info(cal, fmt, arg...) \
60 dev_info(&(cal)->pdev->dev, fmt, ##arg)
61 #define cal_err(cal, fmt, arg...) \
62 dev_err(&(cal)->pdev->dev, fmt, ##arg)
63
64 #define ctx_dbg(level, ctx, fmt, arg...) \
65 cal_dbg(level, (ctx)->cal, "ctx%u: " fmt, (ctx)->index, ##arg)
66 #define ctx_info(ctx, fmt, arg...) \
67 cal_info((ctx)->cal, "ctx%u: " fmt, (ctx)->index, ##arg)
68 #define ctx_err(ctx, fmt, arg...) \
69 cal_err((ctx)->cal, "ctx%u: " fmt, (ctx)->index, ##arg)
70
71 #define phy_dbg(level, phy, fmt, arg...) \
72 cal_dbg(level, (phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
73 #define phy_info(phy, fmt, arg...) \
74 cal_info((phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
75 #define phy_err(phy, fmt, arg...) \
76 cal_err((phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg)
77
78 #define CAL_NUM_CONTEXT 2
79
80 #define MAX_WIDTH_BYTES (8192 * 8)
81 #define MAX_HEIGHT_LINES 16383
82
83 /* ------------------------------------------------------------------
84 * Format Handling
85 * ------------------------------------------------------------------
86 */
87
88 struct cal_fmt {
89 u32 fourcc;
90 u32 code;
91 /* Bits per pixel */
92 u8 bpp;
93 };
94
95 static const struct cal_fmt cal_formats[] = {
96 {
97 .fourcc = V4L2_PIX_FMT_YUYV,
98 .code = MEDIA_BUS_FMT_YUYV8_2X8,
99 .bpp = 16,
100 }, {
101 .fourcc = V4L2_PIX_FMT_UYVY,
102 .code = MEDIA_BUS_FMT_UYVY8_2X8,
103 .bpp = 16,
104 }, {
105 .fourcc = V4L2_PIX_FMT_YVYU,
106 .code = MEDIA_BUS_FMT_YVYU8_2X8,
107 .bpp = 16,
108 }, {
109 .fourcc = V4L2_PIX_FMT_VYUY,
110 .code = MEDIA_BUS_FMT_VYUY8_2X8,
111 .bpp = 16,
112 }, {
113 .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */
114 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
115 .bpp = 16,
116 }, {
117 .fourcc = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */
118 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
119 .bpp = 16,
120 }, {
121 .fourcc = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */
122 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
123 .bpp = 16,
124 }, {
125 .fourcc = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */
126 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
127 .bpp = 16,
128 }, {
129 .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */
130 .code = MEDIA_BUS_FMT_RGB888_2X12_LE,
131 .bpp = 24,
132 }, {
133 .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */
134 .code = MEDIA_BUS_FMT_RGB888_2X12_BE,
135 .bpp = 24,
136 }, {
137 .fourcc = V4L2_PIX_FMT_RGB32, /* argb */
138 .code = MEDIA_BUS_FMT_ARGB8888_1X32,
139 .bpp = 32,
140 }, {
141 .fourcc = V4L2_PIX_FMT_SBGGR8,
142 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
143 .bpp = 8,
144 }, {
145 .fourcc = V4L2_PIX_FMT_SGBRG8,
146 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
147 .bpp = 8,
148 }, {
149 .fourcc = V4L2_PIX_FMT_SGRBG8,
150 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
151 .bpp = 8,
152 }, {
153 .fourcc = V4L2_PIX_FMT_SRGGB8,
154 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
155 .bpp = 8,
156 }, {
157 .fourcc = V4L2_PIX_FMT_SBGGR10,
158 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
159 .bpp = 10,
160 }, {
161 .fourcc = V4L2_PIX_FMT_SGBRG10,
162 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
163 .bpp = 10,
164 }, {
165 .fourcc = V4L2_PIX_FMT_SGRBG10,
166 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
167 .bpp = 10,
168 }, {
169 .fourcc = V4L2_PIX_FMT_SRGGB10,
170 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
171 .bpp = 10,
172 }, {
173 .fourcc = V4L2_PIX_FMT_SBGGR12,
174 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
175 .bpp = 12,
176 }, {
177 .fourcc = V4L2_PIX_FMT_SGBRG12,
178 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
179 .bpp = 12,
180 }, {
181 .fourcc = V4L2_PIX_FMT_SGRBG12,
182 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
183 .bpp = 12,
184 }, {
185 .fourcc = V4L2_PIX_FMT_SRGGB12,
186 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
187 .bpp = 12,
188 },
189 };
190
191 /* Print Four-character-code (FOURCC) */
192 static char *fourcc_to_str(u32 fmt)
193 {
194 static char code[5];
195
196 code[0] = (unsigned char)(fmt & 0xff);
197 code[1] = (unsigned char)((fmt >> 8) & 0xff);
198 code[2] = (unsigned char)((fmt >> 16) & 0xff);
199 code[3] = (unsigned char)((fmt >> 24) & 0xff);
200 code[4] = '\0';
201
202 return code;
203 }
204
205 /* ------------------------------------------------------------------
206 * Driver Structures
207 * ------------------------------------------------------------------
208 */
209
210 /* buffer for one video frame */
211 struct cal_buffer {
212 /* common v4l buffer stuff -- must be first */
213 struct vb2_v4l2_buffer vb;
214 struct list_head list;
215 };
216
217 struct cal_dmaqueue {
218 struct list_head active;
219 };
220
221 /* CTRL_CORE_CAMERRX_CONTROL register field id */
222 enum cal_camerarx_field {
223 F_CTRLCLKEN,
224 F_CAMMODE,
225 F_LANEENABLE,
226 F_CSI_MODE,
227
228 F_MAX_FIELDS,
229 };
230
231 struct cal_camerarx_data {
232 struct {
233 unsigned int lsb;
234 unsigned int msb;
235 } fields[F_MAX_FIELDS];
236 unsigned int num_lanes;
237 };
238
239 struct cal_data {
240 const struct cal_camerarx_data *camerarx;
241 unsigned int num_csi2_phy;
242 unsigned int flags;
243 };
244
245 /*
246 * The Camera Adaptation Layer (CAL) module is paired with one or more complex
247 * I/O PHYs (CAMERARX). It contains multiple instances of CSI-2, processing and
248 * DMA contexts.
249 *
250 * The cal_dev structure represents the whole subsystem, including the CAL and
251 * the CAMERARX instances. Instances of struct cal_dev are named cal through the
252 * driver.
253 *
254 * The cal_camerarx structure represents one CAMERARX instance. Instances of
255 * cal_camerarx are named phy through the driver.
256 *
257 * The cal_ctx structure represents the combination of one CSI-2 context, one
258 * processing context and one DMA context. Instance of struct cal_ctx are named
259 * ctx through the driver.
260 */
261
262 struct cal_camerarx {
263 void __iomem *base;
264 struct resource *res;
265 struct platform_device *pdev;
266 struct regmap_field *fields[F_MAX_FIELDS];
267
268 struct cal_dev *cal;
269 unsigned int instance;
270
271 struct v4l2_fwnode_endpoint endpoint;
272 struct v4l2_subdev *sensor;
273 unsigned int external_rate;
274 };
275
276 struct cal_dev {
277 struct clk *fclk;
278 int irq;
279 void __iomem *base;
280 struct resource *res;
281 struct platform_device *pdev;
282
283 const struct cal_data *data;
284
285 /* Control Module handle */
286 struct regmap *syscon_camerrx;
287 u32 syscon_camerrx_offset;
288
289 /* Camera Core Module handle */
290 struct cal_camerarx *phy[CAL_NUM_CSI2_PORTS];
291
292 struct cal_ctx *ctx[CAL_NUM_CONTEXT];
293 };
294
295 /*
296 * There is one cal_ctx structure for each camera core context.
297 */
298 struct cal_ctx {
299 struct v4l2_device v4l2_dev;
300 struct v4l2_ctrl_handler ctrl_handler;
301 struct video_device vdev;
302 struct v4l2_async_notifier notifier;
303
304 struct cal_dev *cal;
305 struct cal_camerarx *phy;
306
307 /* v4l2_ioctl mutex */
308 struct mutex mutex;
309 /* v4l2 buffers lock */
310 spinlock_t slock;
311
312 struct cal_dmaqueue vidq;
313
314 /* video capture */
315 const struct cal_fmt *fmt;
316 /* Used to store current pixel format */
317 struct v4l2_format v_fmt;
318 /* Used to store current mbus frame format */
319 struct v4l2_mbus_framefmt m_fmt;
320
321 /* Current subdev enumerated format */
322 const struct cal_fmt *active_fmt[ARRAY_SIZE(cal_formats)];
323 unsigned int num_active_fmt;
324
325 unsigned int sequence;
326 struct vb2_queue vb_vidq;
327 unsigned int index;
328 unsigned int cport;
329 unsigned int virtual_channel;
330
331 /* Pointer pointing to current v4l2_buffer */
332 struct cal_buffer *cur_frm;
333 /* Pointer pointing to next v4l2_buffer */
334 struct cal_buffer *next_frm;
335
336 bool dma_act;
337 };
338
339 static inline struct cal_ctx *notifier_to_ctx(struct v4l2_async_notifier *n)
340 {
341 return container_of(n, struct cal_ctx, notifier);
342 }
343
344 /* ------------------------------------------------------------------
345 * Platform Data
346 * ------------------------------------------------------------------
347 */
348
349 static const struct cal_camerarx_data dra72x_cal_camerarx[] = {
350 {
351 .fields = {
352 [F_CTRLCLKEN] = { 10, 10 },
353 [F_CAMMODE] = { 11, 12 },
354 [F_LANEENABLE] = { 13, 16 },
355 [F_CSI_MODE] = { 17, 17 },
356 },
357 .num_lanes = 4,
358 },
359 {
360 .fields = {
361 [F_CTRLCLKEN] = { 0, 0 },
362 [F_CAMMODE] = { 1, 2 },
363 [F_LANEENABLE] = { 3, 4 },
364 [F_CSI_MODE] = { 5, 5 },
365 },
366 .num_lanes = 2,
367 },
368 };
369
370 static const struct cal_data dra72x_cal_data = {
371 .camerarx = dra72x_cal_camerarx,
372 .num_csi2_phy = ARRAY_SIZE(dra72x_cal_camerarx),
373 };
374
375 static const struct cal_data dra72x_es1_cal_data = {
376 .camerarx = dra72x_cal_camerarx,
377 .num_csi2_phy = ARRAY_SIZE(dra72x_cal_camerarx),
378 .flags = DRA72_CAL_PRE_ES2_LDO_DISABLE,
379 };
380
381 static const struct cal_camerarx_data dra76x_cal_csi_phy[] = {
382 {
383 .fields = {
384 [F_CTRLCLKEN] = { 8, 8 },
385 [F_CAMMODE] = { 9, 10 },
386 [F_CSI_MODE] = { 11, 11 },
387 [F_LANEENABLE] = { 27, 31 },
388 },
389 .num_lanes = 5,
390 },
391 {
392 .fields = {
393 [F_CTRLCLKEN] = { 0, 0 },
394 [F_CAMMODE] = { 1, 2 },
395 [F_CSI_MODE] = { 3, 3 },
396 [F_LANEENABLE] = { 24, 26 },
397 },
398 .num_lanes = 3,
399 },
400 };
401
402 static const struct cal_data dra76x_cal_data = {
403 .camerarx = dra76x_cal_csi_phy,
404 .num_csi2_phy = ARRAY_SIZE(dra76x_cal_csi_phy),
405 };
406
407 static const struct cal_camerarx_data am654_cal_csi_phy[] = {
408 {
409 .fields = {
410 [F_CTRLCLKEN] = { 15, 15 },
411 [F_CAMMODE] = { 24, 25 },
412 [F_LANEENABLE] = { 0, 4 },
413 },
414 .num_lanes = 5,
415 },
416 };
417
418 static const struct cal_data am654_cal_data = {
419 .camerarx = am654_cal_csi_phy,
420 .num_csi2_phy = ARRAY_SIZE(am654_cal_csi_phy),
421 };
422
423 /* ------------------------------------------------------------------
424 * I/O Register Accessors
425 * ------------------------------------------------------------------
426 */
427
428 #define reg_read(dev, offset) ioread32(dev->base + offset)
429 #define reg_write(dev, offset, val) iowrite32(val, dev->base + offset)
430
431 static inline u32 reg_read_field(struct cal_dev *cal, u32 offset, u32 mask)
432 {
433 return FIELD_GET(mask, reg_read(cal, offset));
434 }
435
436 static inline void reg_write_field(struct cal_dev *cal, u32 offset, u32 value,
437 u32 mask)
438 {
439 u32 val = reg_read(cal, offset);
440
441 val &= ~mask;
442 val |= FIELD_PREP(mask, value);
443 reg_write(cal, offset, val);
444 }
445
446 static inline void set_field(u32 *valp, u32 field, u32 mask)
447 {
448 u32 val = *valp;
449
450 val &= ~mask;
451 val |= (field << __ffs(mask)) & mask;
452 *valp = val;
453 }
454
455 static void cal_quickdump_regs(struct cal_dev *cal)
456 {
457 cal_info(cal, "CAL Registers @ 0x%pa:\n", &cal->res->start);
458 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
459 (__force const void *)cal->base,
460 resource_size(cal->res), false);
461
462 if (cal->ctx[0]) {
463 cal_info(cal, "CSI2 Core 0 Registers @ %pa:\n",
464 &cal->ctx[0]->phy->res->start);
465 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
466 (__force const void *)cal->ctx[0]->phy->base,
467 resource_size(cal->ctx[0]->phy->res),
468 false);
469 }
470
471 if (cal->ctx[1]) {
472 cal_info(cal, "CSI2 Core 1 Registers @ %pa:\n",
473 &cal->ctx[1]->phy->res->start);
474 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
475 (__force const void *)cal->ctx[1]->phy->base,
476 resource_size(cal->ctx[1]->phy->res),
477 false);
478 }
479 }
480
481 /* ------------------------------------------------------------------
482 * CAMERARX Management
483 * ------------------------------------------------------------------
484 */
485
486 static u32 cal_camerarx_max_lanes(struct cal_camerarx *phy)
487 {
488 return phy->cal->data->camerarx[phy->instance].num_lanes;
489 }
490
491 static void cal_camerarx_enable(struct cal_camerarx *phy)
492 {
493 u32 max_lanes;
494
495 regmap_field_write(phy->fields[F_CAMMODE], 0);
496 /* Always enable all lanes at the phy control level */
497 max_lanes = (1 << cal_camerarx_max_lanes(phy)) - 1;
498 regmap_field_write(phy->fields[F_LANEENABLE], max_lanes);
499 /* F_CSI_MODE is not present on every architecture */
500 if (phy->fields[F_CSI_MODE])
501 regmap_field_write(phy->fields[F_CSI_MODE], 1);
502 regmap_field_write(phy->fields[F_CTRLCLKEN], 1);
503 }
504
505 static void cal_camerarx_disable(struct cal_camerarx *phy)
506 {
507 regmap_field_write(phy->fields[F_CTRLCLKEN], 0);
508 }
509
510 /*
511 * Errata i913: CSI2 LDO Needs to be disabled when module is powered on
512 *
513 * Enabling CSI2 LDO shorts it to core supply. It is crucial the 2 CSI2
514 * LDOs on the device are disabled if CSI-2 module is powered on
515 * (0x4845 B304 | 0x4845 B384 [28:27] = 0x1) or in ULPS (0x4845 B304
516 * | 0x4845 B384 [28:27] = 0x2) mode. Common concerns include: high
517 * current draw on the module supply in active mode.
518 *
519 * Errata does not apply when CSI-2 module is powered off
520 * (0x4845 B304 | 0x4845 B384 [28:27] = 0x0).
521 *
522 * SW Workaround:
523 * Set the following register bits to disable the LDO,
524 * which is essentially CSI2 REG10 bit 6:
525 *
526 * Core 0: 0x4845 B828 = 0x0000 0040
527 * Core 1: 0x4845 B928 = 0x0000 0040
528 */
529 static void cal_camerarx_i913_errata(struct cal_camerarx *phy)
530 {
531 u32 reg10 = reg_read(phy, CAL_CSI2_PHY_REG10);
532
533 set_field(&reg10, 1, CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK);
534
535 phy_dbg(1, phy, "CSI2_%d_REG10 = 0x%08x\n", phy->instance, reg10);
536 reg_write(phy, CAL_CSI2_PHY_REG10, reg10);
537 }
538
539 /*
540 * Enable the expected IRQ sources
541 */
542 static void cal_camerarx_enable_irqs(struct cal_camerarx *phy)
543 {
544 u32 val;
545
546 const u32 cio_err_mask =
547 CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK |
548 CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK |
549 CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK |
550 CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK;
551
552 /* Enable CIO error irqs */
553 reg_write(phy->cal, CAL_HL_IRQENABLE_SET(0),
554 CAL_HL_IRQ_CIO_MASK(phy->instance));
555 reg_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance),
556 cio_err_mask);
557
558 /* Always enable OCPO error */
559 reg_write(phy->cal, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_OCPO_ERR_MASK);
560
561 /* Enable IRQ_WDMA_END 0/1 */
562 val = 0;
563 set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
564 reg_write(phy->cal, CAL_HL_IRQENABLE_SET(1), val);
565 /* Enable IRQ_WDMA_START 0/1 */
566 val = 0;
567 set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
568 reg_write(phy->cal, CAL_HL_IRQENABLE_SET(2), val);
569 /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
570 reg_write(phy->cal, CAL_CSI2_VC_IRQENABLE(0), 0xFF000000);
571 }
572
573 static void cal_camerarx_disable_irqs(struct cal_camerarx *phy)
574 {
575 u32 val;
576
577 /* Disable CIO error irqs */
578 reg_write(phy->cal, CAL_HL_IRQENABLE_CLR(0),
579 CAL_HL_IRQ_CIO_MASK(phy->instance));
580 reg_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance),
581 0);
582
583 /* Disable IRQ_WDMA_END 0/1 */
584 val = 0;
585 set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
586 reg_write(phy->cal, CAL_HL_IRQENABLE_CLR(1), val);
587 /* Disable IRQ_WDMA_START 0/1 */
588 val = 0;
589 set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
590 reg_write(phy->cal, CAL_HL_IRQENABLE_CLR(2), val);
591 /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
592 reg_write(phy->cal, CAL_CSI2_VC_IRQENABLE(0), 0);
593 }
594
595 static void cal_camerarx_power(struct cal_camerarx *phy, bool enable)
596 {
597 u32 target_state;
598 unsigned int i;
599
600 target_state = enable ? CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON :
601 CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF;
602
603 reg_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
604 target_state, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
605
606 for (i = 0; i < 10; i++) {
607 u32 current_state;
608
609 current_state = reg_read_field(phy->cal,
610 CAL_CSI2_COMPLEXIO_CFG(phy->instance),
611 CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK);
612
613 if (current_state == target_state)
614 break;
615
616 usleep_range(1000, 1100);
617 }
618
619 if (i == 10)
620 phy_err(phy, "Failed to power %s complexio\n",
621 enable ? "up" : "down");
622 }
623
624 /*
625 * TCLK values are OK at their reset values
626 */
627 #define TCLK_TERM 0
628 #define TCLK_MISS 1
629 #define TCLK_SETTLE 14
630
631 static void cal_camerarx_config(struct cal_camerarx *phy,
632 const struct cal_fmt *fmt)
633 {
634 unsigned int reg0, reg1;
635 unsigned int ths_term, ths_settle;
636 unsigned int csi2_ddrclk_khz;
637 struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
638 &phy->endpoint.bus.mipi_csi2;
639 u32 num_lanes = mipi_csi2->num_data_lanes;
640
641 /* DPHY timing configuration */
642 /* CSI-2 is DDR and we only count used lanes. */
643 csi2_ddrclk_khz = phy->external_rate / 1000
644 / (2 * num_lanes) * fmt->bpp;
645 phy_dbg(1, phy, "csi2_ddrclk_khz: %d\n", csi2_ddrclk_khz);
646
647 /* THS_TERM: Programmed value = floor(20 ns/DDRClk period) */
648 ths_term = 20 * csi2_ddrclk_khz / 1000000;
649 phy_dbg(1, phy, "ths_term: %d (0x%02x)\n", ths_term, ths_term);
650
651 /* THS_SETTLE: Programmed value = floor(105 ns/DDRClk period) + 4 */
652 ths_settle = (105 * csi2_ddrclk_khz / 1000000) + 4;
653 phy_dbg(1, phy, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle);
654
655 reg0 = reg_read(phy, CAL_CSI2_PHY_REG0);
656 set_field(&reg0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE,
657 CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK);
658 set_field(&reg0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK);
659 set_field(&reg0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK);
660
661 phy_dbg(1, phy, "CSI2_%d_REG0 = 0x%08x\n", phy->instance, reg0);
662 reg_write(phy, CAL_CSI2_PHY_REG0, reg0);
663
664 reg1 = reg_read(phy, CAL_CSI2_PHY_REG1);
665 set_field(&reg1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK);
666 set_field(&reg1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK);
667 set_field(&reg1, TCLK_MISS, CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK);
668 set_field(&reg1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);
669
670 phy_dbg(1, phy, "CSI2_%d_REG1 = 0x%08x\n", phy->instance, reg1);
671 reg_write(phy, CAL_CSI2_PHY_REG1, reg1);
672 }
673
674 static void cal_camerarx_init(struct cal_camerarx *phy,
675 const struct cal_fmt *fmt)
676 {
677 u32 val;
678 u32 sscounter;
679
680 /* Steps
681 * 1. Configure D-PHY mode and enable required lanes
682 * 2. Reset complex IO - Wait for completion of reset
683 * Note if the external sensor is not sending byte clock,
684 * the reset will timeout
685 * 3 Program Stop States
686 * A. Program THS_TERM, THS_SETTLE, etc... Timings parameters
687 * in terms of DDR clock periods
688 * B. Enable stop state transition timeouts
689 * 4.Force FORCERXMODE
690 * D. Enable pull down using pad control
691 * E. Power up PHY
692 * F. Wait for power up completion
693 * G. Wait for all enabled lane to reach stop state
694 * H. Disable pull down using pad control
695 */
696
697 /* 1. Configure D-PHY mode and enable required lanes */
698 cal_camerarx_enable(phy);
699
700 /* 2. Reset complex IO - Do not wait for reset completion */
701 reg_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
702 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL,
703 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
704 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x De-assert Complex IO Reset\n",
705 phy->instance,
706 reg_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)));
707
708 /* Dummy read to allow SCP reset to complete */
709 reg_read(phy, CAL_CSI2_PHY_REG0);
710
711 /* 3.A. Program Phy Timing Parameters */
712 cal_camerarx_config(phy, fmt);
713
714 /* 3.B. Program Stop States */
715 /*
716 * The stop-state-counter is based on fclk cycles, and we always use
717 * the x16 and x4 settings, so stop-state-timeout =
718 * fclk-cycle * 16 * 4 * counter.
719 *
720 * Stop-state-timeout must be more than 100us as per CSI2 spec, so we
721 * calculate a timeout that's 100us (rounding up).
722 */
723 sscounter = DIV_ROUND_UP(clk_get_rate(phy->cal->fclk), 10000 * 16 * 4);
724
725 val = reg_read(phy->cal, CAL_CSI2_TIMING(phy->instance));
726 set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK);
727 set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK);
728 set_field(&val, sscounter, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK);
729 reg_write(phy->cal, CAL_CSI2_TIMING(phy->instance), val);
730 phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Stop States\n",
731 phy->instance,
732 reg_read(phy->cal, CAL_CSI2_TIMING(phy->instance)));
733
734 /* 4. Force FORCERXMODE */
735 reg_write_field(phy->cal, CAL_CSI2_TIMING(phy->instance),
736 1, CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK);
737 phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Force RXMODE\n",
738 phy->instance,
739 reg_read(phy->cal, CAL_CSI2_TIMING(phy->instance)));
740
741 /* E. Power up the PHY using the complex IO */
742 cal_camerarx_power(phy, true);
743 }
744
745 static void cal_camerarx_wait_reset(struct cal_camerarx *phy)
746 {
747 unsigned long timeout;
748
749 timeout = jiffies + msecs_to_jiffies(750);
750 while (time_before(jiffies, timeout)) {
751 if (reg_read_field(phy->cal,
752 CAL_CSI2_COMPLEXIO_CFG(phy->instance),
753 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
754 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
755 break;
756 usleep_range(500, 5000);
757 }
758
759 if (reg_read_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
760 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) !=
761 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
762 phy_err(phy, "Timeout waiting for Complex IO reset done\n");
763 }
764
765 static void cal_camerarx_wait_stop_state(struct cal_camerarx *phy)
766 {
767 unsigned long timeout;
768
769 timeout = jiffies + msecs_to_jiffies(750);
770 while (time_before(jiffies, timeout)) {
771 if (reg_read_field(phy->cal,
772 CAL_CSI2_TIMING(phy->instance),
773 CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == 0)
774 break;
775 usleep_range(500, 5000);
776 }
777
778 if (reg_read_field(phy->cal, CAL_CSI2_TIMING(phy->instance),
779 CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) != 0)
780 phy_err(phy, "Timeout waiting for stop state\n");
781 }
782
783 static void cal_camerarx_wait_ready(struct cal_camerarx *phy)
784 {
785 /* Steps
786 * 2. Wait for completion of reset
787 * Note if the external sensor is not sending byte clock,
788 * the reset will timeout
789 * 4.Force FORCERXMODE
790 * G. Wait for all enabled lane to reach stop state
791 * H. Disable pull down using pad control
792 */
793
794 /* 2. Wait for reset completion */
795 cal_camerarx_wait_reset(phy);
796
797 /* 4. G. Wait for all enabled lane to reach stop state */
798 cal_camerarx_wait_stop_state(phy);
799
800 phy_dbg(1, phy, "CSI2_%d_REG1 = 0x%08x (Bit(31,28) should be set!)\n",
801 phy->instance, reg_read(phy, CAL_CSI2_PHY_REG1));
802 }
803
804 static void cal_camerarx_deinit(struct cal_camerarx *phy)
805 {
806 unsigned int i;
807
808 cal_camerarx_power(phy, false);
809
810 /* Assert Comple IO Reset */
811 reg_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
812 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL,
813 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
814
815 /* Wait for power down completion */
816 for (i = 0; i < 10; i++) {
817 if (reg_read_field(phy->cal,
818 CAL_CSI2_COMPLEXIO_CFG(phy->instance),
819 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
820 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING)
821 break;
822 usleep_range(1000, 1100);
823 }
824 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO in Reset (%d) %s\n",
825 phy->instance,
826 reg_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)), i,
827 (i >= 10) ? "(timeout)" : "");
828
829 /* Disable the phy */
830 cal_camerarx_disable(phy);
831 }
832
833 static void cal_camerarx_lane_config(struct cal_camerarx *phy)
834 {
835 u32 val = reg_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance));
836 u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK;
837 u32 polarity_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK;
838 struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
839 &phy->endpoint.bus.mipi_csi2;
840 int lane;
841
842 set_field(&val, mipi_csi2->clock_lane + 1, lane_mask);
843 set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask);
844 for (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) {
845 /*
846 * Every lane are one nibble apart starting with the
847 * clock followed by the data lanes so shift masks by 4.
848 */
849 lane_mask <<= 4;
850 polarity_mask <<= 4;
851 set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask);
852 set_field(&val, mipi_csi2->lane_polarities[lane + 1],
853 polarity_mask);
854 }
855
856 reg_write(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), val);
857 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n",
858 phy->instance, val);
859 }
860
861 static void cal_camerarx_ppi_enable(struct cal_camerarx *phy)
862 {
863 reg_write(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), BIT(3));
864 reg_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance),
865 1, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
866 }
867
868 static void cal_camerarx_ppi_disable(struct cal_camerarx *phy)
869 {
870 reg_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance),
871 0, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
872 }
873
874 static int cal_camerarx_get_external_info(struct cal_camerarx *phy)
875 {
876 struct v4l2_ctrl *ctrl;
877
878 if (!phy->sensor)
879 return -ENODEV;
880
881 ctrl = v4l2_ctrl_find(phy->sensor->ctrl_handler, V4L2_CID_PIXEL_RATE);
882 if (!ctrl) {
883 phy_err(phy, "no pixel rate control in subdev: %s\n",
884 phy->sensor->name);
885 return -EPIPE;
886 }
887
888 phy->external_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
889 phy_dbg(3, phy, "sensor Pixel Rate: %u\n", phy->external_rate);
890
891 return 0;
892 }
893
894 static int cal_camerarx_regmap_init(struct cal_dev *cal,
895 struct cal_camerarx *phy)
896 {
897 const struct cal_camerarx_data *phy_data;
898 unsigned int i;
899
900 if (!cal->data)
901 return -EINVAL;
902
903 phy_data = &cal->data->camerarx[phy->instance];
904
905 for (i = 0; i < F_MAX_FIELDS; i++) {
906 struct reg_field field = {
907 .reg = cal->syscon_camerrx_offset,
908 .lsb = phy_data->fields[i].lsb,
909 .msb = phy_data->fields[i].msb,
910 };
911
912 /*
913 * Here we update the reg offset with the
914 * value found in DT
915 */
916 phy->fields[i] = devm_regmap_field_alloc(&cal->pdev->dev,
917 cal->syscon_camerrx,
918 field);
919 if (IS_ERR(phy->fields[i])) {
920 cal_err(cal, "Unable to allocate regmap fields\n");
921 return PTR_ERR(phy->fields[i]);
922 }
923 }
924
925 return 0;
926 }
927
928 static struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal,
929 unsigned int instance)
930 {
931 struct platform_device *pdev = cal->pdev;
932 struct cal_camerarx *phy;
933 int ret;
934
935 phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
936 if (!phy)
937 return ERR_PTR(-ENOMEM);
938
939 phy->cal = cal;
940 phy->instance = instance;
941 phy->external_rate = 192000000;
942
943 phy->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
944 (instance == 0) ?
945 "cal_rx_core0" :
946 "cal_rx_core1");
947 phy->base = devm_ioremap_resource(&pdev->dev, phy->res);
948 if (IS_ERR(phy->base)) {
949 cal_err(cal, "failed to ioremap\n");
950 return ERR_CAST(phy->base);
951 }
952
953 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
954 phy->res->name, &phy->res->start, &phy->res->end);
955
956 ret = cal_camerarx_regmap_init(cal, phy);
957 if (ret)
958 return ERR_PTR(ret);
959
960 return phy;
961 }
962
963 static int cal_camerarx_init_regmap(struct cal_dev *cal)
964 {
965 struct device_node *np = cal->pdev->dev.of_node;
966 struct regmap_config config = { };
967 struct regmap *syscon;
968 struct resource *res;
969 unsigned int offset;
970 void __iomem *base;
971
972 syscon = syscon_regmap_lookup_by_phandle_args(np, "ti,camerrx-control",
973 1, &offset);
974 if (!IS_ERR(syscon)) {
975 cal->syscon_camerrx = syscon;
976 cal->syscon_camerrx_offset = offset;
977 return 0;
978 }
979
980 dev_warn(&cal->pdev->dev, "failed to get ti,camerrx-control: %ld\n",
981 PTR_ERR(syscon));
982
983 /*
984 * Backward DTS compatibility. If syscon entry is not present then
985 * check if the camerrx_control resource is present.
986 */
987 res = platform_get_resource_byname(cal->pdev, IORESOURCE_MEM,
988 "camerrx_control");
989 base = devm_ioremap_resource(&cal->pdev->dev, res);
990 if (IS_ERR(base)) {
991 cal_err(cal, "failed to ioremap camerrx_control\n");
992 return PTR_ERR(base);
993 }
994
995 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
996 res->name, &res->start, &res->end);
997
998 config.reg_bits = 32;
999 config.reg_stride = 4;
1000 config.val_bits = 32;
1001 config.max_register = resource_size(res) - 4;
1002
1003 syscon = regmap_init_mmio(NULL, base, &config);
1004 if (IS_ERR(syscon)) {
1005 pr_err("regmap init failed\n");
1006 return PTR_ERR(syscon);
1007 }
1008
1009 /*
1010 * In this case the base already point to the direct CM register so no
1011 * need for an offset.
1012 */
1013 cal->syscon_camerrx = syscon;
1014 cal->syscon_camerrx_offset = 0;
1015
1016 return 0;
1017 }
1018
1019 /* ------------------------------------------------------------------
1020 * Context Management
1021 * ------------------------------------------------------------------
1022 */
1023
1024 static void cal_ctx_csi2_config(struct cal_ctx *ctx)
1025 {
1026 u32 val;
1027
1028 val = reg_read(ctx->cal, CAL_CSI2_CTX0(ctx->index));
1029 set_field(&val, ctx->cport, CAL_CSI2_CTX_CPORT_MASK);
1030 /*
1031 * DT type: MIPI CSI-2 Specs
1032 * 0x1: All - DT filter is disabled
1033 * 0x24: RGB888 1 pixel = 3 bytes
1034 * 0x2B: RAW10 4 pixels = 5 bytes
1035 * 0x2A: RAW8 1 pixel = 1 byte
1036 * 0x1E: YUV422 2 pixels = 4 bytes
1037 */
1038 set_field(&val, 0x1, CAL_CSI2_CTX_DT_MASK);
1039 /* Virtual Channel from the CSI2 sensor usually 0! */
1040 set_field(&val, ctx->virtual_channel, CAL_CSI2_CTX_VC_MASK);
1041 set_field(&val, ctx->v_fmt.fmt.pix.height, CAL_CSI2_CTX_LINES_MASK);
1042 set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK);
1043 set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE,
1044 CAL_CSI2_CTX_PACK_MODE_MASK);
1045 reg_write(ctx->cal, CAL_CSI2_CTX0(ctx->index), val);
1046 ctx_dbg(3, ctx, "CAL_CSI2_CTX0(%d) = 0x%08x\n", ctx->index,
1047 reg_read(ctx->cal, CAL_CSI2_CTX0(ctx->index)));
1048 }
1049
1050 static void cal_ctx_pix_proc_config(struct cal_ctx *ctx)
1051 {
1052 u32 val, extract, pack;
1053
1054 switch (ctx->fmt->bpp) {
1055 case 8:
1056 extract = CAL_PIX_PROC_EXTRACT_B8;
1057 pack = CAL_PIX_PROC_PACK_B8;
1058 break;
1059 case 10:
1060 extract = CAL_PIX_PROC_EXTRACT_B10_MIPI;
1061 pack = CAL_PIX_PROC_PACK_B16;
1062 break;
1063 case 12:
1064 extract = CAL_PIX_PROC_EXTRACT_B12_MIPI;
1065 pack = CAL_PIX_PROC_PACK_B16;
1066 break;
1067 case 16:
1068 extract = CAL_PIX_PROC_EXTRACT_B16_LE;
1069 pack = CAL_PIX_PROC_PACK_B16;
1070 break;
1071 default:
1072 /*
1073 * If you see this warning then it means that you added
1074 * some new entry in the cal_formats[] array with a different
1075 * bit per pixel values then the one supported below.
1076 * Either add support for the new bpp value below or adjust
1077 * the new entry to use one of the value below.
1078 *
1079 * Instead of failing here just use 8 bpp as a default.
1080 */
1081 dev_warn_once(&ctx->cal->pdev->dev,
1082 "%s:%d:%s: bpp:%d unsupported! Overwritten with 8.\n",
1083 __FILE__, __LINE__, __func__, ctx->fmt->bpp);
1084 extract = CAL_PIX_PROC_EXTRACT_B8;
1085 pack = CAL_PIX_PROC_PACK_B8;
1086 break;
1087 }
1088
1089 val = reg_read(ctx->cal, CAL_PIX_PROC(ctx->index));
1090 set_field(&val, extract, CAL_PIX_PROC_EXTRACT_MASK);
1091 set_field(&val, CAL_PIX_PROC_DPCMD_BYPASS, CAL_PIX_PROC_DPCMD_MASK);
1092 set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK);
1093 set_field(&val, pack, CAL_PIX_PROC_PACK_MASK);
1094 set_field(&val, ctx->cport, CAL_PIX_PROC_CPORT_MASK);
1095 set_field(&val, 1, CAL_PIX_PROC_EN_MASK);
1096 reg_write(ctx->cal, CAL_PIX_PROC(ctx->index), val);
1097 ctx_dbg(3, ctx, "CAL_PIX_PROC(%d) = 0x%08x\n", ctx->index,
1098 reg_read(ctx->cal, CAL_PIX_PROC(ctx->index)));
1099 }
1100
1101 static void cal_ctx_wr_dma_config(struct cal_ctx *ctx,
1102 unsigned int width, unsigned int height)
1103 {
1104 u32 val;
1105
1106 val = reg_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->index));
1107 set_field(&val, ctx->cport, CAL_WR_DMA_CTRL_CPORT_MASK);
1108 set_field(&val, height, CAL_WR_DMA_CTRL_YSIZE_MASK);
1109 set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT,
1110 CAL_WR_DMA_CTRL_DTAG_MASK);
1111 set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST,
1112 CAL_WR_DMA_CTRL_MODE_MASK);
1113 set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR,
1114 CAL_WR_DMA_CTRL_PATTERN_MASK);
1115 set_field(&val, 1, CAL_WR_DMA_CTRL_STALL_RD_MASK);
1116 reg_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->index), val);
1117 ctx_dbg(3, ctx, "CAL_WR_DMA_CTRL(%d) = 0x%08x\n", ctx->index,
1118 reg_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->index)));
1119
1120 /*
1121 * width/16 not sure but giving it a whirl.
1122 * zero does not work right
1123 */
1124 reg_write_field(ctx->cal,
1125 CAL_WR_DMA_OFST(ctx->index),
1126 (width / 16),
1127 CAL_WR_DMA_OFST_MASK);
1128 ctx_dbg(3, ctx, "CAL_WR_DMA_OFST(%d) = 0x%08x\n", ctx->index,
1129 reg_read(ctx->cal, CAL_WR_DMA_OFST(ctx->index)));
1130
1131 val = reg_read(ctx->cal, CAL_WR_DMA_XSIZE(ctx->index));
1132 /* 64 bit word means no skipping */
1133 set_field(&val, 0, CAL_WR_DMA_XSIZE_XSKIP_MASK);
1134 /*
1135 * (width*8)/64 this should be size of an entire line
1136 * in 64bit word but 0 means all data until the end
1137 * is detected automagically
1138 */
1139 set_field(&val, (width / 8), CAL_WR_DMA_XSIZE_MASK);
1140 reg_write(ctx->cal, CAL_WR_DMA_XSIZE(ctx->index), val);
1141 ctx_dbg(3, ctx, "CAL_WR_DMA_XSIZE(%d) = 0x%08x\n", ctx->index,
1142 reg_read(ctx->cal, CAL_WR_DMA_XSIZE(ctx->index)));
1143
1144 val = reg_read(ctx->cal, CAL_CTRL);
1145 set_field(&val, CAL_CTRL_BURSTSIZE_BURST128, CAL_CTRL_BURSTSIZE_MASK);
1146 set_field(&val, 0xF, CAL_CTRL_TAGCNT_MASK);
1147 set_field(&val, CAL_CTRL_POSTED_WRITES_NONPOSTED,
1148 CAL_CTRL_POSTED_WRITES_MASK);
1149 set_field(&val, 0xFF, CAL_CTRL_MFLAGL_MASK);
1150 set_field(&val, 0xFF, CAL_CTRL_MFLAGH_MASK);
1151 reg_write(ctx->cal, CAL_CTRL, val);
1152 ctx_dbg(3, ctx, "CAL_CTRL = 0x%08x\n", reg_read(ctx->cal, CAL_CTRL));
1153 }
1154
1155 static void cal_ctx_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr)
1156 {
1157 reg_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->index), dmaaddr);
1158 }
1159
1160 /* ------------------------------------------------------------------
1161 * IRQ Handling
1162 * ------------------------------------------------------------------
1163 */
1164
1165 static inline void cal_schedule_next_buffer(struct cal_ctx *ctx)
1166 {
1167 struct cal_dmaqueue *dma_q = &ctx->vidq;
1168 struct cal_buffer *buf;
1169 unsigned long addr;
1170
1171 buf = list_entry(dma_q->active.next, struct cal_buffer, list);
1172 ctx->next_frm = buf;
1173 list_del(&buf->list);
1174
1175 addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
1176 cal_ctx_wr_dma_addr(ctx, addr);
1177 }
1178
1179 static inline void cal_process_buffer_complete(struct cal_ctx *ctx)
1180 {
1181 ctx->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();
1182 ctx->cur_frm->vb.field = ctx->m_fmt.field;
1183 ctx->cur_frm->vb.sequence = ctx->sequence++;
1184
1185 vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
1186 ctx->cur_frm = ctx->next_frm;
1187 }
1188
1189 #define isvcirqset(irq, vc, ff) (irq & \
1190 (CAL_CSI2_VC_IRQENABLE_ ##ff ##_IRQ_##vc ##_MASK))
1191
1192 #define isportirqset(irq, port) (irq & CAL_HL_IRQ_MASK(port))
1193
1194 static irqreturn_t cal_irq(int irq_cal, void *data)
1195 {
1196 struct cal_dev *cal = data;
1197 struct cal_ctx *ctx;
1198 struct cal_dmaqueue *dma_q;
1199 u32 status;
1200
1201 status = reg_read(cal, CAL_HL_IRQSTATUS(0));
1202 if (status) {
1203 unsigned int i;
1204
1205 reg_write(cal, CAL_HL_IRQSTATUS(0), status);
1206
1207 if (status & CAL_HL_IRQ_OCPO_ERR_MASK)
1208 dev_err_ratelimited(&cal->pdev->dev, "OCPO ERROR\n");
1209
1210 for (i = 0; i < 2; ++i) {
1211 if (status & CAL_HL_IRQ_CIO_MASK(i)) {
1212 u32 cio_stat = reg_read(cal,
1213 CAL_CSI2_COMPLEXIO_IRQSTATUS(i));
1214
1215 dev_err_ratelimited(&cal->pdev->dev,
1216 "CIO%u error: %#08x\n", i, cio_stat);
1217
1218 reg_write(cal, CAL_CSI2_COMPLEXIO_IRQSTATUS(i),
1219 cio_stat);
1220 }
1221 }
1222 }
1223
1224 /* Check which DMA just finished */
1225 status = reg_read(cal, CAL_HL_IRQSTATUS(1));
1226 if (status) {
1227 unsigned int i;
1228
1229 /* Clear Interrupt status */
1230 reg_write(cal, CAL_HL_IRQSTATUS(1), status);
1231
1232 for (i = 0; i < 2; ++i) {
1233 if (isportirqset(status, i)) {
1234 ctx = cal->ctx[i];
1235
1236 spin_lock(&ctx->slock);
1237 ctx->dma_act = false;
1238
1239 if (ctx->cur_frm != ctx->next_frm)
1240 cal_process_buffer_complete(ctx);
1241
1242 spin_unlock(&ctx->slock);
1243 }
1244 }
1245 }
1246
1247 /* Check which DMA just started */
1248 status = reg_read(cal, CAL_HL_IRQSTATUS(2));
1249 if (status) {
1250 unsigned int i;
1251
1252 /* Clear Interrupt status */
1253 reg_write(cal, CAL_HL_IRQSTATUS(2), status);
1254
1255 for (i = 0; i < 2; ++i) {
1256 if (isportirqset(status, i)) {
1257 ctx = cal->ctx[i];
1258 dma_q = &ctx->vidq;
1259
1260 spin_lock(&ctx->slock);
1261 ctx->dma_act = true;
1262 if (!list_empty(&dma_q->active) &&
1263 ctx->cur_frm == ctx->next_frm)
1264 cal_schedule_next_buffer(ctx);
1265 spin_unlock(&ctx->slock);
1266 }
1267 }
1268 }
1269
1270 return IRQ_HANDLED;
1271 }
1272
1273 /* ------------------------------------------------------------------
1274 * V4L2 Video IOCTLs
1275 * ------------------------------------------------------------------
1276 */
1277
1278 static const struct cal_fmt *find_format_by_pix(struct cal_ctx *ctx,
1279 u32 pixelformat)
1280 {
1281 const struct cal_fmt *fmt;
1282 unsigned int k;
1283
1284 for (k = 0; k < ctx->num_active_fmt; k++) {
1285 fmt = ctx->active_fmt[k];
1286 if (fmt->fourcc == pixelformat)
1287 return fmt;
1288 }
1289
1290 return NULL;
1291 }
1292
1293 static const struct cal_fmt *find_format_by_code(struct cal_ctx *ctx,
1294 u32 code)
1295 {
1296 const struct cal_fmt *fmt;
1297 unsigned int k;
1298
1299 for (k = 0; k < ctx->num_active_fmt; k++) {
1300 fmt = ctx->active_fmt[k];
1301 if (fmt->code == code)
1302 return fmt;
1303 }
1304
1305 return NULL;
1306 }
1307
1308 static int cal_querycap(struct file *file, void *priv,
1309 struct v4l2_capability *cap)
1310 {
1311 struct cal_ctx *ctx = video_drvdata(file);
1312
1313 strscpy(cap->driver, CAL_MODULE_NAME, sizeof(cap->driver));
1314 strscpy(cap->card, CAL_MODULE_NAME, sizeof(cap->card));
1315
1316 snprintf(cap->bus_info, sizeof(cap->bus_info),
1317 "platform:%s", dev_name(&ctx->cal->pdev->dev));
1318 return 0;
1319 }
1320
1321 static int cal_enum_fmt_vid_cap(struct file *file, void *priv,
1322 struct v4l2_fmtdesc *f)
1323 {
1324 struct cal_ctx *ctx = video_drvdata(file);
1325 const struct cal_fmt *fmt;
1326
1327 if (f->index >= ctx->num_active_fmt)
1328 return -EINVAL;
1329
1330 fmt = ctx->active_fmt[f->index];
1331
1332 f->pixelformat = fmt->fourcc;
1333 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1334 return 0;
1335 }
1336
1337 static int __subdev_get_format(struct cal_ctx *ctx,
1338 struct v4l2_mbus_framefmt *fmt)
1339 {
1340 struct v4l2_subdev_format sd_fmt;
1341 struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
1342 int ret;
1343
1344 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1345 sd_fmt.pad = 0;
1346
1347 ret = v4l2_subdev_call(ctx->phy->sensor, pad, get_fmt, NULL, &sd_fmt);
1348 if (ret)
1349 return ret;
1350
1351 *fmt = *mbus_fmt;
1352
1353 ctx_dbg(1, ctx, "%s %dx%d code:%04X\n", __func__,
1354 fmt->width, fmt->height, fmt->code);
1355
1356 return 0;
1357 }
1358
1359 static int __subdev_set_format(struct cal_ctx *ctx,
1360 struct v4l2_mbus_framefmt *fmt)
1361 {
1362 struct v4l2_subdev_format sd_fmt;
1363 struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
1364 int ret;
1365
1366 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1367 sd_fmt.pad = 0;
1368 *mbus_fmt = *fmt;
1369
1370 ret = v4l2_subdev_call(ctx->phy->sensor, pad, set_fmt, NULL, &sd_fmt);
1371 if (ret)
1372 return ret;
1373
1374 ctx_dbg(1, ctx, "%s %dx%d code:%04X\n", __func__,
1375 fmt->width, fmt->height, fmt->code);
1376
1377 return 0;
1378 }
1379
1380 static int cal_calc_format_size(struct cal_ctx *ctx,
1381 const struct cal_fmt *fmt,
1382 struct v4l2_format *f)
1383 {
1384 u32 bpl, max_width;
1385
1386 if (!fmt) {
1387 ctx_dbg(3, ctx, "No cal_fmt provided!\n");
1388 return -EINVAL;
1389 }
1390
1391 /*
1392 * Maximum width is bound by the DMA max width in bytes.
1393 * We need to recalculate the actual maxi width depending on the
1394 * number of bytes per pixels required.
1395 */
1396 max_width = MAX_WIDTH_BYTES / (ALIGN(fmt->bpp, 8) >> 3);
1397 v4l_bound_align_image(&f->fmt.pix.width, 48, max_width, 2,
1398 &f->fmt.pix.height, 32, MAX_HEIGHT_LINES, 0, 0);
1399
1400 bpl = (f->fmt.pix.width * ALIGN(fmt->bpp, 8)) >> 3;
1401 f->fmt.pix.bytesperline = ALIGN(bpl, 16);
1402
1403 f->fmt.pix.sizeimage = f->fmt.pix.height *
1404 f->fmt.pix.bytesperline;
1405
1406 ctx_dbg(3, ctx, "%s: fourcc: %s size: %dx%d bpl:%d img_size:%d\n",
1407 __func__, fourcc_to_str(f->fmt.pix.pixelformat),
1408 f->fmt.pix.width, f->fmt.pix.height,
1409 f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
1410
1411 return 0;
1412 }
1413
1414 static int cal_g_fmt_vid_cap(struct file *file, void *priv,
1415 struct v4l2_format *f)
1416 {
1417 struct cal_ctx *ctx = video_drvdata(file);
1418
1419 *f = ctx->v_fmt;
1420
1421 return 0;
1422 }
1423
1424 static int cal_try_fmt_vid_cap(struct file *file, void *priv,
1425 struct v4l2_format *f)
1426 {
1427 struct cal_ctx *ctx = video_drvdata(file);
1428 const struct cal_fmt *fmt;
1429 struct v4l2_subdev_frame_size_enum fse;
1430 int ret, found;
1431
1432 fmt = find_format_by_pix(ctx, f->fmt.pix.pixelformat);
1433 if (!fmt) {
1434 ctx_dbg(3, ctx, "Fourcc format (0x%08x) not found.\n",
1435 f->fmt.pix.pixelformat);
1436
1437 /* Just get the first one enumerated */
1438 fmt = ctx->active_fmt[0];
1439 f->fmt.pix.pixelformat = fmt->fourcc;
1440 }
1441
1442 f->fmt.pix.field = ctx->v_fmt.fmt.pix.field;
1443
1444 /* check for/find a valid width/height */
1445 ret = 0;
1446 found = false;
1447 fse.pad = 0;
1448 fse.code = fmt->code;
1449 fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1450 for (fse.index = 0; ; fse.index++) {
1451 ret = v4l2_subdev_call(ctx->phy->sensor, pad, enum_frame_size,
1452 NULL, &fse);
1453 if (ret)
1454 break;
1455
1456 if ((f->fmt.pix.width == fse.max_width) &&
1457 (f->fmt.pix.height == fse.max_height)) {
1458 found = true;
1459 break;
1460 } else if ((f->fmt.pix.width >= fse.min_width) &&
1461 (f->fmt.pix.width <= fse.max_width) &&
1462 (f->fmt.pix.height >= fse.min_height) &&
1463 (f->fmt.pix.height <= fse.max_height)) {
1464 found = true;
1465 break;
1466 }
1467 }
1468
1469 if (!found) {
1470 /* use existing values as default */
1471 f->fmt.pix.width = ctx->v_fmt.fmt.pix.width;
1472 f->fmt.pix.height = ctx->v_fmt.fmt.pix.height;
1473 }
1474
1475 /*
1476 * Use current colorspace for now, it will get
1477 * updated properly during s_fmt
1478 */
1479 f->fmt.pix.colorspace = ctx->v_fmt.fmt.pix.colorspace;
1480 return cal_calc_format_size(ctx, fmt, f);
1481 }
1482
1483 static int cal_s_fmt_vid_cap(struct file *file, void *priv,
1484 struct v4l2_format *f)
1485 {
1486 struct cal_ctx *ctx = video_drvdata(file);
1487 struct vb2_queue *q = &ctx->vb_vidq;
1488 const struct cal_fmt *fmt;
1489 struct v4l2_mbus_framefmt mbus_fmt;
1490 int ret;
1491
1492 if (vb2_is_busy(q)) {
1493 ctx_dbg(3, ctx, "%s device busy\n", __func__);
1494 return -EBUSY;
1495 }
1496
1497 ret = cal_try_fmt_vid_cap(file, priv, f);
1498 if (ret < 0)
1499 return ret;
1500
1501 fmt = find_format_by_pix(ctx, f->fmt.pix.pixelformat);
1502
1503 v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);
1504
1505 ret = __subdev_set_format(ctx, &mbus_fmt);
1506 if (ret)
1507 return ret;
1508
1509 /* Just double check nothing has gone wrong */
1510 if (mbus_fmt.code != fmt->code) {
1511 ctx_dbg(3, ctx,
1512 "%s subdev changed format on us, this should not happen\n",
1513 __func__);
1514 return -EINVAL;
1515 }
1516
1517 v4l2_fill_pix_format(&ctx->v_fmt.fmt.pix, &mbus_fmt);
1518 ctx->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1519 ctx->v_fmt.fmt.pix.pixelformat = fmt->fourcc;
1520 cal_calc_format_size(ctx, fmt, &ctx->v_fmt);
1521 ctx->fmt = fmt;
1522 ctx->m_fmt = mbus_fmt;
1523 *f = ctx->v_fmt;
1524
1525 return 0;
1526 }
1527
1528 static int cal_enum_framesizes(struct file *file, void *fh,
1529 struct v4l2_frmsizeenum *fsize)
1530 {
1531 struct cal_ctx *ctx = video_drvdata(file);
1532 const struct cal_fmt *fmt;
1533 struct v4l2_subdev_frame_size_enum fse;
1534 int ret;
1535
1536 /* check for valid format */
1537 fmt = find_format_by_pix(ctx, fsize->pixel_format);
1538 if (!fmt) {
1539 ctx_dbg(3, ctx, "Invalid pixel code: %x\n",
1540 fsize->pixel_format);
1541 return -EINVAL;
1542 }
1543
1544 fse.index = fsize->index;
1545 fse.pad = 0;
1546 fse.code = fmt->code;
1547 fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1548
1549 ret = v4l2_subdev_call(ctx->phy->sensor, pad, enum_frame_size, NULL,
1550 &fse);
1551 if (ret)
1552 return ret;
1553
1554 ctx_dbg(1, ctx, "%s: index: %d code: %x W:[%d,%d] H:[%d,%d]\n",
1555 __func__, fse.index, fse.code, fse.min_width, fse.max_width,
1556 fse.min_height, fse.max_height);
1557
1558 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1559 fsize->discrete.width = fse.max_width;
1560 fsize->discrete.height = fse.max_height;
1561
1562 return 0;
1563 }
1564
1565 static int cal_enum_input(struct file *file, void *priv,
1566 struct v4l2_input *inp)
1567 {
1568 if (inp->index > 0)
1569 return -EINVAL;
1570
1571 inp->type = V4L2_INPUT_TYPE_CAMERA;
1572 sprintf(inp->name, "Camera %u", inp->index);
1573 return 0;
1574 }
1575
1576 static int cal_g_input(struct file *file, void *priv, unsigned int *i)
1577 {
1578 *i = 0;
1579 return 0;
1580 }
1581
1582 static int cal_s_input(struct file *file, void *priv, unsigned int i)
1583 {
1584 return i > 0 ? -EINVAL : 0;
1585 }
1586
1587 /* timeperframe is arbitrary and continuous */
1588 static int cal_enum_frameintervals(struct file *file, void *priv,
1589 struct v4l2_frmivalenum *fival)
1590 {
1591 struct cal_ctx *ctx = video_drvdata(file);
1592 const struct cal_fmt *fmt;
1593 struct v4l2_subdev_frame_interval_enum fie = {
1594 .index = fival->index,
1595 .width = fival->width,
1596 .height = fival->height,
1597 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1598 };
1599 int ret;
1600
1601 fmt = find_format_by_pix(ctx, fival->pixel_format);
1602 if (!fmt)
1603 return -EINVAL;
1604
1605 fie.code = fmt->code;
1606 ret = v4l2_subdev_call(ctx->phy->sensor, pad, enum_frame_interval,
1607 NULL, &fie);
1608 if (ret)
1609 return ret;
1610 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1611 fival->discrete = fie.interval;
1612
1613 return 0;
1614 }
1615
1616 static const struct v4l2_file_operations cal_fops = {
1617 .owner = THIS_MODULE,
1618 .open = v4l2_fh_open,
1619 .release = vb2_fop_release,
1620 .read = vb2_fop_read,
1621 .poll = vb2_fop_poll,
1622 .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
1623 .mmap = vb2_fop_mmap,
1624 };
1625
1626 static const struct v4l2_ioctl_ops cal_ioctl_ops = {
1627 .vidioc_querycap = cal_querycap,
1628 .vidioc_enum_fmt_vid_cap = cal_enum_fmt_vid_cap,
1629 .vidioc_g_fmt_vid_cap = cal_g_fmt_vid_cap,
1630 .vidioc_try_fmt_vid_cap = cal_try_fmt_vid_cap,
1631 .vidioc_s_fmt_vid_cap = cal_s_fmt_vid_cap,
1632 .vidioc_enum_framesizes = cal_enum_framesizes,
1633 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1634 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1635 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1636 .vidioc_querybuf = vb2_ioctl_querybuf,
1637 .vidioc_qbuf = vb2_ioctl_qbuf,
1638 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1639 .vidioc_expbuf = vb2_ioctl_expbuf,
1640 .vidioc_enum_input = cal_enum_input,
1641 .vidioc_g_input = cal_g_input,
1642 .vidioc_s_input = cal_s_input,
1643 .vidioc_enum_frameintervals = cal_enum_frameintervals,
1644 .vidioc_streamon = vb2_ioctl_streamon,
1645 .vidioc_streamoff = vb2_ioctl_streamoff,
1646 .vidioc_log_status = v4l2_ctrl_log_status,
1647 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1648 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1649 };
1650
1651 /* ------------------------------------------------------------------
1652 * videobuf2 Operations
1653 * ------------------------------------------------------------------
1654 */
1655
1656 static int cal_queue_setup(struct vb2_queue *vq,
1657 unsigned int *nbuffers, unsigned int *nplanes,
1658 unsigned int sizes[], struct device *alloc_devs[])
1659 {
1660 struct cal_ctx *ctx = vb2_get_drv_priv(vq);
1661 unsigned size = ctx->v_fmt.fmt.pix.sizeimage;
1662
1663 if (vq->num_buffers + *nbuffers < 3)
1664 *nbuffers = 3 - vq->num_buffers;
1665
1666 if (*nplanes) {
1667 if (sizes[0] < size)
1668 return -EINVAL;
1669 size = sizes[0];
1670 }
1671
1672 *nplanes = 1;
1673 sizes[0] = size;
1674
1675 ctx_dbg(3, ctx, "nbuffers=%d, size=%d\n", *nbuffers, sizes[0]);
1676
1677 return 0;
1678 }
1679
1680 static int cal_buffer_prepare(struct vb2_buffer *vb)
1681 {
1682 struct cal_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1683 struct cal_buffer *buf = container_of(vb, struct cal_buffer,
1684 vb.vb2_buf);
1685 unsigned long size;
1686
1687 if (WARN_ON(!ctx->fmt))
1688 return -EINVAL;
1689
1690 size = ctx->v_fmt.fmt.pix.sizeimage;
1691 if (vb2_plane_size(vb, 0) < size) {
1692 ctx_err(ctx,
1693 "data will not fit into plane (%lu < %lu)\n",
1694 vb2_plane_size(vb, 0), size);
1695 return -EINVAL;
1696 }
1697
1698 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
1699 return 0;
1700 }
1701
1702 static void cal_buffer_queue(struct vb2_buffer *vb)
1703 {
1704 struct cal_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1705 struct cal_buffer *buf = container_of(vb, struct cal_buffer,
1706 vb.vb2_buf);
1707 struct cal_dmaqueue *vidq = &ctx->vidq;
1708 unsigned long flags;
1709
1710 /* recheck locking */
1711 spin_lock_irqsave(&ctx->slock, flags);
1712 list_add_tail(&buf->list, &vidq->active);
1713 spin_unlock_irqrestore(&ctx->slock, flags);
1714 }
1715
1716 static int cal_start_streaming(struct vb2_queue *vq, unsigned int count)
1717 {
1718 struct cal_ctx *ctx = vb2_get_drv_priv(vq);
1719 struct cal_dmaqueue *dma_q = &ctx->vidq;
1720 struct cal_buffer *buf, *tmp;
1721 unsigned long addr;
1722 unsigned long flags;
1723 int ret;
1724
1725 spin_lock_irqsave(&ctx->slock, flags);
1726 if (list_empty(&dma_q->active)) {
1727 spin_unlock_irqrestore(&ctx->slock, flags);
1728 ctx_dbg(3, ctx, "buffer queue is empty\n");
1729 return -EIO;
1730 }
1731
1732 buf = list_entry(dma_q->active.next, struct cal_buffer, list);
1733 ctx->cur_frm = buf;
1734 ctx->next_frm = buf;
1735 list_del(&buf->list);
1736 spin_unlock_irqrestore(&ctx->slock, flags);
1737
1738 addr = vb2_dma_contig_plane_dma_addr(&ctx->cur_frm->vb.vb2_buf, 0);
1739 ctx->sequence = 0;
1740
1741 ret = cal_camerarx_get_external_info(ctx->phy);
1742 if (ret < 0)
1743 goto err;
1744
1745 ret = v4l2_subdev_call(ctx->phy->sensor, core, s_power, 1);
1746 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) {
1747 ctx_err(ctx, "power on failed in subdev\n");
1748 goto err;
1749 }
1750
1751 pm_runtime_get_sync(&ctx->cal->pdev->dev);
1752
1753 cal_ctx_csi2_config(ctx);
1754 cal_ctx_pix_proc_config(ctx);
1755 cal_ctx_wr_dma_config(ctx, ctx->v_fmt.fmt.pix.bytesperline,
1756 ctx->v_fmt.fmt.pix.height);
1757 cal_camerarx_lane_config(ctx->phy);
1758
1759 cal_camerarx_enable_irqs(ctx->phy);
1760 cal_camerarx_init(ctx->phy, ctx->fmt);
1761
1762 ret = v4l2_subdev_call(ctx->phy->sensor, video, s_stream, 1);
1763 if (ret) {
1764 v4l2_subdev_call(ctx->phy->sensor, core, s_power, 0);
1765 ctx_err(ctx, "stream on failed in subdev\n");
1766 pm_runtime_put_sync(&ctx->cal->pdev->dev);
1767 goto err;
1768 }
1769
1770 cal_camerarx_wait_ready(ctx->phy);
1771 cal_ctx_wr_dma_addr(ctx, addr);
1772 cal_camerarx_ppi_enable(ctx->phy);
1773
1774 if (debug >= 4)
1775 cal_quickdump_regs(ctx->cal);
1776
1777 return 0;
1778
1779 err:
1780 spin_lock_irqsave(&ctx->slock, flags);
1781 vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
1782 ctx->cur_frm = NULL;
1783 ctx->next_frm = NULL;
1784 list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1785 list_del(&buf->list);
1786 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
1787 }
1788 spin_unlock_irqrestore(&ctx->slock, flags);
1789 return ret;
1790 }
1791
1792 static void cal_stop_streaming(struct vb2_queue *vq)
1793 {
1794 struct cal_ctx *ctx = vb2_get_drv_priv(vq);
1795 struct cal_dmaqueue *dma_q = &ctx->vidq;
1796 struct cal_buffer *buf, *tmp;
1797 unsigned long timeout;
1798 unsigned long flags;
1799 int ret;
1800 bool dma_act;
1801
1802 cal_camerarx_ppi_disable(ctx->phy);
1803
1804 /* wait for stream and dma to finish */
1805 dma_act = true;
1806 timeout = jiffies + msecs_to_jiffies(500);
1807 while (dma_act && time_before(jiffies, timeout)) {
1808 msleep(50);
1809
1810 spin_lock_irqsave(&ctx->slock, flags);
1811 dma_act = ctx->dma_act;
1812 spin_unlock_irqrestore(&ctx->slock, flags);
1813 }
1814
1815 if (dma_act)
1816 ctx_err(ctx, "failed to disable dma cleanly\n");
1817
1818 cal_camerarx_disable_irqs(ctx->phy);
1819 cal_camerarx_deinit(ctx->phy);
1820
1821 if (v4l2_subdev_call(ctx->phy->sensor, video, s_stream, 0))
1822 ctx_err(ctx, "stream off failed in subdev\n");
1823
1824 ret = v4l2_subdev_call(ctx->phy->sensor, core, s_power, 0);
1825 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
1826 ctx_err(ctx, "power off failed in subdev\n");
1827
1828 /* Release all active buffers */
1829 spin_lock_irqsave(&ctx->slock, flags);
1830 list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1831 list_del(&buf->list);
1832 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1833 }
1834
1835 if (ctx->cur_frm == ctx->next_frm) {
1836 vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1837 } else {
1838 vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1839 vb2_buffer_done(&ctx->next_frm->vb.vb2_buf,
1840 VB2_BUF_STATE_ERROR);
1841 }
1842 ctx->cur_frm = NULL;
1843 ctx->next_frm = NULL;
1844 spin_unlock_irqrestore(&ctx->slock, flags);
1845
1846 pm_runtime_put_sync(&ctx->cal->pdev->dev);
1847 }
1848
1849 static const struct vb2_ops cal_video_qops = {
1850 .queue_setup = cal_queue_setup,
1851 .buf_prepare = cal_buffer_prepare,
1852 .buf_queue = cal_buffer_queue,
1853 .start_streaming = cal_start_streaming,
1854 .stop_streaming = cal_stop_streaming,
1855 .wait_prepare = vb2_ops_wait_prepare,
1856 .wait_finish = vb2_ops_wait_finish,
1857 };
1858
1859 /* ------------------------------------------------------------------
1860 * Initialization and module stuff
1861 * ------------------------------------------------------------------
1862 */
1863
1864 static const struct video_device cal_videodev = {
1865 .name = CAL_MODULE_NAME,
1866 .fops = &cal_fops,
1867 .ioctl_ops = &cal_ioctl_ops,
1868 .minor = -1,
1869 .release = video_device_release_empty,
1870 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
1871 V4L2_CAP_READWRITE,
1872 };
1873
1874 static int cal_complete_ctx(struct cal_ctx *ctx)
1875 {
1876 struct video_device *vfd;
1877 struct vb2_queue *q;
1878 int ret;
1879
1880 /* initialize locks */
1881 spin_lock_init(&ctx->slock);
1882 mutex_init(&ctx->mutex);
1883
1884 /* initialize queue */
1885 q = &ctx->vb_vidq;
1886 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1887 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
1888 q->drv_priv = ctx;
1889 q->buf_struct_size = sizeof(struct cal_buffer);
1890 q->ops = &cal_video_qops;
1891 q->mem_ops = &vb2_dma_contig_memops;
1892 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1893 q->lock = &ctx->mutex;
1894 q->min_buffers_needed = 3;
1895 q->dev = &ctx->cal->pdev->dev;
1896
1897 ret = vb2_queue_init(q);
1898 if (ret)
1899 return ret;
1900
1901 /* init video dma queues */
1902 INIT_LIST_HEAD(&ctx->vidq.active);
1903
1904 vfd = &ctx->vdev;
1905 *vfd = cal_videodev;
1906 vfd->v4l2_dev = &ctx->v4l2_dev;
1907 vfd->queue = q;
1908
1909 /*
1910 * Provide a mutex to v4l2 core. It will be used to protect
1911 * all fops and v4l2 ioctls.
1912 */
1913 vfd->lock = &ctx->mutex;
1914 video_set_drvdata(vfd, ctx);
1915
1916 ret = video_register_device(vfd, VFL_TYPE_VIDEO, video_nr);
1917 if (ret < 0)
1918 return ret;
1919
1920 ctx_info(ctx, "V4L2 device registered as %s\n",
1921 video_device_node_name(vfd));
1922
1923 return 0;
1924 }
1925
1926 static int cal_async_bound(struct v4l2_async_notifier *notifier,
1927 struct v4l2_subdev *subdev,
1928 struct v4l2_async_subdev *asd)
1929 {
1930 struct cal_ctx *ctx = notifier_to_ctx(notifier);
1931 struct v4l2_subdev_mbus_code_enum mbus_code;
1932 unsigned int i, j, k;
1933 int ret = 0;
1934
1935 if (ctx->phy->sensor) {
1936 ctx_info(ctx, "Rejecting subdev %s (Already set!!)",
1937 subdev->name);
1938 return 0;
1939 }
1940
1941 ctx->phy->sensor = subdev;
1942 ctx_dbg(1, ctx, "Using sensor %s for capture\n", subdev->name);
1943
1944 /* Enumerate sub device formats and enable all matching local formats */
1945 ctx->num_active_fmt = 0;
1946 for (j = 0, i = 0; ret != -EINVAL; ++j) {
1947
1948 memset(&mbus_code, 0, sizeof(mbus_code));
1949 mbus_code.index = j;
1950 mbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1951 ret = v4l2_subdev_call(subdev, pad, enum_mbus_code,
1952 NULL, &mbus_code);
1953 if (ret)
1954 continue;
1955
1956 ctx_dbg(2, ctx,
1957 "subdev %s: code: %04x idx: %u\n",
1958 subdev->name, mbus_code.code, j);
1959
1960 for (k = 0; k < ARRAY_SIZE(cal_formats); k++) {
1961 const struct cal_fmt *fmt = &cal_formats[k];
1962
1963 if (mbus_code.code == fmt->code) {
1964 ctx->active_fmt[i] = fmt;
1965 ctx_dbg(2, ctx,
1966 "matched fourcc: %s: code: %04x idx: %u\n",
1967 fourcc_to_str(fmt->fourcc),
1968 fmt->code, i);
1969 ctx->num_active_fmt = ++i;
1970 }
1971 }
1972 }
1973
1974 if (i == 0) {
1975 ctx_err(ctx, "No suitable format reported by subdev %s\n",
1976 subdev->name);
1977 return -EINVAL;
1978 }
1979
1980 cal_complete_ctx(ctx);
1981
1982 return 0;
1983 }
1984
1985 static int cal_async_complete(struct v4l2_async_notifier *notifier)
1986 {
1987 struct cal_ctx *ctx = notifier_to_ctx(notifier);
1988 const struct cal_fmt *fmt;
1989 struct v4l2_mbus_framefmt mbus_fmt;
1990 int ret;
1991
1992 ret = __subdev_get_format(ctx, &mbus_fmt);
1993 if (ret)
1994 return ret;
1995
1996 fmt = find_format_by_code(ctx, mbus_fmt.code);
1997 if (!fmt) {
1998 ctx_dbg(3, ctx, "mbus code format (0x%08x) not found.\n",
1999 mbus_fmt.code);
2000 return -EINVAL;
2001 }
2002
2003 /* Save current subdev format */
2004 v4l2_fill_pix_format(&ctx->v_fmt.fmt.pix, &mbus_fmt);
2005 ctx->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2006 ctx->v_fmt.fmt.pix.pixelformat = fmt->fourcc;
2007 cal_calc_format_size(ctx, fmt, &ctx->v_fmt);
2008 ctx->fmt = fmt;
2009 ctx->m_fmt = mbus_fmt;
2010
2011 return 0;
2012 }
2013
2014 static const struct v4l2_async_notifier_operations cal_async_ops = {
2015 .bound = cal_async_bound,
2016 .complete = cal_async_complete,
2017 };
2018
2019 static struct device_node *
2020 of_get_next_port(const struct device_node *parent,
2021 struct device_node *prev)
2022 {
2023 struct device_node *port;
2024
2025 if (!parent)
2026 return NULL;
2027
2028 if (!prev) {
2029 struct device_node *ports;
2030 /*
2031 * It's the first call, we have to find a port subnode
2032 * within this node or within an optional 'ports' node.
2033 */
2034 ports = of_get_child_by_name(parent, "ports");
2035 if (ports)
2036 parent = ports;
2037
2038 port = of_get_child_by_name(parent, "port");
2039
2040 /* release the 'ports' node */
2041 of_node_put(ports);
2042 } else {
2043 struct device_node *ports;
2044
2045 ports = of_get_parent(prev);
2046 if (!ports)
2047 return NULL;
2048
2049 do {
2050 port = of_get_next_child(ports, prev);
2051 if (!port) {
2052 of_node_put(ports);
2053 return NULL;
2054 }
2055 prev = port;
2056 } while (!of_node_name_eq(port, "port"));
2057 of_node_put(ports);
2058 }
2059
2060 return port;
2061 }
2062
2063 static struct device_node *
2064 of_get_next_endpoint(const struct device_node *parent,
2065 struct device_node *prev)
2066 {
2067 struct device_node *ep;
2068
2069 if (!parent)
2070 return NULL;
2071
2072 do {
2073 ep = of_get_next_child(parent, prev);
2074 if (!ep)
2075 return NULL;
2076 prev = ep;
2077 } while (!of_node_name_eq(ep, "endpoint"));
2078
2079 return ep;
2080 }
2081
2082 static int of_cal_create_instance(struct cal_ctx *ctx, int inst)
2083 {
2084 struct platform_device *pdev = ctx->cal->pdev;
2085 struct device_node *ep_node, *port, *sensor_node, *parent;
2086 struct v4l2_fwnode_endpoint *endpoint;
2087 struct v4l2_async_subdev *asd;
2088 u32 regval = 0;
2089 int ret, index, lane;
2090 bool found_port = false;
2091
2092 parent = pdev->dev.of_node;
2093
2094 endpoint = &ctx->phy->endpoint;
2095
2096 ep_node = NULL;
2097 port = NULL;
2098 sensor_node = NULL;
2099 ret = -EINVAL;
2100
2101 ctx_dbg(3, ctx, "Scanning Port node for csi2 port: %d\n", inst);
2102 for (index = 0; index < CAL_NUM_CSI2_PORTS; index++) {
2103 port = of_get_next_port(parent, port);
2104 if (!port) {
2105 ctx_dbg(1, ctx, "No port node found for csi2 port:%d\n",
2106 index);
2107 goto cleanup_exit;
2108 }
2109
2110 /* Match the slice number with <REG> */
2111 of_property_read_u32(port, "reg", &regval);
2112 ctx_dbg(3, ctx, "port:%d inst:%d <reg>:%d\n",
2113 index, inst, regval);
2114 if ((regval == inst) && (index == inst)) {
2115 found_port = true;
2116 break;
2117 }
2118 }
2119
2120 if (!found_port) {
2121 ctx_dbg(1, ctx, "No port node matches csi2 port:%d\n",
2122 inst);
2123 goto cleanup_exit;
2124 }
2125
2126 ctx_dbg(3, ctx, "Scanning sub-device for csi2 port: %d\n",
2127 inst);
2128
2129 ep_node = of_get_next_endpoint(port, ep_node);
2130 if (!ep_node) {
2131 ctx_dbg(3, ctx, "can't get next endpoint\n");
2132 goto cleanup_exit;
2133 }
2134
2135 sensor_node = of_graph_get_remote_port_parent(ep_node);
2136 if (!sensor_node) {
2137 ctx_dbg(3, ctx, "can't get remote parent\n");
2138 goto cleanup_exit;
2139 }
2140
2141 v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), endpoint);
2142
2143 if (endpoint->bus_type != V4L2_MBUS_CSI2_DPHY) {
2144 ctx_err(ctx, "Port:%d sub-device %pOFn is not a CSI2 device\n",
2145 inst, sensor_node);
2146 goto cleanup_exit;
2147 }
2148
2149 /* Store Virtual Channel number */
2150 ctx->virtual_channel = endpoint->base.id;
2151
2152 ctx_dbg(3, ctx, "Port:%d v4l2-endpoint: CSI2\n", inst);
2153 ctx_dbg(3, ctx, "Virtual Channel=%d\n", ctx->virtual_channel);
2154 ctx_dbg(3, ctx, "flags=0x%08x\n", endpoint->bus.mipi_csi2.flags);
2155 ctx_dbg(3, ctx, "clock_lane=%d\n", endpoint->bus.mipi_csi2.clock_lane);
2156 ctx_dbg(3, ctx, "num_data_lanes=%d\n",
2157 endpoint->bus.mipi_csi2.num_data_lanes);
2158 ctx_dbg(3, ctx, "data_lanes= <\n");
2159 for (lane = 0; lane < endpoint->bus.mipi_csi2.num_data_lanes; lane++)
2160 ctx_dbg(3, ctx, "\t%d\n",
2161 endpoint->bus.mipi_csi2.data_lanes[lane]);
2162 ctx_dbg(3, ctx, "\t>\n");
2163
2164 ctx_dbg(1, ctx, "Port: %d found sub-device %pOFn\n",
2165 inst, sensor_node);
2166
2167 v4l2_async_notifier_init(&ctx->notifier);
2168
2169 asd = kzalloc(sizeof(*asd), GFP_KERNEL);
2170 if (!asd)
2171 goto cleanup_exit;
2172
2173 asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
2174 asd->match.fwnode = of_fwnode_handle(sensor_node);
2175
2176 ret = v4l2_async_notifier_add_subdev(&ctx->notifier, asd);
2177 if (ret) {
2178 ctx_err(ctx, "Error adding asd\n");
2179 kfree(asd);
2180 goto cleanup_exit;
2181 }
2182
2183 ctx->notifier.ops = &cal_async_ops;
2184 ret = v4l2_async_notifier_register(&ctx->v4l2_dev,
2185 &ctx->notifier);
2186 if (ret) {
2187 ctx_err(ctx, "Error registering async notifier\n");
2188 v4l2_async_notifier_cleanup(&ctx->notifier);
2189 ret = -EINVAL;
2190 }
2191
2192 /*
2193 * On success we need to keep reference on sensor_node, or
2194 * if notifier_cleanup was called above, sensor_node was
2195 * already put.
2196 */
2197 sensor_node = NULL;
2198
2199 cleanup_exit:
2200 of_node_put(sensor_node);
2201 of_node_put(ep_node);
2202 of_node_put(port);
2203
2204 return ret;
2205 }
2206
2207 static struct cal_ctx *cal_ctx_create(struct cal_dev *cal, int inst)
2208 {
2209 struct cal_ctx *ctx;
2210 struct v4l2_ctrl_handler *hdl;
2211 int ret;
2212
2213 ctx = devm_kzalloc(&cal->pdev->dev, sizeof(*ctx), GFP_KERNEL);
2214 if (!ctx)
2215 return NULL;
2216
2217 /* save the cal_dev * for future ref */
2218 ctx->cal = cal;
2219
2220 snprintf(ctx->v4l2_dev.name, sizeof(ctx->v4l2_dev.name),
2221 "%s-%03d", CAL_MODULE_NAME, inst);
2222 ret = v4l2_device_register(&cal->pdev->dev, &ctx->v4l2_dev);
2223 if (ret)
2224 goto err_exit;
2225
2226 hdl = &ctx->ctrl_handler;
2227 ret = v4l2_ctrl_handler_init(hdl, 11);
2228 if (ret) {
2229 ctx_err(ctx, "Failed to init ctrl handler\n");
2230 goto unreg_dev;
2231 }
2232 ctx->v4l2_dev.ctrl_handler = hdl;
2233
2234 /* Make sure Camera Core H/W register area is available */
2235 ctx->phy = cal->phy[inst];
2236
2237 /* Store the instance id */
2238 ctx->index = inst;
2239 ctx->cport = inst;
2240
2241 ret = of_cal_create_instance(ctx, inst);
2242 if (ret) {
2243 ret = -EINVAL;
2244 goto free_hdl;
2245 }
2246 return ctx;
2247
2248 free_hdl:
2249 v4l2_ctrl_handler_free(hdl);
2250 unreg_dev:
2251 v4l2_device_unregister(&ctx->v4l2_dev);
2252 err_exit:
2253 return NULL;
2254 }
2255
2256 static const struct of_device_id cal_of_match[] = {
2257 {
2258 .compatible = "ti,dra72-cal",
2259 .data = (void *)&dra72x_cal_data,
2260 },
2261 {
2262 .compatible = "ti,dra72-pre-es2-cal",
2263 .data = (void *)&dra72x_es1_cal_data,
2264 },
2265 {
2266 .compatible = "ti,dra76-cal",
2267 .data = (void *)&dra76x_cal_data,
2268 },
2269 {
2270 .compatible = "ti,am654-cal",
2271 .data = (void *)&am654_cal_data,
2272 },
2273 {},
2274 };
2275 MODULE_DEVICE_TABLE(of, cal_of_match);
2276
2277 /*
2278 * Get Revision and HW info
2279 */
2280 static void cal_get_hwinfo(struct cal_dev *cal)
2281 {
2282 u32 revision;
2283 u32 hwinfo;
2284
2285 revision = reg_read(cal, CAL_HL_REVISION);
2286 cal_dbg(3, cal, "CAL_HL_REVISION = 0x%08x (expecting 0x40000200)\n",
2287 revision);
2288
2289 hwinfo = reg_read(cal, CAL_HL_HWINFO);
2290 cal_dbg(3, cal, "CAL_HL_HWINFO = 0x%08x (expecting 0xA3C90469)\n",
2291 hwinfo);
2292 }
2293
2294 static int cal_probe(struct platform_device *pdev)
2295 {
2296 struct cal_dev *cal;
2297 struct cal_ctx *ctx;
2298 unsigned int i;
2299 int ret;
2300 int irq;
2301
2302 cal = devm_kzalloc(&pdev->dev, sizeof(*cal), GFP_KERNEL);
2303 if (!cal)
2304 return -ENOMEM;
2305
2306 cal->data = of_device_get_match_data(&pdev->dev);
2307 if (!cal->data) {
2308 dev_err(&pdev->dev, "Could not get feature data based on compatible version\n");
2309 return -ENODEV;
2310 }
2311
2312 cal->pdev = pdev;
2313 platform_set_drvdata(pdev, cal);
2314
2315 /* Acquire resources: clocks, CAMERARX regmap, I/O memory and IRQ. */
2316 cal->fclk = devm_clk_get(&pdev->dev, "fck");
2317 if (IS_ERR(cal->fclk)) {
2318 dev_err(&pdev->dev, "cannot get CAL fclk\n");
2319 return PTR_ERR(cal->fclk);
2320 }
2321
2322 ret = cal_camerarx_init_regmap(cal);
2323 if (ret < 0)
2324 return ret;
2325
2326 cal->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2327 "cal_top");
2328 cal->base = devm_ioremap_resource(&pdev->dev, cal->res);
2329 if (IS_ERR(cal->base))
2330 return PTR_ERR(cal->base);
2331
2332 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
2333 cal->res->name, &cal->res->start, &cal->res->end);
2334
2335 irq = platform_get_irq(pdev, 0);
2336 cal_dbg(1, cal, "got irq# %d\n", irq);
2337 ret = devm_request_irq(&pdev->dev, irq, cal_irq, 0, CAL_MODULE_NAME,
2338 cal);
2339 if (ret)
2340 return ret;
2341
2342 /* Create CAMERARX PHYs. */
2343 for (i = 0; i < cal->data->num_csi2_phy; ++i) {
2344 cal->phy[i] = cal_camerarx_create(cal, i);
2345 if (IS_ERR(cal->phy[i]))
2346 return PTR_ERR(cal->phy[i]);
2347 }
2348
2349 /* Create contexts. */
2350 for (i = 0; i < cal->data->num_csi2_phy; ++i)
2351 cal->ctx[i] = cal_ctx_create(cal, i);
2352
2353 if (!cal->ctx[0] && !cal->ctx[1]) {
2354 cal_err(cal, "Neither port is configured, no point in staying up\n");
2355 return -ENODEV;
2356 }
2357
2358 vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
2359
2360 /* Read the revision and hardware info to verify hardware access. */
2361 pm_runtime_enable(&pdev->dev);
2362 ret = pm_runtime_get_sync(&pdev->dev);
2363 if (ret)
2364 goto runtime_disable;
2365
2366 cal_get_hwinfo(cal);
2367 pm_runtime_put_sync(&pdev->dev);
2368
2369 return 0;
2370
2371 runtime_disable:
2372 vb2_dma_contig_clear_max_seg_size(&pdev->dev);
2373
2374 pm_runtime_disable(&pdev->dev);
2375 for (i = 0; i < CAL_NUM_CONTEXT; i++) {
2376 ctx = cal->ctx[i];
2377 if (ctx) {
2378 v4l2_async_notifier_unregister(&ctx->notifier);
2379 v4l2_async_notifier_cleanup(&ctx->notifier);
2380 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
2381 v4l2_device_unregister(&ctx->v4l2_dev);
2382 }
2383 }
2384
2385 return ret;
2386 }
2387
2388 static int cal_remove(struct platform_device *pdev)
2389 {
2390 struct cal_dev *cal = platform_get_drvdata(pdev);
2391 struct cal_ctx *ctx;
2392 unsigned int i;
2393
2394 cal_dbg(1, cal, "Removing %s\n", CAL_MODULE_NAME);
2395
2396 pm_runtime_get_sync(&pdev->dev);
2397
2398 for (i = 0; i < CAL_NUM_CONTEXT; i++) {
2399 ctx = cal->ctx[i];
2400 if (ctx) {
2401 ctx_dbg(1, ctx, "unregistering %s\n",
2402 video_device_node_name(&ctx->vdev));
2403 cal_camerarx_disable(ctx->phy);
2404 v4l2_async_notifier_unregister(&ctx->notifier);
2405 v4l2_async_notifier_cleanup(&ctx->notifier);
2406 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
2407 v4l2_device_unregister(&ctx->v4l2_dev);
2408 video_unregister_device(&ctx->vdev);
2409 }
2410 }
2411
2412 pm_runtime_put_sync(&pdev->dev);
2413 pm_runtime_disable(&pdev->dev);
2414
2415 vb2_dma_contig_clear_max_seg_size(&pdev->dev);
2416
2417 return 0;
2418 }
2419
2420 static int cal_runtime_resume(struct device *dev)
2421 {
2422 struct cal_dev *cal = dev_get_drvdata(dev);
2423
2424 if (cal->data->flags & DRA72_CAL_PRE_ES2_LDO_DISABLE) {
2425 /*
2426 * Apply errata on both port everytime we (re-)enable
2427 * the clock
2428 */
2429 cal_camerarx_i913_errata(cal->phy[0]);
2430 cal_camerarx_i913_errata(cal->phy[1]);
2431 }
2432
2433 return 0;
2434 }
2435
2436 static const struct dev_pm_ops cal_pm_ops = {
2437 .runtime_resume = cal_runtime_resume,
2438 };
2439
2440 static struct platform_driver cal_pdrv = {
2441 .probe = cal_probe,
2442 .remove = cal_remove,
2443 .driver = {
2444 .name = CAL_MODULE_NAME,
2445 .pm = &cal_pm_ops,
2446 .of_match_table = cal_of_match,
2447 },
2448 };
2449
2450 module_platform_driver(cal_pdrv);
A mirror of Linus' kernel repository