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AArch64: Improve codegen in AdvSIMD pow
authorPierre Blanchard <pierre.blanchard@arm.com>
Mon, 9 Dec 2024 15:53:04 +0000 (15:53 +0000)
committerWilco Dijkstra <wilco.dijkstra@arm.com>
Mon, 9 Dec 2024 16:20:34 +0000 (16:20 +0000)
commit569cfaaf4984ae70b23c61ee28a609b5aef93fea
tree286944be23810a2f5ebf039b89322042046e6aabtree
parentb602f60f5e6178abe4b024a64c9532f78f2ecf9dcommit | diff
AArch64: Improve codegen in AdvSIMD pow

Remove spurious ADRP. Improve memory access by shuffling constants and
using more indexed MLAs.

A few more optimisation with no impact on accuracy
- force fmas contraction
- switch from shift-aided rint to rint instruction

Between 1 and 5% throughput improvement on Neoverse
V1 depending on benchmark.
sysdeps/aarch64/fpu/pow_advsimd.c diff | blob | blame | history
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