Fix invalid right shift count with recent ifcvt changes

Fix invalid right shift count with recent ifcvt changes

I got too clever trying to simplify the right shift computation in my recent
ifcvt patch.  Interestingly enough, I haven't seen anything but the Linaro CI
configuration actually trip the problem, though the code is clearly wrong.

The problem I was trying to avoid were the leading zeros when calling clz on a
HWI when the real object is just say 32 bits.

The net is we get a right shift count of "2" when we really wanted a right
shift count of 30.  That causes the execution aspect of bics_3 to fail.

The scan failures are due to creating slightly more efficient code. THe new
code sequences don't need to use conditional execution for selection and thus
we can use bic rather bics which requires a twiddle in the scan.

I reviewed recent bug reports and haven't seen one for this issue.  So no new
testcase as this is covered by the armv7 testsuite in the right configuration.

Bootstrapped and regression tested on x86_64, also verified it fixes the Linaro
reported CI failure and verified the crosses are still happy.  Pushing to the
trunk.

gcc/
	* ifcvt.cc (noce_try_sign_bit_splat): Fix right shift computation.

gcc/testsuite/
	* gcc.target/arm/bics_3.c: Adjust expected output