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AArch64: Improve codegen in SVE F32 logs
authorJoe Ramsay <Joe.Ramsay@arm.com>
Mon, 23 Sep 2024 14:30:20 +0000 (15:30 +0100)
committerWilco Dijkstra <wilco.dijkstra@arm.com>
Mon, 23 Sep 2024 14:44:07 +0000 (15:44 +0100)
commita15b1394b5eba98ffe28a02a392b587e4fe13c0d
treed80072ec1d867aab9bd0e3060ff99b43588c7046tree
parent7b8c134b5460ed933d610fa92ed1227372b68fdccommit | diff
AArch64: Improve codegen in SVE F32 logs

Reduce MOVPRFXs by using unpredicated (non-destructive) instructions
where possible.  Similar to the recent change to AdvSIMD F32 logs,
adjust special-case arguments and bounds to allow for more optimal
register usage.  For all 3 routines one MOVPRFX remains in the
reduction, which cannot be avoided as immediate AND and ASR are both
destructive.

Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
sysdeps/aarch64/fpu/log10f_sve.c diff | blob | blame | history
sysdeps/aarch64/fpu/log2f_sve.c diff | blob | blame | history
sysdeps/aarch64/fpu/logf_sve.c diff | blob | blame | history
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