[RISC-V] Fix ICE due to splitter emitting constant loads directly

[RISC-V] Fix ICE due to splitter emitting constant loads directly

This is a fix for a bug found internally in Ventana using the cf3 testsuite.

cf3 looks to be dead as a project and likely subsumed by modern fuzzers.  In
fact internally we tripped another issue with cf3 that had already been
reported by Edwin with the fuzzer he runs.

Anyway, the splitter in question blindly emits the 2nd adjusted constant into a
register, that's not valid if the constant requires any kind of synthesis --
and it well could since we're mostly focused on the first constant turning into
something that can be loaded via LUI without increasing the cost of the second
constant.

Instead of using the split RTL template, this just emits the code we want
directly, using riscv_move_insn to synthesize the constant into the provided
temporary register.

Tested in my system.  Waiting on upstream CI's verdict before moving forward.

gcc/
	* config/riscv/riscv.md (lui-constraint<X:mode>and_to_or): Do not use
	the RTL template for split code.  Emit it directly taking care to avoid
	emitting a constant load that needed synthesis.  Fix formatting.

gcc/testsuite/
	* gcc.target/riscv/ventana-16122.c: New test.