RISC-V: costs: support shift-and-add in strength-reduction

RISC-V: costs: support shift-and-add in strength-reduction

The strength-reduction implementation in expmed.cc will assess the
profitability of using shift-and-add using a RTL expression that wraps
a MULT (with a power-of-2) in a PLUS.  Unless the RISC-V rtx_costs
function recognizes this as expressing a sh[123]add instruction, we
will return an inflated cost---thus defeating the optimization.

This change adds the necessary idiom recognition to provide an
accurate cost for this for of expressing sh[123]add.

Instead on expanding to
	li	a5,200
	mulw	a0,a5,a0
with this change, the expression 'a * 200' is sythesized as:
	sh2add	a0,a0,a0   // *5 = a + 4 * a
	sh2add	a0,a0,a0   // *5 = a + 4 * a
	slli	a0,a0,3    // *8

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_rtx_costs): Recognize shNadd,
	if expressed as a plus and multiplication with a power-of-2.
	Split costing for MINUS from PLUS.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zba-shNadd-07.c: New test.