[PATCH PR81228][AARCH64]Fix ICE by adding LTGT in vec_cmp<mode><v_int_equiv>

[PATCH PR81228][AARCH64]Fix ICE by adding LTGT in vec_cmp<mode><v_int_equiv>

This patch is a follow up to the existing discussions on
https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01904.html
Bin had earlier submitted this patch to fix the ICE that
occurs because of the missing LTGT in aarch64-simd.md.
That discussion opened up a new bug report PR81647 for
an inconsistent behavior.

As discussed earlier on the gcc-patches discussion and on
the bug report, PR81647 was occurring because of how UNEQ
was handled in aarch64-simd.md rather than LTGT.
Since __builtin_islessgreater is guaranteed to not give an
FP exception but LTGT might, __builtin_islessgreater gets
converted to ~UNEQ very early on in fold_builtin_unordered_cmp.
Thus I will post a separate patch for correcting how UNEQ and
other unordered comparisons are handled in aarch64-simd.md.

This patch is only adding the missing LTGT to plug the ICE.

Testing done: Checked for regressions on bootstrapped
aarch64-none-linux-gnu and added a new compile time test case
that gives out LTGT to make sure it doesn't ICE

*** gcc/ChangeLog ***

2017-12-14  Sudakshina Das  <sudi.das@arm.com>
	    Bin Cheng  <bin.cheng@arm.com>

	PR target/81228
	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Move LTGT
	to CCFPEmode.
	* config/aarch64/aarch64-simd.md (vec_cmp<mode><v_int_equiv>): Add
	LTGT.

*** gcc/testsuite/ChangeLog ***

2017-12-14  Sudakshina Das  <sudi.das@arm.com>

	PR target/81228
	* gcc.dg/pr81228.c: New.

Co-Authored-By: Bin Cheng <bin.cheng@arm.com>
From-SVN: r255625