From 0085d49d30124a3b0cfd04357d22588815c5563b Mon Sep 17 00:00:00 2001 From: Matt Atwood Date: Sat, 14 Jun 2025 01:01:42 +0530 Subject: [PATCH] drm/i915: Set max cdclk for display 30.02 Display version 30.02 has a lower max cdclk rate than 30.00. Bspec: 68861 Signed-off-by: Matt Atwood Signed-off-by: Dnyaneshwar Bhadane Reviewed-by: Matt Roper Signed-off-by: Matt Roper Link: https://lore.kernel.org/r/20250613193146.3549862-6-dnyaneshwar.bhadane@intel.com --- drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 38b3094b37d7f..1cbb1d526fe87 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3386,7 +3386,9 @@ static int intel_compute_max_dotclk(struct intel_display *display) */ void intel_update_max_cdclk(struct intel_display *display) { - if (DISPLAY_VER(display) >= 30) { + if (DISPLAY_VERx100(display) >= 3002) { + display->cdclk.max_cdclk_freq = 480000; + } else if (DISPLAY_VER(display) >= 30) { display->cdclk.max_cdclk_freq = 691200; } else if (display->platform.jasperlake || display->platform.elkhartlake) { if (display->cdclk.hw.ref == 24000) -- 2.47.2