From 00b98ae50e480b0af997b22e78cd95c84acb6a50 Mon Sep 17 00:00:00 2001 From: Julian Seward Date: Tue, 27 Dec 2005 14:03:47 +0000 Subject: [PATCH] Merge r5262 (fix for: fsub 3,3,3 in ppc32 dispatcher doesn't clear NaNs) git-svn-id: svn://svn.valgrind.org/valgrind/branches/VALGRIND_3_1_BRANCH@5446 --- coregrind/m_dispatch/dispatch-ppc32-linux.S | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/coregrind/m_dispatch/dispatch-ppc32-linux.S b/coregrind/m_dispatch/dispatch-ppc32-linux.S index d3e6e1dd11..6973bb6356 100644 --- a/coregrind/m_dispatch/dispatch-ppc32-linux.S +++ b/coregrind/m_dispatch/dispatch-ppc32-linux.S @@ -163,8 +163,8 @@ LafterVMX1: stw 3,28(1) /* spill orig guest_state ptr */ /* 24(sp) used later to stop ctr reg being clobbered */ - - /* 8:20(sp) free */ + /* 20(sp) used later to load fpscr with zero */ + /* 8:16(sp) free */ /* Linkage Area (reserved) 4(sp) : LR @@ -190,7 +190,14 @@ LafterVMX1: cmplwi 3,0 beq LafterFP2 - fsub 3,3,3 /* generate zero */ + /* get zero into f3 (tedious) */ + /* note: fsub 3,3,3 is not a reliable way to do this, + since if f3 holds a NaN or similar then we don't necessarily + wind up with zero. */ + li 3,0 + stw 3,20(1) + lfs 3,20(1) + /* load f3 to fpscr (0xFF = all bit fields) */ mtfsf 0xFF,3 LafterFP2: -- 2.47.2