From 0100a04a55685b6bfb2ea40e9d6882cc35e2e433 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 5 Mar 2025 09:55:36 +0100 Subject: [PATCH] arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style Reorder properties to comply with the DeviceTree coding style guidelines: https://docs.kernel.org/devicetree/bindings/dts-coding-style.html Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20250305085537.3976579-4-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 12 ++++++------ .../boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 14 +++++++------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index c95f9d642f0d4..d9d491b12c33a 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -212,22 +212,22 @@ }; &cpsw3g_mdio { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&cpsw_mdio_pins_default>; bootph-all; + status = "okay"; cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <1>; interrupt-parent = <&main_gpio0>; interrupts = <84 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; bootph-all; + ti,rx-internal-delay = ; + ti,fifo-depth = ; }; }; @@ -276,11 +276,11 @@ }; &main_i2c0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; bootph-all; + status = "okay"; eeprom@50 { compatible = "atmel,24c32"; @@ -381,9 +381,9 @@ }; &ospi0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; serial_flash: flash@0 { compatible = "jedec,spi-nor"; @@ -401,12 +401,12 @@ }; &sdhci0 { - status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; keep-power-in-suspend; bootph-all; + status = "okay"; }; &tscadc0 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 6fbd8d932396a..f63c101b7d61a 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -352,10 +352,10 @@ }; &main_i2c1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; + status = "okay"; eeprom@51 { compatible = "atmel,24c02"; @@ -385,25 +385,25 @@ }; &main_mcan0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan0_pins_default>; phys = <&can_tc1>; + status = "okay"; }; &main_mcan1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan1_pins_default>; phys = <&can_tc2>; + status = "okay"; }; &main_spi0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>; ti,pindir-d0-out-d1-in; + status = "okay"; tpm@1 { compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; @@ -413,27 +413,27 @@ }; &main_uart0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; bootph-all; + status = "okay"; }; &main_uart1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; uart-has-rtscts; + status = "okay"; }; &sdhci1 { - status = "okay"; vmmc-supply = <&vcc_3v3_mmc>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; no-1-8-v; bootph-all; + status = "okay"; }; &serdes0 { -- 2.47.2