From 011ec88dd2ba2bc065c678cf20431e11dc33a531 Mon Sep 17 00:00:00 2001 From: Ju-Zhe Zhong Date: Tue, 7 Feb 2023 14:33:28 +0800 Subject: [PATCH] RISC-V: Add vwcvt C API test gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vwcvt_x-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x-3.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_m-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_m-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_m-3.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vwcvt_x-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_m-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvt_x_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvt_x_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvt_x_tumu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwcvtu_x_tumu-3.c | 111 ++++++++++++++++++ 36 files changed, 3996 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-1.c new file mode 100644 index 000000000000..43b38ac1563b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4(vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4(src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2(vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2(src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1(vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1(src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2(vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2(src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4(vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4(src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8(vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8(src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2(vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2(src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1(vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1(src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2(vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2(src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4(vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4(src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8(vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8(src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1(vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1(src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2(vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2(src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4(vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4(src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8(vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8(src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-2.c new file mode 100644 index 000000000000..6b03c04bc1e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4(vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4(src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2(vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2(src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1(vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1(src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2(vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2(src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4(vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4(src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8(vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8(src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2(vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2(src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1(vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1(src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2(vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2(src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4(vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4(src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8(vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8(src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1(vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1(src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2(vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2(src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4(vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4(src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8(vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8(src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-3.c new file mode 100644 index 000000000000..15eae6769d67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4(vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4(src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2(vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2(src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1(vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1(src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2(vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2(src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4(vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4(src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8(vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8(src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2(vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2(src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1(vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1(src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2(vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2(src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4(vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4(src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8(vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8(src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1(vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1(src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2(vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2(src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4(vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4(src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8(vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8(src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-1.c new file mode 100644 index 000000000000..4809bd72265a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_m(vbool64_t mask,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_m(mask,src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_m(vbool32_t mask,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_m(mask,src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_m(vbool16_t mask,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_m(mask,src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_m(vbool8_t mask,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_m(mask,src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_m(vbool4_t mask,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_m(mask,src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_m(vbool2_t mask,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_m(mask,src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_m(vbool64_t mask,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_m(mask,src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_m(vbool32_t mask,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_m(mask,src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_m(vbool16_t mask,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_m(mask,src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_m(vbool8_t mask,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_m(mask,src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_m(vbool4_t mask,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_m(mask,src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_m(vbool64_t mask,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_m(mask,src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_m(vbool32_t mask,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_m(mask,src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_m(vbool16_t mask,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_m(mask,src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_m(vbool8_t mask,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_m(mask,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-2.c new file mode 100644 index 000000000000..ac6f904a02e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_m(vbool64_t mask,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_m(mask,src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_m(vbool32_t mask,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_m(mask,src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_m(vbool16_t mask,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_m(mask,src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_m(vbool8_t mask,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_m(mask,src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_m(vbool4_t mask,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_m(mask,src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_m(vbool2_t mask,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_m(mask,src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_m(vbool64_t mask,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_m(mask,src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_m(vbool32_t mask,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_m(mask,src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_m(vbool16_t mask,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_m(mask,src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_m(vbool8_t mask,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_m(mask,src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_m(vbool4_t mask,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_m(mask,src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_m(vbool64_t mask,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_m(mask,src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_m(vbool32_t mask,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_m(mask,src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_m(vbool16_t mask,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_m(mask,src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_m(vbool8_t mask,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_m(mask,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-3.c new file mode 100644 index 000000000000..cbbbb258283e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_m(vbool64_t mask,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_m(mask,src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_m(vbool32_t mask,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_m(mask,src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_m(vbool16_t mask,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_m(mask,src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_m(vbool8_t mask,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_m(mask,src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_m(vbool4_t mask,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_m(mask,src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_m(vbool2_t mask,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_m(mask,src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_m(vbool64_t mask,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_m(mask,src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_m(vbool32_t mask,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_m(mask,src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_m(vbool16_t mask,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_m(mask,src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_m(vbool8_t mask,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_m(mask,src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_m(vbool4_t mask,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_m(mask,src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_m(vbool64_t mask,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_m(mask,src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_m(vbool32_t mask,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_m(mask,src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_m(vbool16_t mask,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_m(mask,src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_m(vbool8_t mask,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_m(mask,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c new file mode 100644 index 000000000000..2f635736b28a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_mu(mask,merge,src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_mu(mask,merge,src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_mu(mask,merge,src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_mu(mask,merge,src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_mu(mask,merge,src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_mu(mask,merge,src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_mu(mask,merge,src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_mu(mask,merge,src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_mu(mask,merge,src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_mu(mask,merge,src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_mu(mask,merge,src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_mu(mask,merge,src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_mu(mask,merge,src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_mu(mask,merge,src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_mu(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c new file mode 100644 index 000000000000..27a834cde4b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_mu(mask,merge,src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_mu(mask,merge,src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_mu(mask,merge,src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_mu(mask,merge,src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_mu(mask,merge,src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_mu(mask,merge,src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_mu(mask,merge,src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_mu(mask,merge,src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_mu(mask,merge,src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_mu(mask,merge,src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_mu(mask,merge,src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_mu(mask,merge,src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_mu(mask,merge,src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_mu(mask,merge,src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_mu(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c new file mode 100644 index 000000000000..a323f50af96d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_mu(mask,merge,src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_mu(mask,merge,src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_mu(mask,merge,src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_mu(mask,merge,src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_mu(mask,merge,src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_mu(mask,merge,src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_mu(mask,merge,src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_mu(mask,merge,src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_mu(mask,merge,src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_mu(mask,merge,src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_mu(mask,merge,src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_mu(mask,merge,src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_mu(mask,merge,src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_mu(mask,merge,src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_mu(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c new file mode 100644 index 000000000000..9547f9206d44 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tu(vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tu(merge,src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tu(vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tu(merge,src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tu(vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tu(merge,src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tu(vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tu(merge,src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tu(vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tu(merge,src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tu(vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tu(merge,src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tu(vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tu(merge,src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tu(vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tu(merge,src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tu(vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tu(merge,src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tu(vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tu(merge,src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tu(vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tu(merge,src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tu(vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tu(merge,src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tu(vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tu(merge,src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tu(vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tu(merge,src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tu(vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tu(merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c new file mode 100644 index 000000000000..f0fcdfab0c81 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tu(vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tu(merge,src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tu(vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tu(merge,src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tu(vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tu(merge,src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tu(vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tu(merge,src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tu(vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tu(merge,src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tu(vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tu(merge,src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tu(vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tu(merge,src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tu(vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tu(merge,src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tu(vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tu(merge,src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tu(vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tu(merge,src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tu(vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tu(merge,src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tu(vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tu(merge,src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tu(vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tu(merge,src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tu(vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tu(merge,src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tu(vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tu(merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c new file mode 100644 index 000000000000..f279382b3d2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tu(vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tu(merge,src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tu(vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tu(merge,src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tu(vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tu(merge,src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tu(vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tu(merge,src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tu(vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tu(merge,src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tu(vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tu(merge,src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tu(vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tu(merge,src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tu(vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tu(merge,src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tu(vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tu(merge,src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tu(vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tu(merge,src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tu(vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tu(merge,src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tu(vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tu(merge,src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tu(vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tu(merge,src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tu(vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tu(merge,src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tu(vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tu(merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c new file mode 100644 index 000000000000..573a1f1c416f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tum(mask,merge,src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tum(mask,merge,src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tum(mask,merge,src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tum(mask,merge,src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tum(mask,merge,src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tum(mask,merge,src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tum(mask,merge,src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tum(mask,merge,src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tum(mask,merge,src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tum(mask,merge,src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tum(mask,merge,src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tum(mask,merge,src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tum(mask,merge,src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tum(mask,merge,src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tum(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c new file mode 100644 index 000000000000..c18da782ff3c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tum(mask,merge,src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tum(mask,merge,src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tum(mask,merge,src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tum(mask,merge,src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tum(mask,merge,src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tum(mask,merge,src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tum(mask,merge,src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tum(mask,merge,src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tum(mask,merge,src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tum(mask,merge,src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tum(mask,merge,src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tum(mask,merge,src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tum(mask,merge,src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tum(mask,merge,src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tum(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c new file mode 100644 index 000000000000..5ac16b4c2131 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tum(mask,merge,src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tum(mask,merge,src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tum(mask,merge,src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tum(mask,merge,src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tum(mask,merge,src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tum(mask,merge,src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tum(mask,merge,src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tum(mask,merge,src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tum(mask,merge,src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tum(mask,merge,src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tum(mask,merge,src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tum(mask,merge,src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tum(mask,merge,src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tum(mask,merge,src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tum(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c new file mode 100644 index 000000000000..4fe5a55f5d19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tumu(mask,merge,src,vl); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tumu(mask,merge,src,vl); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tumu(mask,merge,src,vl); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tumu(mask,merge,src,vl); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tumu(mask,merge,src,vl); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tumu(mask,merge,src,vl); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tumu(mask,merge,src,vl); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tumu(mask,merge,src,vl); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tumu(mask,merge,src,vl); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tumu(mask,merge,src,vl); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tumu(mask,merge,src,vl); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tumu(mask,merge,src,vl); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tumu(mask,merge,src,vl); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tumu(mask,merge,src,vl); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tumu(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c new file mode 100644 index 000000000000..ae292da32dfe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tumu(mask,merge,src,31); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tumu(mask,merge,src,31); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tumu(mask,merge,src,31); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tumu(mask,merge,src,31); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tumu(mask,merge,src,31); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tumu(mask,merge,src,31); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tumu(mask,merge,src,31); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tumu(mask,merge,src,31); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tumu(mask,merge,src,31); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tumu(mask,merge,src,31); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tumu(mask,merge,src,31); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tumu(mask,merge,src,31); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tumu(mask,merge,src,31); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tumu(mask,merge,src,31); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tumu(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c new file mode 100644 index 000000000000..4e26fa30f533 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwcvt_x_x_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf4_tumu(mask,merge,src,32); +} + + +vint16mf2_t test___riscv_vwcvt_x_x_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16mf2_tumu(mask,merge,src,32); +} + + +vint16m1_t test___riscv_vwcvt_x_x_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m1_tumu(mask,merge,src,32); +} + + +vint16m2_t test___riscv_vwcvt_x_x_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m2_tumu(mask,merge,src,32); +} + + +vint16m4_t test___riscv_vwcvt_x_x_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m4_tumu(mask,merge,src,32); +} + + +vint16m8_t test___riscv_vwcvt_x_x_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i16m8_tumu(mask,merge,src,32); +} + + +vint32mf2_t test___riscv_vwcvt_x_x_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32mf2_tumu(mask,merge,src,32); +} + + +vint32m1_t test___riscv_vwcvt_x_x_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m1_tumu(mask,merge,src,32); +} + + +vint32m2_t test___riscv_vwcvt_x_x_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m2_tumu(mask,merge,src,32); +} + + +vint32m4_t test___riscv_vwcvt_x_x_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m4_tumu(mask,merge,src,32); +} + + +vint32m8_t test___riscv_vwcvt_x_x_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i32m8_tumu(mask,merge,src,32); +} + + +vint64m1_t test___riscv_vwcvt_x_x_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m1_tumu(mask,merge,src,32); +} + + +vint64m2_t test___riscv_vwcvt_x_x_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m2_tumu(mask,merge,src,32); +} + + +vint64m4_t test___riscv_vwcvt_x_x_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m4_tumu(mask,merge,src,32); +} + + +vint64m8_t test___riscv_vwcvt_x_x_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl) +{ + return __riscv_vwcvt_x_x_v_i64m8_tumu(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-1.c new file mode 100644 index 000000000000..614b2f6cc81b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4(vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4(src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2(vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2(src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1(vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1(src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2(vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2(src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4(vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4(src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8(vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8(src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2(vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2(src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1(vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1(src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2(vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2(src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4(vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4(src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8(vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8(src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1(vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1(src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2(vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2(src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4(vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4(src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8(vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8(src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-2.c new file mode 100644 index 000000000000..0f331b1ed989 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4(vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4(src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2(vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2(src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1(vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1(src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2(vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2(src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4(vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4(src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8(vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8(src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2(vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2(src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1(vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1(src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2(vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2(src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4(vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4(src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8(vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8(src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1(vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1(src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2(vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2(src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4(vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4(src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8(vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8(src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-3.c new file mode 100644 index 000000000000..00d6f3cd2dfc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4(vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4(src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2(vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2(src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1(vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1(src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2(vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2(src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4(vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4(src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8(vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8(src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2(vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2(src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1(vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1(src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2(vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2(src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4(vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4(src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8(vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8(src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1(vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1(src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2(vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2(src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4(vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4(src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8(vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8(src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c new file mode 100644 index 000000000000..a328f719658f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_m(vbool64_t mask,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_m(mask,src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_m(vbool32_t mask,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_m(mask,src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_m(vbool16_t mask,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_m(mask,src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_m(vbool8_t mask,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_m(mask,src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_m(vbool4_t mask,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_m(mask,src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_m(vbool2_t mask,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_m(mask,src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_m(vbool64_t mask,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_m(mask,src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_m(vbool32_t mask,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_m(mask,src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_m(vbool16_t mask,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_m(mask,src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_m(vbool8_t mask,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_m(mask,src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_m(vbool4_t mask,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_m(mask,src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_m(vbool64_t mask,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_m(mask,src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_m(vbool32_t mask,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_m(mask,src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_m(vbool16_t mask,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_m(mask,src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_m(vbool8_t mask,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_m(mask,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c new file mode 100644 index 000000000000..87e262148098 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_m(vbool64_t mask,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_m(mask,src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_m(vbool32_t mask,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_m(mask,src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_m(vbool16_t mask,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_m(mask,src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_m(vbool8_t mask,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_m(mask,src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_m(vbool4_t mask,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_m(mask,src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_m(vbool2_t mask,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_m(mask,src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_m(vbool64_t mask,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_m(mask,src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_m(vbool32_t mask,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_m(mask,src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_m(vbool16_t mask,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_m(mask,src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_m(vbool8_t mask,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_m(mask,src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_m(vbool4_t mask,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_m(mask,src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_m(vbool64_t mask,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_m(mask,src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_m(vbool32_t mask,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_m(mask,src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_m(vbool16_t mask,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_m(mask,src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_m(vbool8_t mask,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_m(mask,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c new file mode 100644 index 000000000000..49d5713fe1f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_m(vbool64_t mask,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_m(mask,src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_m(vbool32_t mask,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_m(mask,src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_m(vbool16_t mask,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_m(mask,src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_m(vbool8_t mask,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_m(mask,src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_m(vbool4_t mask,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_m(mask,src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_m(vbool2_t mask,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_m(mask,src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_m(vbool64_t mask,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_m(mask,src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_m(vbool32_t mask,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_m(mask,src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_m(vbool16_t mask,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_m(mask,src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_m(vbool8_t mask,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_m(mask,src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_m(vbool4_t mask,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_m(mask,src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_m(vbool64_t mask,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_m(mask,src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_m(vbool32_t mask,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_m(mask,src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_m(vbool16_t mask,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_m(mask,src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_m(vbool8_t mask,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_m(mask,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c new file mode 100644 index 000000000000..96c14911e7c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_mu(mask,merge,src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_mu(mask,merge,src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_mu(mask,merge,src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_mu(mask,merge,src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_mu(mask,merge,src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_mu(mask,merge,src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_mu(mask,merge,src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_mu(mask,merge,src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_mu(mask,merge,src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_mu(mask,merge,src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_mu(mask,merge,src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_mu(mask,merge,src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_mu(mask,merge,src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_mu(mask,merge,src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_mu(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c new file mode 100644 index 000000000000..7ce833acebeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_mu(mask,merge,src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_mu(mask,merge,src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_mu(mask,merge,src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_mu(mask,merge,src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_mu(mask,merge,src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_mu(mask,merge,src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_mu(mask,merge,src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_mu(mask,merge,src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_mu(mask,merge,src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_mu(mask,merge,src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_mu(mask,merge,src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_mu(mask,merge,src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_mu(mask,merge,src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_mu(mask,merge,src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_mu(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c new file mode 100644 index 000000000000..6bc2904cae9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_mu(mask,merge,src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_mu(mask,merge,src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_mu(mask,merge,src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_mu(mask,merge,src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_mu(mask,merge,src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_mu(mask,merge,src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_mu(mask,merge,src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_mu(mask,merge,src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_mu(mask,merge,src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_mu(mask,merge,src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_mu(mask,merge,src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_mu(mask,merge,src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_mu(mask,merge,src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_mu(mask,merge,src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_mu(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c new file mode 100644 index 000000000000..481384ea6cc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tu(merge,src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tu(merge,src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tu(vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tu(merge,src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tu(vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tu(merge,src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tu(vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tu(merge,src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tu(vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tu(merge,src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tu(merge,src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tu(vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tu(merge,src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tu(vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tu(merge,src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tu(vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tu(merge,src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tu(vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tu(merge,src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tu(vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tu(merge,src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tu(vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tu(merge,src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tu(vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tu(merge,src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tu(vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tu(merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c new file mode 100644 index 000000000000..decca0134b96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tu(merge,src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tu(merge,src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tu(vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tu(merge,src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tu(vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tu(merge,src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tu(vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tu(merge,src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tu(vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tu(merge,src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tu(merge,src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tu(vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tu(merge,src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tu(vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tu(merge,src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tu(vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tu(merge,src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tu(vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tu(merge,src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tu(vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tu(merge,src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tu(vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tu(merge,src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tu(vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tu(merge,src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tu(vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tu(merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c new file mode 100644 index 000000000000..12956462bc06 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tu(merge,src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tu(merge,src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tu(vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tu(merge,src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tu(vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tu(merge,src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tu(vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tu(merge,src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tu(vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tu(merge,src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tu(merge,src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tu(vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tu(merge,src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tu(vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tu(merge,src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tu(vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tu(merge,src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tu(vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tu(merge,src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tu(vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tu(merge,src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tu(vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tu(merge,src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tu(vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tu(merge,src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tu(vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tu(merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c new file mode 100644 index 000000000000..0c0f51397613 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tum(mask,merge,src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tum(mask,merge,src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tum(mask,merge,src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tum(mask,merge,src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tum(mask,merge,src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tum(mask,merge,src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tum(mask,merge,src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tum(mask,merge,src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tum(mask,merge,src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tum(mask,merge,src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tum(mask,merge,src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tum(mask,merge,src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tum(mask,merge,src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tum(mask,merge,src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tum(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c new file mode 100644 index 000000000000..37981fedc85c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tum(mask,merge,src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tum(mask,merge,src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tum(mask,merge,src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tum(mask,merge,src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tum(mask,merge,src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tum(mask,merge,src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tum(mask,merge,src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tum(mask,merge,src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tum(mask,merge,src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tum(mask,merge,src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tum(mask,merge,src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tum(mask,merge,src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tum(mask,merge,src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tum(mask,merge,src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tum(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c new file mode 100644 index 000000000000..9320c6f1c773 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tum(mask,merge,src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tum(mask,merge,src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tum(mask,merge,src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tum(mask,merge,src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tum(mask,merge,src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tum(mask,merge,src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tum(mask,merge,src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tum(mask,merge,src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tum(mask,merge,src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tum(mask,merge,src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tum(mask,merge,src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tum(mask,merge,src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tum(mask,merge,src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tum(mask,merge,src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tum(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c new file mode 100644 index 000000000000..aaf285c333c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tumu(mask,merge,src,vl); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tumu(mask,merge,src,vl); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tumu(mask,merge,src,vl); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tumu(mask,merge,src,vl); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tumu(mask,merge,src,vl); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tumu(mask,merge,src,vl); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tumu(mask,merge,src,vl); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tumu(mask,merge,src,vl); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tumu(mask,merge,src,vl); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tumu(mask,merge,src,vl); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tumu(mask,merge,src,vl); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tumu(mask,merge,src,vl); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tumu(mask,merge,src,vl); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tumu(mask,merge,src,vl); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tumu(mask,merge,src,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c new file mode 100644 index 000000000000..4acf2a0c1597 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tumu(mask,merge,src,31); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tumu(mask,merge,src,31); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tumu(mask,merge,src,31); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tumu(mask,merge,src,31); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tumu(mask,merge,src,31); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tumu(mask,merge,src,31); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tumu(mask,merge,src,31); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tumu(mask,merge,src,31); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tumu(mask,merge,src,31); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tumu(mask,merge,src,31); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tumu(mask,merge,src,31); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tumu(mask,merge,src,31); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tumu(mask,merge,src,31); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tumu(mask,merge,src,31); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tumu(mask,merge,src,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c new file mode 100644 index 000000000000..05dbe8434054 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwcvtu_x_x_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf4_tumu(mask,merge,src,32); +} + + +vuint16mf2_t test___riscv_vwcvtu_x_x_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16mf2_tumu(mask,merge,src,32); +} + + +vuint16m1_t test___riscv_vwcvtu_x_x_v_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m1_tumu(mask,merge,src,32); +} + + +vuint16m2_t test___riscv_vwcvtu_x_x_v_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m2_tumu(mask,merge,src,32); +} + + +vuint16m4_t test___riscv_vwcvtu_x_x_v_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m4_tumu(mask,merge,src,32); +} + + +vuint16m8_t test___riscv_vwcvtu_x_x_v_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u16m8_tumu(mask,merge,src,32); +} + + +vuint32mf2_t test___riscv_vwcvtu_x_x_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32mf2_tumu(mask,merge,src,32); +} + + +vuint32m1_t test___riscv_vwcvtu_x_x_v_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m1_tumu(mask,merge,src,32); +} + + +vuint32m2_t test___riscv_vwcvtu_x_x_v_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m2_tumu(mask,merge,src,32); +} + + +vuint32m4_t test___riscv_vwcvtu_x_x_v_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m4_tumu(mask,merge,src,32); +} + + +vuint32m8_t test___riscv_vwcvtu_x_x_v_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u32m8_tumu(mask,merge,src,32); +} + + +vuint64m1_t test___riscv_vwcvtu_x_x_v_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m1_tumu(mask,merge,src,32); +} + + +vuint64m2_t test___riscv_vwcvtu_x_x_v_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m2_tumu(mask,merge,src,32); +} + + +vuint64m4_t test___riscv_vwcvtu_x_x_v_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m4_tumu(mask,merge,src,32); +} + + +vuint64m8_t test___riscv_vwcvtu_x_x_v_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl) +{ + return __riscv_vwcvtu_x_x_v_u64m8_tumu(mask,merge,src,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ -- 2.47.2