From 024d8f4aa35970c4563c6ef0c4170133719b2103 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 13 Jan 2026 10:59:02 +0000 Subject: [PATCH] arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Enable the cmu_dpu clock management unit. It feeds some of the display IPs. Additionally add the sysreg_dpu node which contains the BUSCOMPONENT_DRCG_EN and MEMCLK registers required by cmu_dpu to enable dynamic root clock gating of bus components. Reviewed-by: André Draszik Signed-off-by: Peter Griffin Link: https://patch.msgid.link/20260113-dpu-clocks-v3-5-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 48f3819590cf8..d085f9fb0f62a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1815,6 +1815,23 @@ status = "disabled"; }; + cmu_dpu: clock-controller@1c000000 { + compatible = "google,gs101-cmu-dpu"; + reg = <0x1c000000 0x10000>; + #clock-cells = <1>; + + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_DPU_BUS>; + clock-names = "oscclk", "bus"; + samsung,sysreg = <&sysreg_dpu>; + }; + + sysreg_dpu: syscon@1c020000 { + compatible = "google,gs101-dpu-sysreg", "syscon"; + reg = <0x1c020000 0x10000>; + clocks = <&cmu_dpu CLK_GOUT_DPU_SYSREG_DPU_PCLK>; + }; + cmu_top: clock-controller@1e080000 { compatible = "google,gs101-cmu-top"; reg = <0x1e080000 0x10000>; -- 2.47.3