From 0337fa5644e2201701b8ad40959fa5e0432fc681 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 12 Jul 2025 16:23:33 +0200 Subject: [PATCH] 5.15-stable patches added patches: gre-fix-ipv6-multicast-route-creation.patch pinctrl-qcom-msm-mark-certain-pins-as-invalid-for-interrupts.patch x86-mce-amd-fix-threshold-limit-reset.patch x86-mce-don-t-remove-sysfs-if-thresholding-sysfs-init-fails.patch x86-mce-make-sure-cmci-banks-are-cleared-during-shutdown-on-intel.patch --- ...re-fix-ipv6-multicast-route-creation.patch | 67 +++++++++++++++++ ...rtain-pins-as-invalid-for-interrupts.patch | 71 +++++++++++++++++++ queue-5.15/series | 5 ++ ...86-mce-amd-fix-threshold-limit-reset.patch | 59 +++++++++++++++ ...sfs-if-thresholding-sysfs-init-fails.patch | 52 ++++++++++++++ ...are-cleared-during-shutdown-on-intel.patch | 40 +++++++++++ 6 files changed, 294 insertions(+) create mode 100644 queue-5.15/gre-fix-ipv6-multicast-route-creation.patch create mode 100644 queue-5.15/pinctrl-qcom-msm-mark-certain-pins-as-invalid-for-interrupts.patch create mode 100644 queue-5.15/x86-mce-amd-fix-threshold-limit-reset.patch create mode 100644 queue-5.15/x86-mce-don-t-remove-sysfs-if-thresholding-sysfs-init-fails.patch create mode 100644 queue-5.15/x86-mce-make-sure-cmci-banks-are-cleared-during-shutdown-on-intel.patch diff --git a/queue-5.15/gre-fix-ipv6-multicast-route-creation.patch b/queue-5.15/gre-fix-ipv6-multicast-route-creation.patch new file mode 100644 index 0000000000..a7d76f3c6c --- /dev/null +++ b/queue-5.15/gre-fix-ipv6-multicast-route-creation.patch @@ -0,0 +1,67 @@ +From 4e914ef063de40397e25a025c70d9737a9e45a8c Mon Sep 17 00:00:00 2001 +From: Guillaume Nault +Date: Wed, 9 Jul 2025 16:30:10 +0200 +Subject: gre: Fix IPv6 multicast route creation. + +From: Guillaume Nault + +commit 4e914ef063de40397e25a025c70d9737a9e45a8c upstream. + +Use addrconf_add_dev() instead of ipv6_find_idev() in +addrconf_gre_config() so that we don't just get the inet6_dev, but also +install the default ff00::/8 multicast route. + +Before commit 3e6a0243ff00 ("gre: Fix again IPv6 link-local address +generation."), the multicast route was created at the end of the +function by addrconf_add_mroute(). But this code path is now only taken +in one particular case (gre devices not bound to a local IP address and +in EUI64 mode). For all other cases, the function exits early and +addrconf_add_mroute() is not called anymore. + +Using addrconf_add_dev() instead of ipv6_find_idev() in +addrconf_gre_config(), fixes the problem as it will create the default +multicast route for all gre devices. This also brings +addrconf_gre_config() a bit closer to the normal netdevice IPv6 +configuration code (addrconf_dev_config()). + +Cc: stable@vger.kernel.org +Fixes: 3e6a0243ff00 ("gre: Fix again IPv6 link-local address generation.") +Reported-by: Aiden Yang +Closes: https://lore.kernel.org/netdev/CANR=AhRM7YHHXVxJ4DmrTNMeuEOY87K2mLmo9KMed1JMr20p6g@mail.gmail.com/ +Reviewed-by: Gary Guo +Tested-by: Gary Guo +Signed-off-by: Guillaume Nault +Reviewed-by: Ido Schimmel +Link: https://patch.msgid.link/027a923dcb550ad115e6d93ee8bb7d310378bd01.1752070620.git.gnault@redhat.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Greg Kroah-Hartman +--- + net/ipv6/addrconf.c | 9 ++------- + 1 file changed, 2 insertions(+), 7 deletions(-) + +--- a/net/ipv6/addrconf.c ++++ b/net/ipv6/addrconf.c +@@ -3453,11 +3453,9 @@ static void addrconf_gre_config(struct n + + ASSERT_RTNL(); + +- idev = ipv6_find_idev(dev); +- if (IS_ERR(idev)) { +- pr_debug("%s: add_dev failed\n", __func__); ++ idev = addrconf_add_dev(dev); ++ if (IS_ERR(idev)) + return; +- } + + /* Generate the IPv6 link-local address using addrconf_addr_gen(), + * unless we have an IPv4 GRE device not bound to an IP address and +@@ -3471,9 +3469,6 @@ static void addrconf_gre_config(struct n + } + + add_v4_addrs(idev); +- +- if (dev->flags & IFF_POINTOPOINT) +- addrconf_add_mroute(dev); + } + #endif + diff --git a/queue-5.15/pinctrl-qcom-msm-mark-certain-pins-as-invalid-for-interrupts.patch b/queue-5.15/pinctrl-qcom-msm-mark-certain-pins-as-invalid-for-interrupts.patch new file mode 100644 index 0000000000..ae6e0ac770 --- /dev/null +++ b/queue-5.15/pinctrl-qcom-msm-mark-certain-pins-as-invalid-for-interrupts.patch @@ -0,0 +1,71 @@ +From 93712205ce2f1fb047739494c0399a26ea4f0890 Mon Sep 17 00:00:00 2001 +From: Bartosz Golaszewski +Date: Thu, 12 Jun 2025 11:14:48 +0200 +Subject: pinctrl: qcom: msm: mark certain pins as invalid for interrupts + +From: Bartosz Golaszewski + +commit 93712205ce2f1fb047739494c0399a26ea4f0890 upstream. + +On some platforms, the UFS-reset pin has no interrupt logic in TLMM but +is nevertheless registered as a GPIO in the kernel. This enables the +user-space to trigger a BUG() in the pinctrl-msm driver by running, for +example: `gpiomon -c 0 113` on RB2. + +The exact culprit is requesting pins whose intr_detection_width setting +is not 1 or 2 for interrupts. This hits a BUG() in +msm_gpio_irq_set_type(). Potentially crashing the kernel due to an +invalid request from user-space is not optimal, so let's go through the +pins and mark those that would fail the check as invalid for the irq chip +as we should not even register them as available irqs. + +This function can be extended if we determine that there are more +corner-cases like this. + +Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver") +Cc: stable@vger.kernel.org +Reviewed-by: Bjorn Andersson +Signed-off-by: Bartosz Golaszewski +Link: https://lore.kernel.org/20250612091448.41546-1-brgl@bgdev.pl +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/qcom/pinctrl-msm.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/drivers/pinctrl/qcom/pinctrl-msm.c ++++ b/drivers/pinctrl/qcom/pinctrl-msm.c +@@ -949,6 +949,25 @@ static bool msm_gpio_needs_dual_edge_par + test_bit(d->hwirq, pctrl->skip_wake_irqs); + } + ++static void msm_gpio_irq_init_valid_mask(struct gpio_chip *gc, ++ unsigned long *valid_mask, ++ unsigned int ngpios) ++{ ++ struct msm_pinctrl *pctrl = gpiochip_get_data(gc); ++ const struct msm_pingroup *g; ++ int i; ++ ++ bitmap_fill(valid_mask, ngpios); ++ ++ for (i = 0; i < ngpios; i++) { ++ g = &pctrl->soc->groups[i]; ++ ++ if (g->intr_detection_width != 1 && ++ g->intr_detection_width != 2) ++ clear_bit(i, valid_mask); ++ } ++} ++ + static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); +@@ -1305,6 +1324,7 @@ static int msm_gpio_init(struct msm_pinc + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + girq->parents[0] = pctrl->irq; ++ girq->init_valid_mask = msm_gpio_irq_init_valid_mask; + + ret = gpiochip_add_data(&pctrl->chip, pctrl); + if (ret) { diff --git a/queue-5.15/series b/queue-5.15/series index 6f35c1de7f..f03b110a89 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -24,3 +24,8 @@ aoe-avoid-potential-deadlock-at-set_capacity.patch bpf-sockmap-fix-skb-refcnt-race-after-locking-changes.patch jfs-fix-null-ptr-deref-in-dtinsertentry.patch xen-replace-xen_remap-with-memremap.patch +x86-mce-amd-fix-threshold-limit-reset.patch +x86-mce-don-t-remove-sysfs-if-thresholding-sysfs-init-fails.patch +x86-mce-make-sure-cmci-banks-are-cleared-during-shutdown-on-intel.patch +gre-fix-ipv6-multicast-route-creation.patch +pinctrl-qcom-msm-mark-certain-pins-as-invalid-for-interrupts.patch diff --git a/queue-5.15/x86-mce-amd-fix-threshold-limit-reset.patch b/queue-5.15/x86-mce-amd-fix-threshold-limit-reset.patch new file mode 100644 index 0000000000..af83f5058c --- /dev/null +++ b/queue-5.15/x86-mce-amd-fix-threshold-limit-reset.patch @@ -0,0 +1,59 @@ +From 5f6e3b720694ad771911f637a51930f511427ce1 Mon Sep 17 00:00:00 2001 +From: Yazen Ghannam +Date: Tue, 24 Jun 2025 14:15:59 +0000 +Subject: x86/mce/amd: Fix threshold limit reset + +From: Yazen Ghannam + +commit 5f6e3b720694ad771911f637a51930f511427ce1 upstream. + +The MCA threshold limit must be reset after servicing the interrupt. + +Currently, the restart function doesn't have an explicit check for this. It +makes some assumptions based on the current limit and what's in the registers. +These assumptions don't always hold, so the limit won't be reset in some +cases. + +Make the reset condition explicit. Either an interrupt/overflow has occurred +or the bank is being initialized. + +Signed-off-by: Yazen Ghannam +Signed-off-by: Borislav Petkov (AMD) +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/20250624-wip-mca-updates-v4-4-236dd74f645f@amd.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/mce/amd.c | 15 +++++++-------- + 1 file changed, 7 insertions(+), 8 deletions(-) + +--- a/arch/x86/kernel/cpu/mce/amd.c ++++ b/arch/x86/kernel/cpu/mce/amd.c +@@ -310,7 +310,6 @@ static void smca_configure(unsigned int + + struct thresh_restart { + struct threshold_block *b; +- int reset; + int set_lvt_off; + int lvt_off; + u16 old_limit; +@@ -405,13 +404,13 @@ static void threshold_restart_bank(void + + rdmsr(tr->b->address, lo, hi); + +- if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) +- tr->reset = 1; /* limit cannot be lower than err count */ +- +- if (tr->reset) { /* reset err count and overflow bit */ +- hi = +- (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | +- (THRESHOLD_MAX - tr->b->threshold_limit); ++ /* ++ * Reset error count and overflow bit. ++ * This is done during init or after handling an interrupt. ++ */ ++ if (hi & MASK_OVERFLOW_HI || tr->set_lvt_off) { ++ hi &= ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI); ++ hi |= THRESHOLD_MAX - tr->b->threshold_limit; + } else if (tr->old_limit) { /* change limit w/o reset */ + int new_count = (hi & THRESHOLD_MAX) + + (tr->old_limit - tr->b->threshold_limit); diff --git a/queue-5.15/x86-mce-don-t-remove-sysfs-if-thresholding-sysfs-init-fails.patch b/queue-5.15/x86-mce-don-t-remove-sysfs-if-thresholding-sysfs-init-fails.patch new file mode 100644 index 0000000000..693dc8cd1e --- /dev/null +++ b/queue-5.15/x86-mce-don-t-remove-sysfs-if-thresholding-sysfs-init-fails.patch @@ -0,0 +1,52 @@ +From 4c113a5b28bfd589e2010b5fc8867578b0135ed7 Mon Sep 17 00:00:00 2001 +From: Yazen Ghannam +Date: Tue, 24 Jun 2025 14:15:56 +0000 +Subject: x86/mce: Don't remove sysfs if thresholding sysfs init fails + +From: Yazen Ghannam + +commit 4c113a5b28bfd589e2010b5fc8867578b0135ed7 upstream. + +Currently, the MCE subsystem sysfs interface will be removed if the +thresholding sysfs interface fails to be created. A common failure is due to +new MCA bank types that are not recognized and don't have a short name set. + +The MCA thresholding feature is optional and should not break the common MCE +sysfs interface. Also, new MCA bank types are occasionally introduced, and +updates will be needed to recognize them. But likewise, this should not break +the common sysfs interface. + +Keep the MCE sysfs interface regardless of the status of the thresholding +sysfs interface. + +Signed-off-by: Yazen Ghannam +Signed-off-by: Borislav Petkov (AMD) +Reviewed-by: Qiuxu Zhuo +Reviewed-by: Tony Luck +Tested-by: Tony Luck +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/20250624-wip-mca-updates-v4-1-236dd74f645f@amd.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/mce/core.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +--- a/arch/x86/kernel/cpu/mce/core.c ++++ b/arch/x86/kernel/cpu/mce/core.c +@@ -2620,15 +2620,9 @@ static int mce_cpu_dead(unsigned int cpu + static int mce_cpu_online(unsigned int cpu) + { + struct timer_list *t = this_cpu_ptr(&mce_timer); +- int ret; + + mce_device_create(cpu); +- +- ret = mce_threshold_create_device(cpu); +- if (ret) { +- mce_device_remove(cpu); +- return ret; +- } ++ mce_threshold_create_device(cpu); + mce_reenable_cpu(); + mce_start_timer(t); + return 0; diff --git a/queue-5.15/x86-mce-make-sure-cmci-banks-are-cleared-during-shutdown-on-intel.patch b/queue-5.15/x86-mce-make-sure-cmci-banks-are-cleared-during-shutdown-on-intel.patch new file mode 100644 index 0000000000..6c051298c9 --- /dev/null +++ b/queue-5.15/x86-mce-make-sure-cmci-banks-are-cleared-during-shutdown-on-intel.patch @@ -0,0 +1,40 @@ +From 30ad231a5029bfa16e46ce868497b1a5cdd3c24d Mon Sep 17 00:00:00 2001 +From: JP Kobryn +Date: Fri, 27 Jun 2025 10:49:35 -0700 +Subject: x86/mce: Make sure CMCI banks are cleared during shutdown on Intel + +From: JP Kobryn + +commit 30ad231a5029bfa16e46ce868497b1a5cdd3c24d upstream. + +CMCI banks are not cleared during shutdown on Intel CPUs. As a side effect, +when a kexec is performed, CPUs coming back online are unable to +rediscover/claim these occupied banks which breaks MCE reporting. + +Clear the CPU ownership during shutdown via cmci_clear() so the banks can +be reclaimed and MCE reporting will become functional once more. + + [ bp: Massage commit message. ] + +Reported-by: Aijay Adams +Signed-off-by: JP Kobryn +Signed-off-by: Borislav Petkov (AMD) +Reviewed-by: Tony Luck +Reviewed-by: Qiuxu Zhuo +Cc: +Link: https://lore.kernel.org/20250627174935.95194-1-inwardvessel@gmail.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/mce/intel.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/x86/kernel/cpu/mce/intel.c ++++ b/arch/x86/kernel/cpu/mce/intel.c +@@ -542,6 +542,7 @@ void mce_intel_feature_init(struct cpuin + void mce_intel_feature_clear(struct cpuinfo_x86 *c) + { + intel_clear_lmce(); ++ cmci_clear(); + } + + bool intel_filter_mce(struct mce *m) -- 2.47.2