From 04b134837967ef392be361add19c60a1e9cad11d Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Thu, 28 May 2020 13:59:49 +0200 Subject: [PATCH] i386: Fix V2SF horizontal addsub insn MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit PFPNACC insn is incorrectly modelled to perform addition and subtraction of two operands, but in reality it performs horizontal addition and subtraction: Instruction: PFPNACC dest,src Description: dest[31:0] <- dest[31:0] - dest[63:32]; dest[63:32] <- src[31:0] + src[63:32]; 2020-05-28 Uroš Bizjak gcc/ChangeLog: * config/i386/mmx.md (mmx_haddsubv2sf3): Correct RTL template to model horizontal subtraction and addition. --- gcc/config/i386/mmx.md | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 472f90f9bc13..6ea80b868079 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -436,12 +436,17 @@ (define_insn "mmx_addsubv2sf3" [(set (match_operand:V2SF 0 "register_operand" "=y") - (vec_merge:V2SF - (plus:V2SF - (match_operand:V2SF 1 "register_operand" "0") - (match_operand:V2SF 2 "nonimmediate_operand" "ym")) - (minus:V2SF (match_dup 1) (match_dup 2)) - (const_int 1)))] + (vec_concat:V2SF + (minus:SF + (vec_select:SF + (match_operand:V2SF 1 "register_operand" "0") + (parallel [(const_int 0)])) + (vec_select:SF (match_dup 1) (parallel [(const_int 1)]))) + (plus:SF + (vec_select:SF + (match_operand:V2SF 2 "nonimmediate_operand" "ym") + (parallel [(const_int 0)])) + (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))] "TARGET_3DNOW_A" "pfpnacc\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") -- 2.47.2