From 073f06cac87c6f4c0b23e8a283af3fccab8fb53e Mon Sep 17 00:00:00 2001 From: Julian Seward Date: Fri, 15 Aug 2014 09:11:08 +0000 Subject: [PATCH] Rename Iop_QSalN*, Iop_QShlN* and Iop_QShlN*S so as to more accurately reflect what they actually do, which is a zero-fill shift left followed by one of three flavours of saturation (S->S, U->U or S->U). git-svn-id: svn://svn.valgrind.org/vex/trunk@2924 --- VEX/priv/guest_arm64_toIR.c | 21 +++--- VEX/priv/guest_arm_toIR.c | 24 +++---- VEX/priv/host_arm64_isel.c | 140 ++++++++++++++++++------------------ VEX/priv/host_arm_isel.c | 108 ++++++++++++++-------------- VEX/priv/ir_defs.c | 72 +++++++++---------- VEX/pub/libvex_ir.h | 18 +++-- 6 files changed, 196 insertions(+), 187 deletions(-) diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c index 997565cfb5..9e27d903f4 100644 --- a/VEX/priv/guest_arm64_toIR.c +++ b/VEX/priv/guest_arm64_toIR.c @@ -921,23 +921,26 @@ static IROp mkVecQANDqrsarNNARROWSU ( UInt sizeNarrow ) { return ops[sizeNarrow]; } -static IROp mkVecQSHLNSATU2U ( UInt size ) { +static IROp mkVecQSHLNSATUU ( UInt size ) { const IROp ops[4] - = { Iop_QShlN8x16, Iop_QShlN16x8, Iop_QShlN32x4, Iop_QShlN64x2 }; + = { Iop_QShlNsatUU8x16, Iop_QShlNsatUU16x8, + Iop_QShlNsatUU32x4, Iop_QShlNsatUU64x2 }; vassert(size < 4); return ops[size]; } -static IROp mkVecQSHLNSATS2S ( UInt size ) { +static IROp mkVecQSHLNSATSS ( UInt size ) { const IROp ops[4] - = { Iop_QSalN8x16, Iop_QSalN16x8, Iop_QSalN32x4, Iop_QSalN64x2 }; + = { Iop_QShlNsatSS8x16, Iop_QShlNsatSS16x8, + Iop_QShlNsatSS32x4, Iop_QShlNsatSS64x2 }; vassert(size < 4); return ops[size]; } -static IROp mkVecQSHLNSATS2U ( UInt size ) { +static IROp mkVecQSHLNSATSU ( UInt size ) { const IROp ops[4] - = { Iop_QShlN8Sx16, Iop_QShlN16Sx8, Iop_QShlN32Sx4, Iop_QShlN64Sx2 }; + = { Iop_QShlNsatSU8x16, Iop_QShlNsatSU16x8, + Iop_QShlNsatSU32x4, Iop_QShlNsatSU64x2 }; vassert(size < 4); return ops[size]; } @@ -6609,7 +6612,7 @@ void math_QSHL_IMM ( /*OUT*/IRTemp* res, /* UQSHL */ if (vex_streq(nm, "uqshl")) { - IROp qop = mkVecQSHLNSATU2U(size); + IROp qop = mkVecQSHLNSATUU(size); assign(*res, binop(qop, mkexpr(src), mkU8(shift))); if (shift == 0) { /* No shift means no saturation. */ @@ -6629,7 +6632,7 @@ void math_QSHL_IMM ( /*OUT*/IRTemp* res, /* SQSHL */ if (vex_streq(nm, "sqshl")) { - IROp qop = mkVecQSHLNSATS2S(size); + IROp qop = mkVecQSHLNSATSS(size); assign(*res, binop(qop, mkexpr(src), mkU8(shift))); if (shift == 0) { /* No shift means no saturation. */ @@ -6657,7 +6660,7 @@ void math_QSHL_IMM ( /*OUT*/IRTemp* res, /* SQSHLU */ if (vex_streq(nm, "sqshlu")) { - IROp qop = mkVecQSHLNSATS2U(size); + IROp qop = mkVecQSHLNSATSU(size); assign(*res, binop(qop, mkexpr(src), mkU8(shift))); if (shift == 0) { /* If there's no shift, saturation depends on the top bit diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index 64e5d6e386..2070254e68 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -6257,19 +6257,19 @@ Bool dis_neon_data_2reg_and_shift ( UInt theInstr, IRTemp condT ) if (A & 1) { switch (size) { case 0: - op = Q ? Iop_QShlN8x16 : Iop_QShlN8x8; + op = Q ? Iop_QShlNsatUU8x16 : Iop_QShlNsatUU8x8; op_rev = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; break; case 1: - op = Q ? Iop_QShlN16x8 : Iop_QShlN16x4; + op = Q ? Iop_QShlNsatUU16x8 : Iop_QShlNsatUU16x4; op_rev = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; break; case 2: - op = Q ? Iop_QShlN32x4 : Iop_QShlN32x2; + op = Q ? Iop_QShlNsatUU32x4 : Iop_QShlNsatUU32x2; op_rev = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; break; case 3: - op = Q ? Iop_QShlN64x2 : Iop_QShlN64x1; + op = Q ? Iop_QShlNsatUU64x2 : Iop_QShlNsatUU64x1; op_rev = Q ? Iop_ShrN64x2 : Iop_Shr64; break; default: @@ -6281,19 +6281,19 @@ Bool dis_neon_data_2reg_and_shift ( UInt theInstr, IRTemp condT ) } else { switch (size) { case 0: - op = Q ? Iop_QShlN8Sx16 : Iop_QShlN8Sx8; + op = Q ? Iop_QShlNsatSU8x16 : Iop_QShlNsatSU8x8; op_rev = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; break; case 1: - op = Q ? Iop_QShlN16Sx8 : Iop_QShlN16Sx4; + op = Q ? Iop_QShlNsatSU16x8 : Iop_QShlNsatSU16x4; op_rev = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; break; case 2: - op = Q ? Iop_QShlN32Sx4 : Iop_QShlN32Sx2; + op = Q ? Iop_QShlNsatSU32x4 : Iop_QShlNsatSU32x2; op_rev = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; break; case 3: - op = Q ? Iop_QShlN64Sx2 : Iop_QShlN64Sx1; + op = Q ? Iop_QShlNsatSU64x2 : Iop_QShlNsatSU64x1; op_rev = Q ? Iop_ShrN64x2 : Iop_Shr64; break; default: @@ -6308,19 +6308,19 @@ Bool dis_neon_data_2reg_and_shift ( UInt theInstr, IRTemp condT ) return False; switch (size) { case 0: - op = Q ? Iop_QSalN8x16 : Iop_QSalN8x8; + op = Q ? Iop_QShlNsatSS8x16 : Iop_QShlNsatSS8x8; op_rev = Q ? Iop_SarN8x16 : Iop_SarN8x8; break; case 1: - op = Q ? Iop_QSalN16x8 : Iop_QSalN16x4; + op = Q ? Iop_QShlNsatSS16x8 : Iop_QShlNsatSS16x4; op_rev = Q ? Iop_SarN16x8 : Iop_SarN16x4; break; case 2: - op = Q ? Iop_QSalN32x4 : Iop_QSalN32x2; + op = Q ? Iop_QShlNsatSS32x4 : Iop_QShlNsatSS32x2; op_rev = Q ? Iop_SarN32x4 : Iop_SarN32x2; break; case 3: - op = Q ? Iop_QSalN64x2 : Iop_QSalN64x1; + op = Q ? Iop_QShlNsatSS64x2 : Iop_QShlNsatSS64x1; op_rev = Q ? Iop_SarN64x2 : Iop_Sar64; break; default: diff --git a/VEX/priv/host_arm64_isel.c b/VEX/priv/host_arm64_isel.c index 71ee7a64cf..3915ae16a0 100644 --- a/VEX/priv/host_arm64_isel.c +++ b/VEX/priv/host_arm64_isel.c @@ -3316,10 +3316,10 @@ static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo, //ZZ res, argL, size, False)); //ZZ return res; //ZZ } -//ZZ case Iop_QSalN8x8: -//ZZ case Iop_QSalN16x4: -//ZZ case Iop_QSalN32x2: -//ZZ case Iop_QSalN64x1: { +//ZZ case Iop_QShlNsatSS8x8: +//ZZ case Iop_QShlNsatSS16x4: +//ZZ case Iop_QShlNsatSS32x2: +//ZZ case Iop_QShlNsatSS64x1: { //ZZ HReg res = newVRegD(env); //ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); //ZZ UInt size, imm; @@ -3330,10 +3330,10 @@ static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo, //ZZ } //ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; //ZZ switch (e->Iex.Binop.op) { -//ZZ case Iop_QSalN8x8: size = 8 | imm; break; -//ZZ case Iop_QSalN16x4: size = 16 | imm; break; -//ZZ case Iop_QSalN32x2: size = 32 | imm; break; -//ZZ case Iop_QSalN64x1: size = 64 | imm; break; +//ZZ case Iop_QShlNsatSS8x8: size = 8 | imm; break; +//ZZ case Iop_QShlNsatSS16x4: size = 16 | imm; break; +//ZZ case Iop_QShlNsatSS32x2: size = 32 | imm; break; +//ZZ case Iop_QShlNsatSS64x1: size = 64 | imm; break; //ZZ default: vassert(0); //ZZ } //ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS, @@ -5580,10 +5580,10 @@ static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e ) //ZZ res, argL, size, True)); //ZZ return res; //ZZ } -//ZZ case Iop_QSalN8x16: -//ZZ case Iop_QSalN16x8: -//ZZ case Iop_QSalN32x4: -//ZZ case Iop_QSalN64x2: { +//ZZ case Iop_QShlNsatSS8x16: +//ZZ case Iop_QShlNsatSS16x8: +//ZZ case Iop_QShlNsatSS32x4: +//ZZ case Iop_QShlNsatSS64x2: { //ZZ HReg res = newVRegV(env); //ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); //ZZ UInt size, imm; @@ -5594,10 +5594,10 @@ static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e ) //ZZ } //ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; //ZZ switch (e->Iex.Binop.op) { -//ZZ case Iop_QSalN8x16: size = 8 | imm; break; -//ZZ case Iop_QSalN16x8: size = 16 | imm; break; -//ZZ case Iop_QSalN32x4: size = 32 | imm; break; -//ZZ case Iop_QSalN64x2: size = 64 | imm; break; +//ZZ case Iop_QShlNsatSS8x16: size = 8 | imm; break; +//ZZ case Iop_QShlNsatSS16x8: size = 16 | imm; break; +//ZZ case Iop_QShlNsatSS32x4: size = 32 | imm; break; +//ZZ case Iop_QShlNsatSS64x2: size = 64 | imm; break; //ZZ default: vassert(0); //ZZ } //ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS, @@ -5610,12 +5610,12 @@ static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e ) case Iop_SarN16x8: case Iop_SarN8x16: case Iop_ShlN64x2: case Iop_ShlN32x4: case Iop_ShlN16x8: case Iop_ShlN8x16: - case Iop_QShlN64x2: case Iop_QShlN32x4: - case Iop_QShlN16x8: case Iop_QShlN8x16: - case Iop_QSalN64x2: case Iop_QSalN32x4: - case Iop_QSalN16x8: case Iop_QSalN8x16: - case Iop_QShlN64Sx2: case Iop_QShlN32Sx4: - case Iop_QShlN16Sx8: case Iop_QShlN8Sx16: + case Iop_QShlNsatUU64x2: case Iop_QShlNsatUU32x4: + case Iop_QShlNsatUU16x8: case Iop_QShlNsatUU8x16: + case Iop_QShlNsatSS64x2: case Iop_QShlNsatSS32x4: + case Iop_QShlNsatSS16x8: case Iop_QShlNsatSS8x16: + case Iop_QShlNsatSU64x2: case Iop_QShlNsatSU32x4: + case Iop_QShlNsatSU16x8: case Iop_QShlNsatSU8x16: { IRExpr* argL = e->Iex.Binop.arg1; IRExpr* argR = e->Iex.Binop.arg2; @@ -5626,58 +5626,58 @@ static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e ) ARM64VecShiftOp op = ARM64vecsh_INVALID; /* Establish the instruction to use. */ switch (e->Iex.Binop.op) { - case Iop_ShrN64x2: op = ARM64vecsh_USHR64x2; break; - case Iop_ShrN32x4: op = ARM64vecsh_USHR32x4; break; - case Iop_ShrN16x8: op = ARM64vecsh_USHR16x8; break; - case Iop_ShrN8x16: op = ARM64vecsh_USHR8x16; break; - case Iop_SarN64x2: op = ARM64vecsh_SSHR64x2; break; - case Iop_SarN32x4: op = ARM64vecsh_SSHR32x4; break; - case Iop_SarN16x8: op = ARM64vecsh_SSHR16x8; break; - case Iop_SarN8x16: op = ARM64vecsh_SSHR8x16; break; - case Iop_ShlN64x2: op = ARM64vecsh_SHL64x2; break; - case Iop_ShlN32x4: op = ARM64vecsh_SHL32x4; break; - case Iop_ShlN16x8: op = ARM64vecsh_SHL16x8; break; - case Iop_ShlN8x16: op = ARM64vecsh_SHL8x16; break; - case Iop_QShlN64x2: op = ARM64vecsh_UQSHL64x2; break; - case Iop_QShlN32x4: op = ARM64vecsh_UQSHL32x4; break; - case Iop_QShlN16x8: op = ARM64vecsh_UQSHL16x8; break; - case Iop_QShlN8x16: op = ARM64vecsh_UQSHL8x16; break; - case Iop_QSalN64x2: op = ARM64vecsh_SQSHL64x2; break; - case Iop_QSalN32x4: op = ARM64vecsh_SQSHL32x4; break; - case Iop_QSalN16x8: op = ARM64vecsh_SQSHL16x8; break; - case Iop_QSalN8x16: op = ARM64vecsh_SQSHL8x16; break; - case Iop_QShlN64Sx2: op = ARM64vecsh_SQSHLU64x2; break; - case Iop_QShlN32Sx4: op = ARM64vecsh_SQSHLU32x4; break; - case Iop_QShlN16Sx8: op = ARM64vecsh_SQSHLU16x8; break; - case Iop_QShlN8Sx16: op = ARM64vecsh_SQSHLU8x16; break; + case Iop_ShrN64x2: op = ARM64vecsh_USHR64x2; break; + case Iop_ShrN32x4: op = ARM64vecsh_USHR32x4; break; + case Iop_ShrN16x8: op = ARM64vecsh_USHR16x8; break; + case Iop_ShrN8x16: op = ARM64vecsh_USHR8x16; break; + case Iop_SarN64x2: op = ARM64vecsh_SSHR64x2; break; + case Iop_SarN32x4: op = ARM64vecsh_SSHR32x4; break; + case Iop_SarN16x8: op = ARM64vecsh_SSHR16x8; break; + case Iop_SarN8x16: op = ARM64vecsh_SSHR8x16; break; + case Iop_ShlN64x2: op = ARM64vecsh_SHL64x2; break; + case Iop_ShlN32x4: op = ARM64vecsh_SHL32x4; break; + case Iop_ShlN16x8: op = ARM64vecsh_SHL16x8; break; + case Iop_ShlN8x16: op = ARM64vecsh_SHL8x16; break; + case Iop_QShlNsatUU64x2: op = ARM64vecsh_UQSHL64x2; break; + case Iop_QShlNsatUU32x4: op = ARM64vecsh_UQSHL32x4; break; + case Iop_QShlNsatUU16x8: op = ARM64vecsh_UQSHL16x8; break; + case Iop_QShlNsatUU8x16: op = ARM64vecsh_UQSHL8x16; break; + case Iop_QShlNsatSS64x2: op = ARM64vecsh_SQSHL64x2; break; + case Iop_QShlNsatSS32x4: op = ARM64vecsh_SQSHL32x4; break; + case Iop_QShlNsatSS16x8: op = ARM64vecsh_SQSHL16x8; break; + case Iop_QShlNsatSS8x16: op = ARM64vecsh_SQSHL8x16; break; + case Iop_QShlNsatSU64x2: op = ARM64vecsh_SQSHLU64x2; break; + case Iop_QShlNsatSU32x4: op = ARM64vecsh_SQSHLU32x4; break; + case Iop_QShlNsatSU16x8: op = ARM64vecsh_SQSHLU16x8; break; + case Iop_QShlNsatSU8x16: op = ARM64vecsh_SQSHLU8x16; break; default: vassert(0); } /* Establish the shift limits, for sanity check purposes only. */ switch (e->Iex.Binop.op) { - case Iop_ShrN64x2: limLo = 1; limHi = 64; break; - case Iop_ShrN32x4: limLo = 1; limHi = 32; break; - case Iop_ShrN16x8: limLo = 1; limHi = 16; break; - case Iop_ShrN8x16: limLo = 1; limHi = 8; break; - case Iop_SarN64x2: limLo = 1; limHi = 64; break; - case Iop_SarN32x4: limLo = 1; limHi = 32; break; - case Iop_SarN16x8: limLo = 1; limHi = 16; break; - case Iop_SarN8x16: limLo = 1; limHi = 8; break; - case Iop_ShlN64x2: limLo = 0; limHi = 63; break; - case Iop_ShlN32x4: limLo = 0; limHi = 31; break; - case Iop_ShlN16x8: limLo = 0; limHi = 15; break; - case Iop_ShlN8x16: limLo = 0; limHi = 7; break; - case Iop_QShlN64x2: limLo = 0; limHi = 63; break; - case Iop_QShlN32x4: limLo = 0; limHi = 31; break; - case Iop_QShlN16x8: limLo = 0; limHi = 15; break; - case Iop_QShlN8x16: limLo = 0; limHi = 7; break; - case Iop_QSalN64x2: limLo = 0; limHi = 63; break; - case Iop_QSalN32x4: limLo = 0; limHi = 31; break; - case Iop_QSalN16x8: limLo = 0; limHi = 15; break; - case Iop_QSalN8x16: limLo = 0; limHi = 7; break; - case Iop_QShlN64Sx2: limLo = 0; limHi = 63; break; - case Iop_QShlN32Sx4: limLo = 0; limHi = 31; break; - case Iop_QShlN16Sx8: limLo = 0; limHi = 15; break; - case Iop_QShlN8Sx16: limLo = 0; limHi = 7; break; + case Iop_ShrN64x2: limLo = 1; limHi = 64; break; + case Iop_ShrN32x4: limLo = 1; limHi = 32; break; + case Iop_ShrN16x8: limLo = 1; limHi = 16; break; + case Iop_ShrN8x16: limLo = 1; limHi = 8; break; + case Iop_SarN64x2: limLo = 1; limHi = 64; break; + case Iop_SarN32x4: limLo = 1; limHi = 32; break; + case Iop_SarN16x8: limLo = 1; limHi = 16; break; + case Iop_SarN8x16: limLo = 1; limHi = 8; break; + case Iop_ShlN64x2: limLo = 0; limHi = 63; break; + case Iop_ShlN32x4: limLo = 0; limHi = 31; break; + case Iop_ShlN16x8: limLo = 0; limHi = 15; break; + case Iop_ShlN8x16: limLo = 0; limHi = 7; break; + case Iop_QShlNsatUU64x2: limLo = 0; limHi = 63; break; + case Iop_QShlNsatUU32x4: limLo = 0; limHi = 31; break; + case Iop_QShlNsatUU16x8: limLo = 0; limHi = 15; break; + case Iop_QShlNsatUU8x16: limLo = 0; limHi = 7; break; + case Iop_QShlNsatSS64x2: limLo = 0; limHi = 63; break; + case Iop_QShlNsatSS32x4: limLo = 0; limHi = 31; break; + case Iop_QShlNsatSS16x8: limLo = 0; limHi = 15; break; + case Iop_QShlNsatSS8x16: limLo = 0; limHi = 7; break; + case Iop_QShlNsatSU64x2: limLo = 0; limHi = 63; break; + case Iop_QShlNsatSU32x4: limLo = 0; limHi = 31; break; + case Iop_QShlNsatSU16x8: limLo = 0; limHi = 15; break; + case Iop_QShlNsatSU8x16: limLo = 0; limHi = 7; break; default: vassert(0); } /* For left shifts, the allowable amt values are diff --git a/VEX/priv/host_arm_isel.c b/VEX/priv/host_arm_isel.c index 8235282aaf..6b18689633 100644 --- a/VEX/priv/host_arm_isel.c +++ b/VEX/priv/host_arm_isel.c @@ -2672,72 +2672,72 @@ static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e ) res, argL, argR, size, False)); return res; } - case Iop_QShlN8x8: - case Iop_QShlN16x4: - case Iop_QShlN32x2: - case Iop_QShlN64x1: { + case Iop_QShlNsatUU8x8: + case Iop_QShlNsatUU16x4: + case Iop_QShlNsatUU32x2: + case Iop_QShlNsatUU64x1: { HReg res = newVRegD(env); HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); UInt size, imm; if (e->Iex.Binop.arg2->tag != Iex_Const || typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { - vpanic("ARM taget supports Iop_QShlNAxB with constant " + vpanic("ARM target supports Iop_QShlNsatUUAxB with constant " "second argument only\n"); } imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; switch (e->Iex.Binop.op) { - case Iop_QShlN8x8: size = 8 | imm; break; - case Iop_QShlN16x4: size = 16 | imm; break; - case Iop_QShlN32x2: size = 32 | imm; break; - case Iop_QShlN64x1: size = 64 | imm; break; + case Iop_QShlNsatUU8x8: size = 8 | imm; break; + case Iop_QShlNsatUU16x4: size = 16 | imm; break; + case Iop_QShlNsatUU32x2: size = 32 | imm; break; + case Iop_QShlNsatUU64x1: size = 64 | imm; break; default: vassert(0); } addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU, res, argL, size, False)); return res; } - case Iop_QShlN8Sx8: - case Iop_QShlN16Sx4: - case Iop_QShlN32Sx2: - case Iop_QShlN64Sx1: { + case Iop_QShlNsatSU8x8: + case Iop_QShlNsatSU16x4: + case Iop_QShlNsatSU32x2: + case Iop_QShlNsatSU64x1: { HReg res = newVRegD(env); HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); UInt size, imm; if (e->Iex.Binop.arg2->tag != Iex_Const || typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { - vpanic("ARM taget supports Iop_QShlNAxB with constant " + vpanic("ARM target supports Iop_QShlNsatSUAxB with constant " "second argument only\n"); } imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; switch (e->Iex.Binop.op) { - case Iop_QShlN8Sx8: size = 8 | imm; break; - case Iop_QShlN16Sx4: size = 16 | imm; break; - case Iop_QShlN32Sx2: size = 32 | imm; break; - case Iop_QShlN64Sx1: size = 64 | imm; break; + case Iop_QShlNsatSU8x8: size = 8 | imm; break; + case Iop_QShlNsatSU16x4: size = 16 | imm; break; + case Iop_QShlNsatSU32x2: size = 32 | imm; break; + case Iop_QShlNsatSU64x1: size = 64 | imm; break; default: vassert(0); } addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS, res, argL, size, False)); return res; } - case Iop_QSalN8x8: - case Iop_QSalN16x4: - case Iop_QSalN32x2: - case Iop_QSalN64x1: { + case Iop_QShlNsatSS8x8: + case Iop_QShlNsatSS16x4: + case Iop_QShlNsatSS32x2: + case Iop_QShlNsatSS64x1: { HReg res = newVRegD(env); HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); UInt size, imm; if (e->Iex.Binop.arg2->tag != Iex_Const || typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { - vpanic("ARM taget supports Iop_QShlNAxB with constant " + vpanic("ARM target supports Iop_QShlNsatSSAxB with constant " "second argument only\n"); } imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; switch (e->Iex.Binop.op) { - case Iop_QSalN8x8: size = 8 | imm; break; - case Iop_QSalN16x4: size = 16 | imm; break; - case Iop_QSalN32x2: size = 32 | imm; break; - case Iop_QSalN64x1: size = 64 | imm; break; + case Iop_QShlNsatSS8x8: size = 8 | imm; break; + case Iop_QShlNsatSS16x4: size = 16 | imm; break; + case Iop_QShlNsatSS32x2: size = 32 | imm; break; + case Iop_QShlNsatSS64x1: size = 64 | imm; break; default: vassert(0); } addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS, @@ -4842,72 +4842,72 @@ static HReg iselNeonExpr_wrk ( ISelEnv* env, IRExpr* e ) res, argL, argR, size, True)); return res; } - case Iop_QShlN8x16: - case Iop_QShlN16x8: - case Iop_QShlN32x4: - case Iop_QShlN64x2: { + case Iop_QShlNsatUU8x16: + case Iop_QShlNsatUU16x8: + case Iop_QShlNsatUU32x4: + case Iop_QShlNsatUU64x2: { HReg res = newVRegV(env); HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); UInt size, imm; if (e->Iex.Binop.arg2->tag != Iex_Const || typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { - vpanic("ARM taget supports Iop_QShlNAxB with constant " + vpanic("ARM target supports Iop_QShlNsatUUAxB with constant " "second argument only\n"); } imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; switch (e->Iex.Binop.op) { - case Iop_QShlN8x16: size = 8 | imm; break; - case Iop_QShlN16x8: size = 16 | imm; break; - case Iop_QShlN32x4: size = 32 | imm; break; - case Iop_QShlN64x2: size = 64 | imm; break; + case Iop_QShlNsatUU8x16: size = 8 | imm; break; + case Iop_QShlNsatUU16x8: size = 16 | imm; break; + case Iop_QShlNsatUU32x4: size = 32 | imm; break; + case Iop_QShlNsatUU64x2: size = 64 | imm; break; default: vassert(0); } addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU, res, argL, size, True)); return res; } - case Iop_QShlN8Sx16: - case Iop_QShlN16Sx8: - case Iop_QShlN32Sx4: - case Iop_QShlN64Sx2: { + case Iop_QShlNsatSU8x16: + case Iop_QShlNsatSU16x8: + case Iop_QShlNsatSU32x4: + case Iop_QShlNsatSU64x2: { HReg res = newVRegV(env); HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); UInt size, imm; if (e->Iex.Binop.arg2->tag != Iex_Const || typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { - vpanic("ARM taget supports Iop_QShlNASxB with constant " + vpanic("ARM target supports Iop_QShlNsatSUAxB with constant " "second argument only\n"); } imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; switch (e->Iex.Binop.op) { - case Iop_QShlN8Sx16: size = 8 | imm; break; - case Iop_QShlN16Sx8: size = 16 | imm; break; - case Iop_QShlN32Sx4: size = 32 | imm; break; - case Iop_QShlN64Sx2: size = 64 | imm; break; + case Iop_QShlNsatSU8x16: size = 8 | imm; break; + case Iop_QShlNsatSU16x8: size = 16 | imm; break; + case Iop_QShlNsatSU32x4: size = 32 | imm; break; + case Iop_QShlNsatSU64x2: size = 64 | imm; break; default: vassert(0); } addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS, res, argL, size, True)); return res; } - case Iop_QSalN8x16: - case Iop_QSalN16x8: - case Iop_QSalN32x4: - case Iop_QSalN64x2: { + case Iop_QShlNsatSS8x16: + case Iop_QShlNsatSS16x8: + case Iop_QShlNsatSS32x4: + case Iop_QShlNsatSS64x2: { HReg res = newVRegV(env); HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); UInt size, imm; if (e->Iex.Binop.arg2->tag != Iex_Const || typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { - vpanic("ARM taget supports Iop_QShlNAxB with constant " + vpanic("ARM target supports Iop_QShlNsatSSAxB with constant " "second argument only\n"); } imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; switch (e->Iex.Binop.op) { - case Iop_QSalN8x16: size = 8 | imm; break; - case Iop_QSalN16x8: size = 16 | imm; break; - case Iop_QSalN32x4: size = 32 | imm; break; - case Iop_QSalN64x2: size = 64 | imm; break; + case Iop_QShlNsatSS8x16: size = 8 | imm; break; + case Iop_QShlNsatSS16x8: size = 16 | imm; break; + case Iop_QShlNsatSS32x4: size = 32 | imm; break; + case Iop_QShlNsatSS64x2: size = 64 | imm; break; default: vassert(0); } addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS, diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c index ed23fd9415..50f161d2bf 100644 --- a/VEX/priv/ir_defs.c +++ b/VEX/priv/ir_defs.c @@ -559,18 +559,18 @@ void ppIROp ( IROp op ) case Iop_QSal16x4: vex_printf("QSal16x4"); return; case Iop_QSal32x2: vex_printf("QSal32x2"); return; case Iop_QSal64x1: vex_printf("QSal64x1"); return; - case Iop_QShlN8x8: vex_printf("QShlN8x8"); return; - case Iop_QShlN16x4: vex_printf("QShlN16x4"); return; - case Iop_QShlN32x2: vex_printf("QShlN32x2"); return; - case Iop_QShlN64x1: vex_printf("QShlN64x1"); return; - case Iop_QShlN8Sx8: vex_printf("QShlN8Sx8"); return; - case Iop_QShlN16Sx4: vex_printf("QShlN16Sx4"); return; - case Iop_QShlN32Sx2: vex_printf("QShlN32Sx2"); return; - case Iop_QShlN64Sx1: vex_printf("QShlN64Sx1"); return; - case Iop_QSalN8x8: vex_printf("QSalN8x8"); return; - case Iop_QSalN16x4: vex_printf("QSalN16x4"); return; - case Iop_QSalN32x2: vex_printf("QSalN32x2"); return; - case Iop_QSalN64x1: vex_printf("QSalN64x1"); return; + case Iop_QShlNsatUU8x8: vex_printf("QShlNsatUU8x8"); return; + case Iop_QShlNsatUU16x4: vex_printf("QShlNsatUU16x4"); return; + case Iop_QShlNsatUU32x2: vex_printf("QShlNsatUU32x2"); return; + case Iop_QShlNsatUU64x1: vex_printf("QShlNsatUU64x1"); return; + case Iop_QShlNsatSU8x8: vex_printf("QShlNsatSU8x8"); return; + case Iop_QShlNsatSU16x4: vex_printf("QShlNsatSU16x4"); return; + case Iop_QShlNsatSU32x2: vex_printf("QShlNsatSU32x2"); return; + case Iop_QShlNsatSU64x1: vex_printf("QShlNsatSU64x1"); return; + case Iop_QShlNsatSS8x8: vex_printf("QShlNsatSS8x8"); return; + case Iop_QShlNsatSS16x4: vex_printf("QShlNsatSS16x4"); return; + case Iop_QShlNsatSS32x2: vex_printf("QShlNsatSS32x2"); return; + case Iop_QShlNsatSS64x1: vex_printf("QShlNsatSS64x1"); return; case Iop_Sar8x8: vex_printf("Sar8x8"); return; case Iop_Sar16x4: vex_printf("Sar16x4"); return; case Iop_Sar32x2: vex_printf("Sar32x2"); return; @@ -874,18 +874,18 @@ void ppIROp ( IROp op ) case Iop_QShl16x8: vex_printf("QShl16x8"); return; case Iop_QShl32x4: vex_printf("QShl32x4"); return; case Iop_QShl64x2: vex_printf("QShl64x2"); return; - case Iop_QSalN8x16: vex_printf("QSalN8x16"); return; - case Iop_QSalN16x8: vex_printf("QSalN16x8"); return; - case Iop_QSalN32x4: vex_printf("QSalN32x4"); return; - case Iop_QSalN64x2: vex_printf("QSalN64x2"); return; - case Iop_QShlN8x16: vex_printf("QShlN8x16"); return; - case Iop_QShlN16x8: vex_printf("QShlN16x8"); return; - case Iop_QShlN32x4: vex_printf("QShlN32x4"); return; - case Iop_QShlN64x2: vex_printf("QShlN64x2"); return; - case Iop_QShlN8Sx16: vex_printf("QShlN8Sx16"); return; - case Iop_QShlN16Sx8: vex_printf("QShlN16Sx8"); return; - case Iop_QShlN32Sx4: vex_printf("QShlN32Sx4"); return; - case Iop_QShlN64Sx2: vex_printf("QShlN64Sx2"); return; + case Iop_QShlNsatSS8x16: vex_printf("QShlNsatSS8x16"); return; + case Iop_QShlNsatSS16x8: vex_printf("QShlNsatSS16x8"); return; + case Iop_QShlNsatSS32x4: vex_printf("QShlNsatSS32x4"); return; + case Iop_QShlNsatSS64x2: vex_printf("QShlNsatSS64x2"); return; + case Iop_QShlNsatUU8x16: vex_printf("QShlNsatUU8x16"); return; + case Iop_QShlNsatUU16x8: vex_printf("QShlNsatUU16x8"); return; + case Iop_QShlNsatUU32x4: vex_printf("QShlNsatUU32x4"); return; + case Iop_QShlNsatUU64x2: vex_printf("QShlNsatUU64x2"); return; + case Iop_QShlNsatSU8x16: vex_printf("QShlNsatSU8x16"); return; + case Iop_QShlNsatSU16x8: vex_printf("QShlNsatSU16x8"); return; + case Iop_QShlNsatSU32x4: vex_printf("QShlNsatSU32x4"); return; + case Iop_QShlNsatSU64x2: vex_printf("QShlNsatSU64x2"); return; case Iop_Shr8x16: vex_printf("Shr8x16"); return; case Iop_Shr16x8: vex_printf("Shr16x8"); return; case Iop_Shr32x4: vex_printf("Shr32x4"); return; @@ -2545,12 +2545,12 @@ void typeOfPrimop ( IROp op, case Iop_ShlN32x2: case Iop_ShlN16x4: case Iop_ShlN8x8: case Iop_ShrN32x2: case Iop_ShrN16x4: case Iop_ShrN8x8: case Iop_SarN32x2: case Iop_SarN16x4: case Iop_SarN8x8: - case Iop_QShlN8x8: case Iop_QShlN16x4: - case Iop_QShlN32x2: case Iop_QShlN64x1: - case Iop_QShlN8Sx8: case Iop_QShlN16Sx4: - case Iop_QShlN32Sx2: case Iop_QShlN64Sx1: - case Iop_QSalN8x8: case Iop_QSalN16x4: - case Iop_QSalN32x2: case Iop_QSalN64x1: + case Iop_QShlNsatUU8x8: case Iop_QShlNsatUU16x4: + case Iop_QShlNsatUU32x2: case Iop_QShlNsatUU64x1: + case Iop_QShlNsatSU8x8: case Iop_QShlNsatSU16x4: + case Iop_QShlNsatSU32x2: case Iop_QShlNsatSU64x1: + case Iop_QShlNsatSS8x8: case Iop_QShlNsatSS16x4: + case Iop_QShlNsatSS32x2: case Iop_QShlNsatSS64x1: BINARY(Ity_I64,Ity_I8, Ity_I64); case Iop_Shl8: case Iop_Shr8: case Iop_Sar8: @@ -2983,12 +2983,12 @@ void typeOfPrimop ( IROp op, case Iop_ShrN32x4: case Iop_ShrN64x2: case Iop_SarN8x16: case Iop_SarN16x8: case Iop_SarN32x4: case Iop_SarN64x2: - case Iop_QShlN8x16: case Iop_QShlN16x8: - case Iop_QShlN32x4: case Iop_QShlN64x2: - case Iop_QShlN8Sx16: case Iop_QShlN16Sx8: - case Iop_QShlN32Sx4: case Iop_QShlN64Sx2: - case Iop_QSalN8x16: case Iop_QSalN16x8: - case Iop_QSalN32x4: case Iop_QSalN64x2: + case Iop_QShlNsatUU8x16: case Iop_QShlNsatUU16x8: + case Iop_QShlNsatUU32x4: case Iop_QShlNsatUU64x2: + case Iop_QShlNsatSU8x16: case Iop_QShlNsatSU16x8: + case Iop_QShlNsatSU32x4: case Iop_QShlNsatSU64x2: + case Iop_QShlNsatSS8x16: case Iop_QShlNsatSS16x8: + case Iop_QShlNsatSS32x4: case Iop_QShlNsatSS64x2: case Iop_SHA256: case Iop_SHA512: case Iop_QandQShrNnarrow16Uto8Ux8: case Iop_QandQShrNnarrow32Uto16Ux4: diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h index b494afa885..9431acbbdd 100644 --- a/VEX/pub/libvex_ir.h +++ b/VEX/pub/libvex_ir.h @@ -919,9 +919,12 @@ typedef Iop_QShl8x8, Iop_QShl16x4, Iop_QShl32x2, Iop_QShl64x1, Iop_QSal8x8, Iop_QSal16x4, Iop_QSal32x2, Iop_QSal64x1, /* VECTOR x INTEGER SATURATING SHIFT */ - Iop_QShlN8Sx8, Iop_QShlN16Sx4, Iop_QShlN32Sx2, Iop_QShlN64Sx1, - Iop_QShlN8x8, Iop_QShlN16x4, Iop_QShlN32x2, Iop_QShlN64x1, - Iop_QSalN8x8, Iop_QSalN16x4, Iop_QSalN32x2, Iop_QSalN64x1, + Iop_QShlNsatSU8x8, Iop_QShlNsatSU16x4, + Iop_QShlNsatSU32x2, Iop_QShlNsatSU64x1, + Iop_QShlNsatUU8x8, Iop_QShlNsatUU16x4, + Iop_QShlNsatUU32x2, Iop_QShlNsatUU64x1, + Iop_QShlNsatSS8x8, Iop_QShlNsatSS16x4, + Iop_QShlNsatSS32x2, Iop_QShlNsatSS64x1, /* NARROWING (binary) -- narrow 2xI64 into 1xI64, hi half from left arg */ @@ -1534,9 +1537,12 @@ typedef Iop_QShl8x16, Iop_QShl16x8, Iop_QShl32x4, Iop_QShl64x2, Iop_QSal8x16, Iop_QSal16x8, Iop_QSal32x4, Iop_QSal64x2, /* VECTOR x INTEGER SATURATING SHIFT */ - Iop_QShlN8Sx16, Iop_QShlN16Sx8, Iop_QShlN32Sx4, Iop_QShlN64Sx2, - Iop_QShlN8x16, Iop_QShlN16x8, Iop_QShlN32x4, Iop_QShlN64x2, - Iop_QSalN8x16, Iop_QSalN16x8, Iop_QSalN32x4, Iop_QSalN64x2, + Iop_QShlNsatSU8x16, Iop_QShlNsatSU16x8, + Iop_QShlNsatSU32x4, Iop_QShlNsatSU64x2, + Iop_QShlNsatUU8x16, Iop_QShlNsatUU16x8, + Iop_QShlNsatUU32x4, Iop_QShlNsatUU64x2, + Iop_QShlNsatSS8x16, Iop_QShlNsatSS16x8, + Iop_QShlNsatSS32x4, Iop_QShlNsatSS64x2, /* VECTOR x VECTOR BIDIRECTIONAL SATURATING (& MAYBE ROUNDING) SHIFT */ /* The least significant 8 bits of each lane of the second -- 2.47.2