From 07f7615c181dd50fdae68e37b422053554eca1ec Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Tue, 5 Sep 2023 11:23:26 +0300 Subject: [PATCH] arc: Remove obsolete mbbit-peephole option and unused patterns. gcc/ * common/config/arc/arc-common.cc (arc_option_optimization_table): Remove mbbit_peephole. * config/arc/arc.md (UNSPEC_ARC_DIRECT): Remove. (store_direct): Likewise. (BBIT peephole2): Likewise. * config/arc/arc.opt (mbbit-peephole): Ignore option. * doc/invoke.texi (mbbit-peephole): Update document. Signed-off-by: Claudiu Zissulescu --- gcc/common/config/arc/arc-common.cc | 1 - gcc/config/arc/arc.md | 31 ----------------------------- gcc/config/arc/arc.opt | 4 ++-- gcc/doc/invoke.texi | 2 +- 4 files changed, 3 insertions(+), 35 deletions(-) diff --git a/gcc/common/config/arc/arc-common.cc b/gcc/common/config/arc/arc-common.cc index 95f5dd612011..3fd66e1f6b59 100644 --- a/gcc/common/config/arc/arc-common.cc +++ b/gcc/common/config/arc/arc-common.cc @@ -46,7 +46,6 @@ static const struct default_options arc_option_optimization_table[] = { { OPT_LEVELS_ALL, OPT_msize_level_, NULL, 1 }, { OPT_LEVELS_ALL, OPT_mearly_cbranchsi, NULL, 1 }, - { OPT_LEVELS_ALL, OPT_mbbit_peephole, NULL, 1 }, { OPT_LEVELS_SIZE, OPT_ftree_loop_optimize, NULL, 0}, { OPT_LEVELS_SIZE, OPT_fmove_loop_invariants, NULL, 0}, { OPT_LEVELS_SIZE, OPT_fbranch_count_reg, NULL, 0}, diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index a4e77a207bf7..d401e600f42b 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -3589,37 +3589,6 @@ archs4x, archs4xd" (set_attr "type" "compare") (set_attr "length" "*,4")]) -; combine suffers from 'simplifications' that replace a one-bit zero -; extract with a shift if it can prove that the upper bits are zero. -; arc_reorg sees the code after sched2, which can have caused our -; inputs to be clobbered even if they were not clobbered before. -; Therefore, add a third way to convert btst / b{eq,ne} to bbit{0,1} -; OTOH, this is somewhat marginal, and can leat to out-of-range -; bbit (i.e. bad scheduling) and missed conditional execution, -; so make this an option. -(define_peephole2 - [(set (reg:CC_ZN CC_REG) - (compare:CC_ZN - (zero_extract:SI (match_operand:SI 0 "register_operand" "") - (const_int 1) - (match_operand:SI 1 "nonmemory_operand" "")) - (const_int 0))) - (set (pc) - (if_then_else (match_operator 3 "equality_comparison_operator" - [(reg:CC_ZN CC_REG) (const_int 0)]) - (label_ref (match_operand 2 "" "")) - (pc)))] - "TARGET_BBIT_PEEPHOLE && peep2_regno_dead_p (2, CC_REG)" - [(parallel [(set (pc) - (if_then_else - (match_op_dup 3 - [(zero_extract:SI (match_dup 0) - (const_int 1) (match_dup 1)) - (const_int 0)]) - (label_ref (match_dup 2)) - (pc))) - (clobber (reg:CC_ZN CC_REG))])]) - (define_insn "*cmpsi_cc_z_insn" [(set (reg:CC_Z CC_REG) (compare:CC_Z (match_operand:SI 0 "register_operand" "q,c") diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index 273667c9b588..4af901f26191 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -322,8 +322,8 @@ Target Var(TARGET_EARLY_CBRANCHSI) Enable pre-reload use of cbranchsi pattern. mbbit-peephole -Target Var(TARGET_BBIT_PEEPHOLE) -Enable bbit peephole2. +Target Ignore +Does nothing. Preserved for backward compatibility. mcase-vector-pcrel Target Var(TARGET_CASE_VECTOR_PC_RELATIVE) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 435fb2fba992..33befee7d6b0 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21603,7 +21603,7 @@ Enable the use of pre/post modify with register displacement. @opindex mbbit-peephole @item -mbbit-peephole -Enable bbit peephole2. +Does nothing. Preserved for backward compatibility. @opindex mno-brcc @item -mno-brcc -- 2.47.2