From 08a0b6dabd76c8ca4366a59c2fdcd1ef8f8b1cb9 Mon Sep 17 00:00:00 2001 From: Pan Li Date: Fri, 6 Jun 2025 10:03:50 +0800 Subject: [PATCH] RISC-V: Reconcile the existing test for vdivu.vx combine Some existing vdiv related test need some adjust for the asm check due to cost model. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Adjust the asm check for vdivu. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c index 4685ed22a78..a8be5edcc70 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c @@ -5,8 +5,8 @@ /* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ /* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ /* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */ /* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c index 59c48d2d9ba..7feee0ec154 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c @@ -5,8 +5,8 @@ /* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ /* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ /* Division by constant is done by calculating a reciprocal and then multiplying. Hence we do not expect 6 vfdivs. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c index b574dc42182..766b17fc37d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c @@ -5,8 +5,8 @@ /* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ /* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ /* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */ /* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c index 9b46c6be0ef..c59c66439f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c @@ -5,8 +5,8 @@ /* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ /* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ /* Division by constant is done by calculating a reciprocal and then multiplying. Hence we do not expect 6 vfdivs. */ -- 2.47.2