From 0975002be52bd21196b868707ed1415cf1c45b98 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Thu, 22 Jan 2026 16:28:36 -0600 Subject: [PATCH] gpu: nova-core: rename Imem to ImemSecure Rename FalconMem::Imem to ImemSecure to indicate that it references Secure Instruction Memory. This change has no functional impact. On Falcon cores, pages in instruction memory can be tagged as Secure or Non-Secure. For GA102 and later, only Secure is used, which is why FalconMem::Imem seems appropriate. However, Turing firmware images can also contain non-secure sections, and so FalconMem needs to support that. By renaming Imem to ImemSec now, future patches for Turing support will be simpler. Nouveau uses the term "IMEM" to refer both to the Instruction Memory block on Falcon cores as well as to the images of secure firmware uploaded to part of IMEM. OpenRM uses the terms "ImemSec" and "ImemNs" instead, and uses "IMEM" just to refer to the physical memory device. Renaming these terms allows us to align with OpenRM, avoid confusion between IMEM and ImemSec, and makes future patches simpler. Signed-off-by: Timur Tabi Reviewed-by: John Hubbard Reviewed-by: Gary Guo Acked-by: Danilo Krummrich Link: https://patch.msgid.link/20260122222848.2555890-2-ttabi@nvidia.com Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/falcon.rs | 20 +++++++++++++------- drivers/gpu/nova-core/firmware/booter.rs | 12 ++++++------ drivers/gpu/nova-core/firmware/fwsec.rs | 2 +- 3 files changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 46b02c8a591e5..310d4e75bad31 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -240,8 +240,8 @@ impl From for bool { /// Different types of memory present in a falcon core. #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub(crate) enum FalconMem { - /// Instruction Memory. - Imem, + /// Secure Instruction Memory. + ImemSecure, /// Data Memory. Dmem, } @@ -348,8 +348,8 @@ pub(crate) struct FalconBromParams { /// Trait for providing load parameters of falcon firmwares. pub(crate) trait FalconLoadParams { - /// Returns the load parameters for `IMEM`. - fn imem_load_params(&self) -> FalconLoadTarget; + /// Returns the load parameters for Secure `IMEM`. + fn imem_sec_load_params(&self) -> FalconLoadTarget; /// Returns the load parameters for `DMEM`. fn dmem_load_params(&self) -> FalconLoadTarget; @@ -460,7 +460,7 @@ impl Falcon { // // For DMEM we can fold the start offset into the DMA handle. let (src_start, dma_start) = match target_mem { - FalconMem::Imem => (load_offsets.src_start, fw.dma_handle()), + FalconMem::ImemSecure => (load_offsets.src_start, fw.dma_handle()), FalconMem::Dmem => ( 0, fw.dma_handle_with_offset(load_offsets.src_start.into_safe_cast())?, @@ -517,7 +517,7 @@ impl Falcon { let cmd = regs::NV_PFALCON_FALCON_DMATRFCMD::default() .set_size(DmaTrfCmdSize::Size256B) - .set_imem(target_mem == FalconMem::Imem) + .set_imem(target_mem == FalconMem::ImemSecure) .set_sec(if sec { 1 } else { 0 }); for pos in (0..num_transfers).map(|i| i * DMA_LEN) { @@ -552,7 +552,13 @@ impl Falcon { .set_mem_type(FalconFbifMemType::Physical) }); - self.dma_wr(bar, fw, FalconMem::Imem, fw.imem_load_params(), true)?; + self.dma_wr( + bar, + fw, + FalconMem::ImemSecure, + fw.imem_sec_load_params(), + true, + )?; self.dma_wr(bar, fw, FalconMem::Dmem, fw.dmem_load_params(), true)?; self.hal.program_brom(self, bar, &fw.brom_params())?; diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-core/firmware/booter.rs index f107f753214a1..096cd01dbc9d0 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -251,8 +251,8 @@ impl<'a> FirmwareSignature for BooterSignature<'a> {} /// The `Booter` loader firmware, responsible for loading the GSP. pub(crate) struct BooterFirmware { - // Load parameters for `IMEM` falcon memory. - imem_load_target: FalconLoadTarget, + // Load parameters for Secure `IMEM` falcon memory. + imem_sec_load_target: FalconLoadTarget, // Load parameters for `DMEM` falcon memory. dmem_load_target: FalconLoadTarget, // BROM falcon parameters. @@ -354,7 +354,7 @@ impl BooterFirmware { }; Ok(Self { - imem_load_target: FalconLoadTarget { + imem_sec_load_target: FalconLoadTarget { src_start: app0.offset, dst_start: 0, len: app0.len, @@ -371,8 +371,8 @@ impl BooterFirmware { } impl FalconLoadParams for BooterFirmware { - fn imem_load_params(&self) -> FalconLoadTarget { - self.imem_load_target.clone() + fn imem_sec_load_params(&self) -> FalconLoadTarget { + self.imem_sec_load_target.clone() } fn dmem_load_params(&self) -> FalconLoadTarget { @@ -384,7 +384,7 @@ impl FalconLoadParams for BooterFirmware { } fn boot_addr(&self) -> u32 { - self.imem_load_target.src_start + self.imem_sec_load_target.src_start } } diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-core/firmware/fwsec.rs index b28e34d279f46..6a2f5a0d4b15a 100644 --- a/drivers/gpu/nova-core/firmware/fwsec.rs +++ b/drivers/gpu/nova-core/firmware/fwsec.rs @@ -224,7 +224,7 @@ pub(crate) struct FwsecFirmware { } impl FalconLoadParams for FwsecFirmware { - fn imem_load_params(&self) -> FalconLoadTarget { + fn imem_sec_load_params(&self) -> FalconLoadTarget { FalconLoadTarget { src_start: 0, dst_start: self.desc.imem_phys_base, -- 2.47.3