From 0a138a2cfd4e4210da1fe0795f4bf8e9cb5e341c Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 18 Sep 2025 08:44:47 -0700 Subject: [PATCH] arm64: dts: imx8mp-venice-gw702x: reduce RGMII CLK drive strength The i.MX8M Plus EQOS RGMII tracelength is less than 1in and does not require a x6 drive strength. Reduce the CLK drive strength to x1 for lower emissions. Additionally since TXC is not a high frequency clock, use slow slew rate (FSEL=0) for lower emmissions and improved signal quality. Signed-off-by: Tim Harvey Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi index a1232a4f84853..dd9eeb3479fdf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi @@ -462,7 +462,7 @@ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x0 >; }; -- 2.47.3