From 0a325d0b5c863e13ddf7a009e101b91852e3d6e1 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 24 Feb 2026 17:19:24 -0800 Subject: [PATCH] 6.19-stable patches added patches: net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch --- ...loongson-set-clk_csr_i-to-100-150mhz.patch | 39 +++++++++++++++++++ queue-6.19/series | 1 + 2 files changed, 40 insertions(+) create mode 100644 queue-6.19/net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch diff --git a/queue-6.19/net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch b/queue-6.19/net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch new file mode 100644 index 0000000000..5107dd7d03 --- /dev/null +++ b/queue-6.19/net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch @@ -0,0 +1,39 @@ +From e1aa5ef892fb4fa9014a25e87b64b97347919d37 Mon Sep 17 00:00:00 2001 +From: Huacai Chen +Date: Tue, 3 Feb 2026 14:29:01 +0800 +Subject: net: stmmac: dwmac-loongson: Set clk_csr_i to 100-150MHz + +From: Huacai Chen + +commit e1aa5ef892fb4fa9014a25e87b64b97347919d37 upstream. + +Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000 +and LS2K1000/2000/3000) are copy & paste from other drivers. In fact, +Loongson STMMAC use 125MHz clocks and need 62 freq division to within +2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i +to 100-150MHz, otherwise some PHYs may link fail. + +Cc: stable@vger.kernel.org +Fixes: 30bba69d7db40e7 ("stmmac: pci: Add dwmac support for Loongson") +Signed-off-by: Hongliang Wang +Signed-off-by: Huacai Chen +Link: https://patch.msgid.link/20260203062901.2158236-1-chenhuacai@loongson.cn +Signed-off-by: Jakub Kicinski +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c +@@ -91,8 +91,8 @@ static void loongson_default_data(struct + /* Get bus_id, this can be overwritten later */ + plat->bus_id = pci_dev_id(pdev); + +- /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ +- plat->clk_csr = STMMAC_CSR_20_35M; ++ /* clk_csr_i = 100-150MHz & MDC = clk_csr_i/62 */ ++ plat->clk_csr = STMMAC_CSR_100_150M; + plat->core_type = DWMAC_CORE_GMAC; + plat->force_sf_dma_mode = 1; + diff --git a/queue-6.19/series b/queue-6.19/series index 3a613a2cc3..e78cfb36ff 100644 --- a/queue-6.19/series +++ b/queue-6.19/series @@ -778,3 +778,4 @@ alsa-hda-realtek-add-quirk-for-samsung-galaxy-book3-pro-360-np965qfg.patch drm-exynos-vidi-use-priv-vidi_dev-for-ctx-lookup-in-vidi_connection_ioctl.patch drm-exynos-vidi-fix-to-avoid-directly-dereferencing-user-pointer.patch drivers-hv-vmbus-use-kthread-for-vmbus-interrupts-on-preempt_rt.patch +net-stmmac-dwmac-loongson-set-clk_csr_i-to-100-150mhz.patch -- 2.47.3