From 0ac37563fa41c72e499abd620c652ba5debe7fb9 Mon Sep 17 00:00:00 2001 From: Juzhe-Zhong Date: Tue, 30 Jan 2024 09:19:06 +0800 Subject: [PATCH] RISC-V: Fix regression Due to recent middle-end loop vectorizer changes, these tests have regression and the changes are reasonable. Adapt test to fix the regression. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Adapt test. * gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mod-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/shift-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/shift-2.c: Ditto. --- .../gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c index befa4b85e8fb..d5348855aa03 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c @@ -4,5 +4,5 @@ #include "shift-template.h" /* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvsrl\.vv} 2 } } */ /* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c index 976b29fa3565..a533dc79bc09 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c @@ -4,5 +4,5 @@ #include "shift-template.h" /* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvsrl\.vv} 2 } } */ /* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c index 57bbf8fbc683..17d2784b90dc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c @@ -53,5 +53,5 @@ DEF_OP_VV (mod, 128, int64_t, %) DEF_OP_VV (mod, 256, int64_t, %) DEF_OP_VV (mod, 512, int64_t, %) -/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ +/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 47 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c index cb5a1dbc9ffa..ee8da2573c70 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c @@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, int64_t, >>) DEF_OP_VV (shift, 256, int64_t, >>) DEF_OP_VV (shift, 512, int64_t, >>) -/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ +/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 35 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c index e626a52c2d88..ebd5575f2672 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c @@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, uint64_t, >>) DEF_OP_VV (shift, 256, uint64_t, >>) DEF_OP_VV (shift, 512, uint64_t, >>) -/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ -- 2.47.2